From 0944d0e9b0a894ed1823d09c639110864f4dbd94 Mon Sep 17 00:00:00 2001 From: Dustin Crossman Date: Mon, 10 Aug 2020 16:54:40 -0700 Subject: [PATCH 1/5] Update CYSBSYSKIT_01 bsp. --- .../GeneratedSource/cycfg.c | 9 +- .../GeneratedSource/cycfg.h | 3 +- .../GeneratedSource/cycfg.timestamp | 2 +- .../GeneratedSource/cycfg_notices.h | 2 +- .../GeneratedSource/cycfg_peripherals.c | 49 - .../GeneratedSource/cycfg_peripherals.h | 72 - .../GeneratedSource/cycfg_pins.c | 316 +--- .../GeneratedSource/cycfg_pins.h | 258 +--- .../GeneratedSource/cycfg_routing.c | 2 +- .../GeneratedSource/cycfg_routing.h | 8 +- .../GeneratedSource/cycfg_system.c | 1320 ++++++++++++----- .../GeneratedSource/cycfg_system.h | 14 +- .../cyreservedresources.list | 2 +- .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 154 +- .../TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c | 26 +- .../TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h | 7 +- .../TARGET_CYSBSYSKIT_01/cybsp_types.h | 97 +- .../TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct | 6 +- .../TOOLCHAIN_ARM/startup_psoc6_02_cm4.S | 2 - .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld | 6 +- .../TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf | 8 +- 21 files changed, 1168 insertions(+), 1195 deletions(-) delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index b6ffbbf20d3..c4c420e83b5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -5,7 +5,7 @@ * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* Device Support Library (../../../psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -28,8 +28,7 @@ void init_cycfg_all(void) { - init_cycfg_system(); - init_cycfg_routing(); - init_cycfg_peripherals(); - init_cycfg_pins(); + init_cycfg_system(); + init_cycfg_routing(); + init_cycfg_pins(); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 892bfa35b69..8492a5cae88 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -5,7 +5,7 @@ * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* Device Support Library (../../../psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -34,7 +34,6 @@ extern "C" { #include "cycfg_notices.h" #include "cycfg_system.h" #include "cycfg_routing.h" -#include "cycfg_peripherals.h" #include "cycfg_pins.h" void init_cycfg_all(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp index 8619de15427..7539ee57488 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -5,7 +5,7 @@ * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* Device Support Library (../../../psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 3587d0e5f0e..34634762aeb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -6,7 +6,7 @@ * design. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* Device Support Library (../../../psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c deleted file mode 100644 index ba07b3cc9c7..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ /dev/null @@ -1,49 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_peripherals.c -* -* Description: -* Peripheral Hardware Block configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_peripherals.h" - -const cy_stc_smif_config_t CYBSP_QSPI_config = { - .mode = (uint32_t)CY_SMIF_NORMAL, - .deselectDelay = CYBSP_QSPI_DESELECT_DELAY, - .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, - .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, -}; -#if defined (CY_USING_HAL) -const cyhal_resource_inst_t CYBSP_QSPI_obj = { - .type = CYHAL_RSC_SMIF, - .block_num = 0U, - .channel_num = 0U, -}; -#endif //defined (CY_USING_HAL) - - -void init_cycfg_peripherals(void) -{ -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h deleted file mode 100644 index 4753d4284af..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ /dev/null @@ -1,72 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_peripherals.h -* -* Description: -* Peripheral Hardware Block configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_PERIPHERALS_H) -#define CYCFG_PERIPHERALS_H - -#include "cycfg_notices.h" -#include "cy_smif.h" -#include "cycfg_qspi_memslot.h" -#if defined (CY_USING_HAL) -#include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) - -#if defined(__cplusplus) -extern "C" { -#endif - -#define CYBSP_QSPI_ENABLED 1U -#define CYBSP_QSPI_HW SMIF0 -#define CYBSP_QSPI_IRQ smif_interrupt_IRQn -#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL) -#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL) -#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL) -#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL) -#define CYBSP_QSPI_DATALINES0_1 (1UL) -#define CYBSP_QSPI_DATALINES2_3 (1UL) -#define CYBSP_QSPI_DATALINES4_5 (0UL) -#define CYBSP_QSPI_DATALINES6_7 (0UL) -#define CYBSP_QSPI_SS0 (1UL) -#define CYBSP_QSPI_SS1 (0UL) -#define CYBSP_QSPI_SS2 (0UL) -#define CYBSP_QSPI_SS3 (0UL) -#define CYBSP_QSPI_DESELECT_DELAY 7 - -extern const cy_stc_smif_config_t CYBSP_QSPI_config; -#if defined (CY_USING_HAL) -extern const cyhal_resource_inst_t CYBSP_QSPI_obj; -#endif //defined (CY_USING_HAL) - -void init_cycfg_peripherals(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_PERIPHERALS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 5df98a82059..a570f45dec0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -5,7 +5,7 @@ * Pin configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* Device Support Library (../../../psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -26,277 +26,65 @@ #include "cycfg_pins.h" -const cy_stc_gpio_pin_config_t CYBSP_SW1_config = { - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_SW1_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) -const cyhal_resource_inst_t CYBSP_SW1_obj = { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_SW1_PORT_NUM, - .channel_num = CYBSP_SW1_PIN, -}; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_LED1_config = { - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_LED1_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) -const cyhal_resource_inst_t CYBSP_LED1_obj = { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_LED1_PORT_NUM, - .channel_num = CYBSP_LED1_PIN, -}; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config = { - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SS0_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) -const cyhal_resource_inst_t CYBSP_QSPI_SS0_obj = { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SS0_PORT_NUM, - .channel_num = CYBSP_QSPI_SS0_PIN, -}; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config = { - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_DATA3_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) -const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj = { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_DATA3_PORT_NUM, - .channel_num = CYBSP_QSPI_DATA3_PIN, -}; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config = { - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_DATA2_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) -const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj = { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_DATA2_PORT_NUM, - .channel_num = CYBSP_QSPI_DATA2_PIN, -}; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config = { - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_DATA1_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) -const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj = { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_DATA1_PORT_NUM, - .channel_num = CYBSP_QSPI_DATA1_PIN, -}; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config = { - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG, - .hsiom = CYBSP_QSPI_DATA0_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) -const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj = { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_DATA0_PORT_NUM, - .channel_num = CYBSP_QSPI_DATA0_PIN, -}; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config = { - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_QSPI_SPI_CLOCK_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) -const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj = { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_QSPI_SPI_CLOCK_PORT_NUM, - .channel_num = CYBSP_QSPI_SPI_CLOCK_PIN, -}; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = { - .outVal = 1, - .driveMode = CY_GPIO_DM_PULLUP, - .hsiom = CYBSP_SWDIO_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) -const cyhal_resource_inst_t CYBSP_SWDIO_obj = { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_SWDIO_PORT_NUM, - .channel_num = CYBSP_SWDIO_PIN, -}; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = { - .outVal = 1, - .driveMode = CY_GPIO_DM_PULLDOWN, - .hsiom = CYBSP_SWDCK_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) -const cyhal_resource_inst_t CYBSP_SWDCK_obj = { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_SWDCK_PORT_NUM, - .channel_num = CYBSP_SWDCK_PIN, -}; +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = CYBSP_SWDIO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWDIO_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWDIO_PORT_NUM, + .channel_num = CYBSP_SWDIO_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLDOWN, + .hsiom = CYBSP_SWDCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWDCK_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWDCK_PORT_NUM, + .channel_num = CYBSP_SWDCK_PIN, + }; #endif //defined (CY_USING_HAL) void init_cycfg_pins(void) { - Cy_GPIO_Pin_Init(CYBSP_SW1_PORT, CYBSP_SW1_PIN, &CYBSP_SW1_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SW1_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_LED1_PORT, CYBSP_LED1_PIN, &CYBSP_LED1_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_LED1_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SS0_PORT, CYBSP_QSPI_SS0_PIN, &CYBSP_QSPI_SS0_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SS0_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA3_PORT, CYBSP_QSPI_DATA3_PIN, &CYBSP_QSPI_DATA3_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA3_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA2_PORT, CYBSP_QSPI_DATA2_PIN, &CYBSP_QSPI_DATA2_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA2_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA1_PORT, CYBSP_QSPI_DATA1_PIN, &CYBSP_QSPI_DATA1_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA1_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA0_PORT, CYBSP_QSPI_DATA0_PIN, &CYBSP_QSPI_DATA0_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA0_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_QSPI_SPI_CLOCK_PORT, CYBSP_QSPI_SPI_CLOCK_PIN, &CYBSP_QSPI_SPI_CLOCK_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_QSPI_SPI_CLOCK_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); + Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); #endif //defined (CY_USING_HAL) - Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); + Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); + cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index aaf3b7ae4d6..fc29eef18de 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -5,7 +5,7 @@ * Pin configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* Device Support Library (../../../psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -29,207 +29,15 @@ #include "cycfg_notices.h" #include "cy_gpio.h" +#include "cycfg_routing.h" #if defined (CY_USING_HAL) -#include "cyhal_hwmgr.h" + #include "cyhal_hwmgr.h" #endif //defined (CY_USING_HAL) -#include "cycfg_routing.h" #if defined(__cplusplus) extern "C" { #endif -#define CYBSP_SW1_ENABLED 1U -#define CYBSP_SW1_PORT GPIO_PRT0 -#define CYBSP_SW1_PORT_NUM 0U -#define CYBSP_SW1_PIN 4U -#define CYBSP_SW1_NUM 4U -#define CYBSP_SW1_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_SW1_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_0_pin_4_HSIOM -#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_SW1_HSIOM ioss_0_port_0_pin_4_HSIOM -#define CYBSP_SW1_IRQ ioss_interrupts_gpio_0_IRQn -#if defined (CY_USING_HAL) -#define CYBSP_SW1_HAL_PORT_PIN P0_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_SW1_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_SW1_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_SW1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_LED1_ENABLED 1U -#define CYBSP_LED1_PORT GPIO_PRT11 -#define CYBSP_LED1_PORT_NUM 11U -#define CYBSP_LED1_PIN 1U -#define CYBSP_LED1_NUM 1U -#define CYBSP_LED1_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_LED1_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_1_HSIOM -#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_LED1_HSIOM ioss_0_port_11_pin_1_HSIOM -#define CYBSP_LED1_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) -#define CYBSP_LED1_HAL_PORT_PIN P11_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_LED1_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_LED1_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_LED1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SS0_ENABLED 1U -#define CYBSP_QSPI_SS0_PORT GPIO_PRT11 -#define CYBSP_QSPI_SS0_PORT_NUM 11U -#define CYBSP_QSPI_SS0_PIN 2U -#define CYBSP_QSPI_SS0_NUM 2U -#define CYBSP_QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SS0_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_2_HSIOM -#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM -#define CYBSP_QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_SS0_HAL_PORT_PIN P11_2 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_SS0_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_SS0_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_SS0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA3_ENABLED 1U -#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11 -#define CYBSP_QSPI_DATA3_PORT_NUM 11U -#define CYBSP_QSPI_DATA3_PIN 3U -#define CYBSP_QSPI_DATA3_NUM 3U -#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_DATA3_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_3_HSIOM -#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM -#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA3_HAL_PORT_PIN P11_3 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA3_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA2_ENABLED 1U -#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11 -#define CYBSP_QSPI_DATA2_PORT_NUM 11U -#define CYBSP_QSPI_DATA2_PIN 4U -#define CYBSP_QSPI_DATA2_NUM 4U -#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_DATA2_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_4_HSIOM -#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM -#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA2_HAL_PORT_PIN P11_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA2_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA1_ENABLED 1U -#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11 -#define CYBSP_QSPI_DATA1_PORT_NUM 11U -#define CYBSP_QSPI_DATA1_PIN 5U -#define CYBSP_QSPI_DATA1_NUM 5U -#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_DATA1_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_5_HSIOM -#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM -#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA1_HAL_PORT_PIN P11_5 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA1_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA0_ENABLED 1U -#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11 -#define CYBSP_QSPI_DATA0_PORT_NUM 11U -#define CYBSP_QSPI_DATA0_PIN 6U -#define CYBSP_QSPI_DATA0_NUM 6U -#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG -#define CYBSP_QSPI_DATA0_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_6_HSIOM -#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM -#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA0_HAL_PORT_PIN P11_6 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA0_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_DATA0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_QSPI_SPI_CLOCK_ENABLED 1U -#define CYBSP_QSPI_SPI_CLOCK_PORT GPIO_PRT11 -#define CYBSP_QSPI_SPI_CLOCK_PORT_NUM 11U -#define CYBSP_QSPI_SPI_CLOCK_PIN 7U -#define CYBSP_QSPI_SPI_CLOCK_NUM 7U -#define CYBSP_QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_QSPI_SPI_CLOCK_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_7_HSIOM -#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM -#define CYBSP_QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_SPI_CLOCK_HAL_PORT_PIN P11_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_SPI_CLOCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_SPI_CLOCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_QSPI_SPI_CLOCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) #define CYBSP_SWDIO_ENABLED 1U #define CYBSP_SWDIO_PORT GPIO_PRT6 #define CYBSP_SWDIO_PORT_NUM 6U @@ -238,21 +46,24 @@ extern "C" { #define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP #define CYBSP_SWDIO_INIT_DRIVESTATE 1 #ifndef ioss_0_port_6_pin_6_HSIOM -#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO + #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM #define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn #if defined (CY_USING_HAL) -#define CYBSP_SWDIO_HAL_PORT_PIN P6_6 + #define CYBSP_SWDIO_HAL_PORT_PIN P6_6 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO P6_6 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) -#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) -#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) -#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP + #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP #endif //defined (CY_USING_HAL) #define CYBSP_SWDCK_ENABLED 1U #define CYBSP_SWDCK_PORT GPIO_PRT6 @@ -262,62 +73,33 @@ extern "C" { #define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN #define CYBSP_SWDCK_INIT_DRIVESTATE 1 #ifndef ioss_0_port_6_pin_7_HSIOM -#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO + #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM #define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn #if defined (CY_USING_HAL) -#define CYBSP_SWDCK_HAL_PORT_PIN P6_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) -#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_SWDCK_HAL_PORT_PIN P6_7 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) -#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL + #define CYBSP_SWDCK P6_7 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) -#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN -#endif //defined (CY_USING_HAL) - -extern const cy_stc_gpio_pin_config_t CYBSP_SW1_config; -#if defined (CY_USING_HAL) -extern const cyhal_resource_inst_t CYBSP_SW1_obj; + #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_LED1_config; #if defined (CY_USING_HAL) -extern const cyhal_resource_inst_t CYBSP_LED1_obj; + #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config; #if defined (CY_USING_HAL) -extern const cyhal_resource_inst_t CYBSP_QSPI_SS0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config; -#if defined (CY_USING_HAL) -extern const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config; -#if defined (CY_USING_HAL) -extern const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config; -#if defined (CY_USING_HAL) -extern const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config; -#if defined (CY_USING_HAL) -extern const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config; -#if defined (CY_USING_HAL) -extern const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj; + #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN #endif //defined (CY_USING_HAL) + extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config; #if defined (CY_USING_HAL) -extern const cyhal_resource_inst_t CYBSP_SWDIO_obj; + extern const cyhal_resource_inst_t CYBSP_SWDIO_obj; #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config; #if defined (CY_USING_HAL) -extern const cyhal_resource_inst_t CYBSP_SWDCK_obj; + extern const cyhal_resource_inst_t CYBSP_SWDCK_obj; #endif //defined (CY_USING_HAL) void init_cycfg_pins(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index a8de1e3d5fa..50ff9533f8f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -5,7 +5,7 @@ * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* Device Support Library (../../../psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index ad033c5a7a7..fb7532ce6e8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -5,7 +5,7 @@ * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* Device Support Library (../../../psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -34,12 +34,6 @@ extern "C" { #include "cycfg_notices.h" void init_cycfg_routing(void); #define init_cycfg_connectivity() init_cycfg_routing() -#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0 -#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3 -#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2 -#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 -#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 -#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index be7b6c59468..a84bf36bc85 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -5,7 +5,7 @@ * System configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* Device Support Library (../../../psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -32,417 +32,995 @@ #define CY_CFG_SYSCLK_FLL_ERROR 4 #define CY_CFG_SYSCLK_WCO_ERROR 5 #define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE CY_SYSTICK_CLOCK_SOURCE_CLK_LF #define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_CLKLF #define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 +#define CY_CFG_SYSCLK_CLKFAST_DIVIDER 0 #define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE #define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL #define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 #define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF2_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_2 #define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL #define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 #define CY_CFG_SYSCLK_CLKHF4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF4_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE #define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL #define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1 #define CY_CFG_SYSCLK_ILO_ENABLED 1 +#define CY_CFG_SYSCLK_ILO_HIBERNATE true #define CY_CFG_SYSCLK_IMO_ENABLED 1 #define CY_CFG_SYSCLK_CLKLF_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL #define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 0UL #define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 0 #define CY_CFG_SYSCLK_PLL0_ENABLED 1 +#define CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV 25 +#define CY_CFG_SYSCLK_PLL0_REFERENCE_DIV 1 +#define CY_CFG_SYSCLK_PLL0_OUTPUT_DIV 2 +#define CY_CFG_SYSCLK_PLL0_LF_MODE false +#define CY_CFG_SYSCLK_PLL0_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO +#define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 100000000 #define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 +#define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 0 #define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1 +#define CY_CFG_SYSCLK_CLKTIMER_SOURCE CY_SYSCLK_CLKTIMER_IN_IMO +#define CY_CFG_SYSCLK_CLKTIMER_DIVIDER 0U +#if defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) + static cy_stc_pra_system_config_t srss_0_clock_0_secureConfig; +#endif //defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) #if defined (CY_USING_HAL) -const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = { - .type = CYHAL_RSC_CLKPATH, - .block_num = 0U, - .channel_num = 0U, -}; + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 0U, + .channel_num = 0U, + }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) -const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = { - .type = CYHAL_RSC_CLKPATH, - .block_num = 1U, - .channel_num = 0U, -}; + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 1U, + .channel_num = 0U, + }; #endif //defined (CY_USING_HAL) -static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = { - .feedbackDiv = 25, - .referenceDiv = 1, - .outputDiv = 2, - .lfMode = false, - .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, -}; +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = + { + .feedbackDiv = 25, + .referenceDiv = 1, + .outputDiv = 2, + .lfMode = false, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, + }; +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) __WEAK void cycfg_ClockStartupError(uint32_t error) { (void)error; /* Suppress the compiler warning */ - while (1); -} -__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit() -{ - Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF); -} -__STATIC_INLINE void Cy_SysClk_ClkBakInit() -{ - Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF); -} -__STATIC_INLINE void Cy_SysClk_ClkFastInit() -{ - Cy_SysClk_ClkFastSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_ClkHf0Init() -{ - Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); - Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); -} -__STATIC_INLINE void Cy_SysClk_ClkHf2Init() -{ - Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH); - Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2); - Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2); -} -__STATIC_INLINE void Cy_SysClk_ClkHf4Init() -{ - Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH); - Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4); -} -__STATIC_INLINE void Cy_SysClk_IloInit() -{ - /* The WDT is unlocked in the default startup code */ - Cy_SysClk_IloEnable(); - Cy_SysClk_IloHibernateOn(true); -} -__STATIC_INLINE void Cy_SysClk_ClkLfInit() -{ - /* The WDT is unlocked in the default startup code */ - Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); -} -__STATIC_INLINE void Cy_SysClk_ClkPath0Init() -{ - Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPath1Init() -{ - Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); -} -__STATIC_INLINE void Cy_SysClk_ClkPeriInit() -{ - Cy_SysClk_ClkPeriSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_Pll0Init() -{ - if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) { - cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); - } - if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) { - cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); - } -} -__STATIC_INLINE void Cy_SysClk_ClkSlowInit() -{ - Cy_SysClk_ClkSlowSetDivider(0U); -} -__STATIC_INLINE void Cy_SysClk_ClkTimerInit() -{ - Cy_SysClk_ClkTimerDisable(); - Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO); - Cy_SysClk_ClkTimerSetDivider(0U); - Cy_SysClk_ClkTimerEnable(); + while(1); } +#if defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) + __STATIC_INLINE void init_cycfg_secure_struct(cy_stc_pra_system_config_t * secure_config) + { + #ifdef CY_CFG_PWR_ENABLED + secure_config->powerEnable = CY_CFG_PWR_ENABLED; + #endif /* CY_CFG_PWR_ENABLED */ + + #ifdef CY_CFG_PWR_USING_LDO + secure_config->ldoEnable = CY_CFG_PWR_USING_LDO; + #endif /* CY_CFG_PWR_USING_LDO */ + + #ifdef CY_CFG_PWR_USING_PMIC + secure_config->pmicEnable = CY_CFG_PWR_USING_PMIC; + #endif /* CY_CFG_PWR_USING_PMIC */ + + #ifdef CY_CFG_PWR_VBACKUP_USING_VDDD + secure_config->vBackupVDDDEnable = CY_CFG_PWR_VBACKUP_USING_VDDD; + #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ + + #ifdef CY_CFG_PWR_USING_ULP + secure_config->ulpEnable = CY_CFG_PWR_USING_ULP; + #endif /* CY_CFG_PWR_USING_ULP */ + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + secure_config->ecoEnable = CY_CFG_SYSCLK_ECO_ENABLED; + #endif /* CY_CFG_SYSCLK_ECO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + secure_config->extClkEnable = CY_CFG_SYSCLK_EXTCLK_ENABLED; + #endif /* CY_CFG_SYSCLK_EXTCLK_ENABLED */ + + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + secure_config->iloEnable = CY_CFG_SYSCLK_ILO_ENABLED; + #endif /* CY_CFG_SYSCLK_ILO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + secure_config->wcoEnable = CY_CFG_SYSCLK_WCO_ENABLED; + #endif /* CY_CFG_SYSCLK_WCO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + secure_config->fllEnable = CY_CFG_SYSCLK_FLL_ENABLED; + #endif /* CY_CFG_SYSCLK_FLL_ENABLED */ + + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + secure_config->pll0Enable = CY_CFG_SYSCLK_PLL0_ENABLED; + #endif /* CY_CFG_SYSCLK_PLL0_ENABLED */ + + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + secure_config->pll1Enable = CY_CFG_SYSCLK_PLL1_ENABLED; + #endif /* CY_CFG_SYSCLK_PLL1_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + secure_config->path0Enable = CY_CFG_SYSCLK_CLKPATH0_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH0_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + secure_config->path1Enable = CY_CFG_SYSCLK_CLKPATH1_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH1_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + secure_config->path2Enable = CY_CFG_SYSCLK_CLKPATH2_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH2_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + secure_config->path3Enable = CY_CFG_SYSCLK_CLKPATH3_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH3_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + secure_config->path4Enable = CY_CFG_SYSCLK_CLKPATH4_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH4_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + secure_config->path5Enable = CY_CFG_SYSCLK_CLKPATH5_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPATH5_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + secure_config->clkFastEnable = CY_CFG_SYSCLK_CLKFAST_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKFAST_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + secure_config->clkPeriEnable = CY_CFG_SYSCLK_CLKPERI_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPERI_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + secure_config->clkSlowEnable = CY_CFG_SYSCLK_CLKSLOW_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKSLOW_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_ENABLED + secure_config->clkHF0Enable = CY_CFG_SYSCLK_CLKHF0_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF0_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + secure_config->clkHF1Enable = CY_CFG_SYSCLK_CLKHF1_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF1_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + secure_config->clkHF2Enable = CY_CFG_SYSCLK_CLKHF2_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF2_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + secure_config->clkHF3Enable = CY_CFG_SYSCLK_CLKHF3_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF3_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + secure_config->clkHF4Enable = CY_CFG_SYSCLK_CLKHF4_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF4_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + secure_config->clkHF5Enable = CY_CFG_SYSCLK_CLKHF5_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKHF5_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + secure_config->clkPumpEnable = CY_CFG_SYSCLK_CLKPUMP_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKPUMP_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + secure_config->clkLFEnable = CY_CFG_SYSCLK_CLKLF_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKLF_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + secure_config->clkBakEnable = CY_CFG_SYSCLK_CLKBAK_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKBAK_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + secure_config->clkTimerEnable = CY_CFG_SYSCLK_CLKTIMER_ENABLED; + #endif /* CY_CFG_SYSCLK_CLKTIMER_ENABLED */ + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + #error Configuration Error : ALT SYSTICK cannot be enabled for Secure devices. + #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED */ + + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + secure_config->piloEnable = CY_CFG_SYSCLK_PILO_ENABLED; + #endif /* CY_CFG_SYSCLK_PILO_ENABLED */ + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + secure_config->clkAltHfEnable = CY_CFG_SYSCLK_ALTHF_ENABLED; + #endif /* CY_CFG_SYSCLK_ALTHF_ENABLED */ + + #ifdef CY_CFG_PWR_LDO_VOLTAGE + secure_config->ldoVoltage = CY_CFG_PWR_LDO_VOLTAGE; + #endif /* CY_CFG_PWR_LDO_VOLTAGE */ + + #ifdef CY_CFG_PWR_REGULATOR_MODE_MIN + secure_config->pwrCurrentModeMin = CY_CFG_PWR_REGULATOR_MODE_MIN; + #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */ + + #ifdef CY_CFG_PWR_BUCK_VOLTAGE + secure_config->buckVoltage = CY_CFG_PWR_BUCK_VOLTAGE; + #endif /* CY_CFG_PWR_BUCK_VOLTAGE */ + + #ifdef CY_CFG_SYSCLK_ECO_FREQ + secure_config->ecoFreqHz = CY_CFG_SYSCLK_ECO_FREQ; + #endif /* CY_CFG_SYSCLK_ECO_FREQ */ + + #ifdef CY_CFG_SYSCLK_ECO_CLOAD + secure_config->ecoLoad = CY_CFG_SYSCLK_ECO_CLOAD; + #endif /* CY_CFG_SYSCLK_ECO_CLOAD */ + + #ifdef CY_CFG_SYSCLK_ECO_ESR + secure_config->ecoEsr = CY_CFG_SYSCLK_ECO_ESR; + #endif /* CY_CFG_SYSCLK_ECO_ESR */ + + #ifdef CY_CFG_SYSCLK_ECO_DRIVE_LEVEL + secure_config->ecoDriveLevel = CY_CFG_SYSCLK_ECO_DRIVE_LEVEL; + #endif /* CY_CFG_SYSCLK_ECO_DRIVE_LEVEL */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PRT + secure_config->ecoInPort = CY_CFG_SYSCLK_ECO_GPIO_IN_PRT; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PRT */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT + secure_config->ecoOutPort = CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PIN + secure_config->ecoInPinNum = CY_CFG_SYSCLK_ECO_GPIO_IN_PIN; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PIN */ + + #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN + secure_config->ecoOutPinNum = CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN; + #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ + secure_config->extClkFreqHz = CY_CFG_SYSCLK_EXTCLK_FREQ; + #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PRT + secure_config->extClkPort = CY_CFG_SYSCLK_EXTCLK_GPIO_PRT; + #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PRT */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PIN + secure_config->extClkPinNum = CY_CFG_SYSCLK_EXTCLK_GPIO_PIN; + #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PIN */ + + #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM + secure_config->extClkHsiom = CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM; + #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM */ + + #ifdef CY_CFG_SYSCLK_ILO_HIBERNATE + secure_config->iloHibernateON = CY_CFG_SYSCLK_ILO_HIBERNATE; + #endif /* CY_CFG_SYSCLK_ILO_HIBERNATE */ + + #ifdef CY_CFG_SYSCLK_WCO_BYPASS + secure_config->bypassEnable = CY_CFG_SYSCLK_WCO_BYPASS; + #endif /* CY_CFG_SYSCLK_WCO_BYPASS */ + + #ifdef CY_CFG_SYSCLK_WCO_IN_PRT + secure_config->wcoInPort = CY_CFG_SYSCLK_WCO_IN_PRT; + #endif /* CY_CFG_SYSCLK_WCO_IN_PRT */ + + #ifdef CY_CFG_SYSCLK_WCO_OUT_PRT + secure_config->wcoOutPort = CY_CFG_SYSCLK_WCO_OUT_PRT; + #endif /* CY_CFG_SYSCLK_WCO_OUT_PRT */ + + #ifdef CY_CFG_SYSCLK_WCO_IN_PIN + secure_config->wcoInPinNum = CY_CFG_SYSCLK_WCO_IN_PIN; + #endif /* CY_CFG_SYSCLK_WCO_IN_PIN */ + + #ifdef CY_CFG_SYSCLK_WCO_OUT_PIN + secure_config->wcoOutPinNum = CY_CFG_SYSCLK_WCO_OUT_PIN; + #endif /* CY_CFG_SYSCLK_WCO_OUT_PIN */ + + #ifdef CY_CFG_SYSCLK_FLL_OUT_FREQ + secure_config->fllOutFreqHz = CY_CFG_SYSCLK_FLL_OUT_FREQ; + #endif /* CY_CFG_SYSCLK_FLL_OUT_FREQ */ + + #ifdef CY_CFG_SYSCLK_FLL_MULT + secure_config->fllMult = CY_CFG_SYSCLK_FLL_MULT; + #endif /* CY_CFG_SYSCLK_FLL_MULT */ + + #ifdef CY_CFG_SYSCLK_FLL_REFDIV + secure_config->fllRefDiv = CY_CFG_SYSCLK_FLL_REFDIV; + #endif /* CY_CFG_SYSCLK_FLL_REFDIV */ + + #ifdef CY_CFG_SYSCLK_FLL_CCO_RANGE + secure_config->fllCcoRange = CY_CFG_SYSCLK_FLL_CCO_RANGE; + #endif /* CY_CFG_SYSCLK_FLL_CCO_RANGE */ + + #ifdef CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV + secure_config->enableOutputDiv = CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV; + #endif /* CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV */ + + #ifdef CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE + secure_config->lockTolerance = CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE; + #endif /* CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE */ + + #ifdef CY_CFG_SYSCLK_FLL_IGAIN + secure_config->igain = CY_CFG_SYSCLK_FLL_IGAIN; + #endif /* CY_CFG_SYSCLK_FLL_IGAIN */ + + #ifdef CY_CFG_SYSCLK_FLL_PGAIN + secure_config->pgain = CY_CFG_SYSCLK_FLL_PGAIN; + #endif /* CY_CFG_SYSCLK_FLL_PGAIN */ + + #ifdef CY_CFG_SYSCLK_FLL_SETTLING_COUNT + secure_config->settlingCount = CY_CFG_SYSCLK_FLL_SETTLING_COUNT; + #endif /* CY_CFG_SYSCLK_FLL_SETTLING_COUNT */ + + #ifdef CY_CFG_SYSCLK_FLL_OUTPUT_MODE + secure_config->outputMode = CY_CFG_SYSCLK_FLL_OUTPUT_MODE; + #endif /* CY_CFG_SYSCLK_FLL_OUTPUT_MODE */ + + #ifdef CY_CFG_SYSCLK_FLL_CCO_FREQ + secure_config->ccoFreq = CY_CFG_SYSCLK_FLL_CCO_FREQ; + #endif /* CY_CFG_SYSCLK_FLL_CCO_FREQ */ + + #ifdef CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV + secure_config->pll0FeedbackDiv = CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV; + #endif /* CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL0_REFERENCE_DIV + secure_config->pll0ReferenceDiv = CY_CFG_SYSCLK_PLL0_REFERENCE_DIV; + #endif /* CY_CFG_SYSCLK_PLL0_REFERENCE_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_DIV + secure_config->pll0OutputDiv = CY_CFG_SYSCLK_PLL0_OUTPUT_DIV; + #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL0_LF_MODE + secure_config->pll0LfMode = CY_CFG_SYSCLK_PLL0_LF_MODE; + #endif /* CY_CFG_SYSCLK_PLL0_LF_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_MODE + secure_config->pll0OutputMode = CY_CFG_SYSCLK_PLL0_OUTPUT_MODE; + #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ + secure_config->pll0OutFreqHz = CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ; + #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ */ + + #ifdef CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV + secure_config->pll1FeedbackDiv = CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV; + #endif /* CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL1_REFERENCE_DIV + secure_config->pll1ReferenceDiv = CY_CFG_SYSCLK_PLL1_REFERENCE_DIV; + #endif /* CY_CFG_SYSCLK_PLL1_REFERENCE_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_DIV + secure_config->pll1OutputDiv = CY_CFG_SYSCLK_PLL1_OUTPUT_DIV; + #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_DIV */ + + #ifdef CY_CFG_SYSCLK_PLL1_LF_MODE + secure_config->pll1LfMode = CY_CFG_SYSCLK_PLL1_LF_MODE; + #endif /* CY_CFG_SYSCLK_PLL1_LF_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_MODE + secure_config->pll1OutputMode = CY_CFG_SYSCLK_PLL1_OUTPUT_MODE; + #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_MODE */ + + #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ + secure_config->pll1OutFreqHz = CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ; + #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ */ + + #ifdef CY_CFG_SYSCLK_CLKPATH0_SOURCE + secure_config->path0Src = CY_CFG_SYSCLK_CLKPATH0_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH0_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH1_SOURCE + secure_config->path1Src = CY_CFG_SYSCLK_CLKPATH1_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH1_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH2_SOURCE + secure_config->path2Src = CY_CFG_SYSCLK_CLKPATH2_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH2_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH3_SOURCE + secure_config->path3Src = CY_CFG_SYSCLK_CLKPATH3_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH3_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH4_SOURCE + secure_config->path4Src = CY_CFG_SYSCLK_CLKPATH4_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH4_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPATH5_SOURCE + secure_config->path5Src = CY_CFG_SYSCLK_CLKPATH5_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPATH5_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKFAST_DIVIDER + secure_config->clkFastDiv = CY_CFG_SYSCLK_CLKFAST_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKFAST_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKPERI_DIVIDER + secure_config->clkPeriDiv = CY_CFG_SYSCLK_CLKPERI_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKPERI_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKSLOW_DIVIDER + secure_config->clkSlowDiv = CY_CFG_SYSCLK_CLKSLOW_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKSLOW_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_CLKPATH + secure_config->hf0Source = CY_CFG_SYSCLK_CLKHF0_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF0_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_DIVIDER + secure_config->hf0Divider = CY_CFG_SYSCLK_CLKHF0_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF0_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ + secure_config->hf0OutFreqMHz = CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_CLKPATH + secure_config->hf1Source = CY_CFG_SYSCLK_CLKHF1_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF1_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_DIVIDER + secure_config->hf1Divider = CY_CFG_SYSCLK_CLKHF1_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF1_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ + secure_config->hf1OutFreqMHz = CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_CLKPATH + secure_config->hf2Source = CY_CFG_SYSCLK_CLKHF2_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF2_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_DIVIDER + secure_config->hf2Divider = CY_CFG_SYSCLK_CLKHF2_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF2_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ + secure_config->hf2OutFreqMHz = CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_CLKPATH + secure_config->hf3Source = CY_CFG_SYSCLK_CLKHF3_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF3_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_DIVIDER + secure_config->hf3Divider = CY_CFG_SYSCLK_CLKHF3_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF3_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ + secure_config->hf3OutFreqMHz = CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_CLKPATH + secure_config->hf4Source = CY_CFG_SYSCLK_CLKHF4_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF4_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_DIVIDER + secure_config->hf4Divider = CY_CFG_SYSCLK_CLKHF4_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF4_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ + secure_config->hf4OutFreqMHz = CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_CLKPATH + secure_config->hf5Source = CY_CFG_SYSCLK_CLKHF5_CLKPATH; + #endif /* CY_CFG_SYSCLK_CLKHF5_CLKPATH */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_DIVIDER + secure_config->hf5Divider = CY_CFG_SYSCLK_CLKHF5_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKHF5_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ + secure_config->hf5OutFreqMHz = CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ; + #endif /* CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ */ + + #ifdef CY_CFG_SYSCLK_CLKPUMP_SOURCE + secure_config->pumpSource = CY_CFG_SYSCLK_CLKPUMP_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKPUMP_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKPUMP_DIVIDER + secure_config->pumpDivider = CY_CFG_SYSCLK_CLKPUMP_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKPUMP_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKLF_SOURCE + secure_config->clkLfSource = CY_CFG_SYSCLK_CLKLF_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKLF_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKBAK_SOURCE + secure_config->clkBakSource = CY_CFG_SYSCLK_CLKBAK_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKBAK_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKTIMER_SOURCE + secure_config->clkTimerSource = CY_CFG_SYSCLK_CLKTIMER_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKTIMER_SOURCE */ + + #ifdef CY_CFG_SYSCLK_CLKTIMER_DIVIDER + secure_config->clkTimerDivider = CY_CFG_SYSCLK_CLKTIMER_DIVIDER; + #endif /* CY_CFG_SYSCLK_CLKTIMER_DIVIDER */ + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE + secure_config->clkSrcAltSysTick = CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE; + #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD + secure_config->altHFcLoad = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME + secure_config->altHFxtalStartUpTime = CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ + secure_config->altHFfreq = CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV + secure_config->altHFsysClkDiv = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV */ + + #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR + secure_config->altHFvoltageReg = CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR; + #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR */ + } +#endif //defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit() + { + Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkBakInit() + { + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkFastInit() + { + Cy_SysClk_ClkFastSetDivider(0U); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkHf0Init() + { + Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkHf2Init() + { + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkHf4Init() + { + Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH); + Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_IloInit() + { + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_IloEnable(); + Cy_SysClk_IloHibernateOn(true); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkLfInit() + { + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath0Init() + { + Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPath1Init() + { + Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkPeriInit() + { + Cy_SysClk_ClkPeriSetDivider(0U); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_Pll0Init() + { + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR); + } + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkSlowInit() + { + Cy_SysClk_ClkSlowSetDivider(0U); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) +#if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + __STATIC_INLINE void Cy_SysClk_ClkTimerInit() + { + Cy_SysClk_ClkTimerDisable(); + Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO); + Cy_SysClk_ClkTimerSetDivider(0U); + Cy_SysClk_ClkTimerEnable(); + } +#endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) void init_cycfg_system(void) { - /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ - Cy_SysLib_SetWaitStates(false, 150UL); -#ifdef CY_CFG_PWR_ENABLED -#ifdef CY_CFG_PWR_INIT - init_cycfg_power(); -#else -#warning Power system will not be configured. Update power personality to v1.20 or later. -#endif /* CY_CFG_PWR_INIT */ -#endif /* CY_CFG_PWR_ENABLED */ - - /* Reset the core clock path to default and disable all the FLLs/PLLs */ - Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); - Cy_SysClk_ClkFastSetDivider(0U); - Cy_SysClk_ClkPeriSetDivider(1U); - Cy_SysClk_ClkSlowSetDivider(0U); - for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) { /* PLL 1 is the first PLL. 0 is invalid. */ - (void)Cy_SysClk_PllDisable(pll); - } - Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); - - if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && - (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) { - Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); - } - - Cy_SysClk_FllDisable(); - Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); - Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); -#ifdef CY_IP_MXBLESS - (void)Cy_BLE_EcoReset(); -#endif - - - /* Enable all source clocks */ -#ifdef CY_CFG_SYSCLK_PILO_ENABLED - Cy_SysClk_PiloInit(); -#endif - -#ifdef CY_CFG_SYSCLK_WCO_ENABLED - Cy_SysClk_WcoInit(); -#endif - -#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED - Cy_SysClk_ClkLfInit(); -#endif - -#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED - Cy_SysClk_AltHfInit(); -#endif - -#ifdef CY_CFG_SYSCLK_ECO_ENABLED - Cy_SysClk_EcoInit(); -#endif - -#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED - Cy_SysClk_ExtClkInit(); -#endif - - /* Configure CPU clock dividers */ -#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED - Cy_SysClk_ClkFastInit(); -#endif - -#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED - Cy_SysClk_ClkPeriInit(); -#endif - -#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED - Cy_SysClk_ClkSlowInit(); -#endif - -#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) - /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ - Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); - Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); -#else -#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED - Cy_SysClk_ClkPath1Init(); -#endif -#endif - - /* Configure Path Clocks */ -#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED - Cy_SysClk_ClkPath0Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED - Cy_SysClk_ClkPath2Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED - Cy_SysClk_ClkPath3Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED - Cy_SysClk_ClkPath4Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED - Cy_SysClk_ClkPath5Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED - Cy_SysClk_ClkPath6Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED - Cy_SysClk_ClkPath7Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED - Cy_SysClk_ClkPath8Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED - Cy_SysClk_ClkPath9Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED - Cy_SysClk_ClkPath10Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED - Cy_SysClk_ClkPath11Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED - Cy_SysClk_ClkPath12Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED - Cy_SysClk_ClkPath13Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED - Cy_SysClk_ClkPath14Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED - Cy_SysClk_ClkPath15Init(); -#endif - - /* Configure and enable FLL */ -#ifdef CY_CFG_SYSCLK_FLL_ENABLED - Cy_SysClk_FllInit(); -#endif - - Cy_SysClk_ClkHf0Init(); - -#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) -#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED - /* Apply the ClkPath1 user setting */ - Cy_SysClk_ClkPath1Init(); -#endif -#endif - - /* Configure and enable PLLs */ -#ifdef CY_CFG_SYSCLK_PLL0_ENABLED - Cy_SysClk_Pll0Init(); -#endif -#ifdef CY_CFG_SYSCLK_PLL1_ENABLED - Cy_SysClk_Pll1Init(); -#endif -#ifdef CY_CFG_SYSCLK_PLL2_ENABLED - Cy_SysClk_Pll2Init(); -#endif -#ifdef CY_CFG_SYSCLK_PLL3_ENABLED - Cy_SysClk_Pll3Init(); -#endif -#ifdef CY_CFG_SYSCLK_PLL4_ENABLED - Cy_SysClk_Pll4Init(); -#endif -#ifdef CY_CFG_SYSCLK_PLL5_ENABLED - Cy_SysClk_Pll5Init(); -#endif -#ifdef CY_CFG_SYSCLK_PLL6_ENABLED - Cy_SysClk_Pll6Init(); -#endif -#ifdef CY_CFG_SYSCLK_PLL7_ENABLED - Cy_SysClk_Pll7Init(); -#endif -#ifdef CY_CFG_SYSCLK_PLL8_ENABLED - Cy_SysClk_Pll8Init(); -#endif -#ifdef CY_CFG_SYSCLK_PLL9_ENABLED - Cy_SysClk_Pll9Init(); -#endif -#ifdef CY_CFG_SYSCLK_PLL10_ENABLED - Cy_SysClk_Pll10Init(); -#endif -#ifdef CY_CFG_SYSCLK_PLL11_ENABLED - Cy_SysClk_Pll11Init(); -#endif -#ifdef CY_CFG_SYSCLK_PLL12_ENABLED - Cy_SysClk_Pll12Init(); -#endif -#ifdef CY_CFG_SYSCLK_PLL13_ENABLED - Cy_SysClk_Pll13Init(); -#endif -#ifdef CY_CFG_SYSCLK_PLL14_ENABLED - Cy_SysClk_Pll14Init(); -#endif - - /* Configure HF clocks */ -#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED - Cy_SysClk_ClkHf1Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED - Cy_SysClk_ClkHf2Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED - Cy_SysClk_ClkHf3Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED - Cy_SysClk_ClkHf4Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED - Cy_SysClk_ClkHf5Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED - Cy_SysClk_ClkHf6Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED - Cy_SysClk_ClkHf7Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED - Cy_SysClk_ClkHf8Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED - Cy_SysClk_ClkHf9Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED - Cy_SysClk_ClkHf10Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED - Cy_SysClk_ClkHf11Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED - Cy_SysClk_ClkHf12Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED - Cy_SysClk_ClkHf13Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED - Cy_SysClk_ClkHf14Init(); -#endif -#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED - Cy_SysClk_ClkHf15Init(); -#endif - - /* Configure miscellaneous clocks */ -#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED - Cy_SysClk_ClkTimerInit(); -#endif - -#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED - Cy_SysClk_ClkAltSysTickInit(); -#endif - -#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED - Cy_SysClk_ClkPumpInit(); -#endif - -#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED - Cy_SysClk_ClkBakInit(); -#endif - - /* Configure default enabled clocks */ -#ifdef CY_CFG_SYSCLK_ILO_ENABLED - Cy_SysClk_IloInit(); -#else - Cy_SysClk_IloDisable(); -#endif - -#ifndef CY_CFG_SYSCLK_IMO_ENABLED -#error the IMO must be enabled for proper chip operation -#endif - -#ifdef CY_CFG_SYSCLK_MFO_ENABLED - Cy_SysClk_MfoInit(); -#endif - -#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED - Cy_SysClk_ClkMfInit(); -#endif - - /* Set accurate flash wait states */ -#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) - Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); -#endif + #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) + cy_en_pra_status_t configStatus; + init_cycfg_secure_struct(&srss_0_clock_0_secureConfig); + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 1UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 2UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 3UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 4UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + #if ((CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 5UL)) + #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0. + #endif + + configStatus = CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_SYS_CFG_FUNC, + CY_PRA_FUNC_INIT_CYCFG_DEVICE, + &srss_0_clock_0_secureConfig); + if ( configStatus != CY_PRA_STATUS_SUCCESS ) + { + cycfg_ClockStartupError(configStatus); + } - /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ - SystemCoreClockUpdate(); + #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ + Cy_SysClk_ExtClkSetFrequency(CY_CFG_SYSCLK_EXTCLK_FREQ); + #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */ + #else /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + + /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ + Cy_SysLib_SetWaitStates(false, 150UL); + #ifdef CY_CFG_PWR_ENABLED + #ifdef CY_CFG_PWR_INIT + init_cycfg_power(); + #else + #warning Power system will not be configured. Update power personality to v1.20 or later. + #endif /* CY_CFG_PWR_INIT */ + #endif /* CY_CFG_PWR_ENABLED */ + + /* Reset the core clock path to default and disable all the FLLs/PLLs */ + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkFastSetDivider(0U); + Cy_SysClk_ClkPeriSetDivider(1U); + Cy_SysClk_ClkSlowSetDivider(0U); + for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ + { + (void)Cy_SysClk_PllDisable(pll); + } + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); + + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && + (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) + { + Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); + } + + Cy_SysClk_FllDisable(); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); + #ifdef CY_IP_MXBLESS + (void)Cy_BLE_EcoReset(); + #endif + + + /* Enable all source clocks */ + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + Cy_SysClk_PiloInit(); + #endif + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + Cy_SysClk_WcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + Cy_SysClk_ClkLfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + Cy_SysClk_AltHfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + Cy_SysClk_EcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + Cy_SysClk_ExtClkInit(); + #endif + + /* Configure CPU clock dividers */ + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + Cy_SysClk_ClkFastInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + Cy_SysClk_ClkPeriInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + Cy_SysClk_ClkSlowInit(); + #endif + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U)) + /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ + Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); + #else + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure Path Clocks */ + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + Cy_SysClk_ClkPath0Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + Cy_SysClk_ClkPath2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + Cy_SysClk_ClkPath3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + Cy_SysClk_ClkPath4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + Cy_SysClk_ClkPath5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED + Cy_SysClk_ClkPath6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED + Cy_SysClk_ClkPath7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED + Cy_SysClk_ClkPath8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED + Cy_SysClk_ClkPath9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED + Cy_SysClk_ClkPath10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED + Cy_SysClk_ClkPath11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED + Cy_SysClk_ClkPath12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED + Cy_SysClk_ClkPath13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED + Cy_SysClk_ClkPath14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED + Cy_SysClk_ClkPath15Init(); + #endif + + /* Configure and enable FLL */ + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + Cy_SysClk_FllInit(); + #endif + + Cy_SysClk_ClkHf0Init(); + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U)) + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + /* Apply the ClkPath1 user setting */ + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure and enable PLLs */ + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + Cy_SysClk_Pll0Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + Cy_SysClk_Pll1Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL2_ENABLED + Cy_SysClk_Pll2Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL3_ENABLED + Cy_SysClk_Pll3Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL4_ENABLED + Cy_SysClk_Pll4Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL5_ENABLED + Cy_SysClk_Pll5Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL6_ENABLED + Cy_SysClk_Pll6Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL7_ENABLED + Cy_SysClk_Pll7Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL8_ENABLED + Cy_SysClk_Pll8Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL9_ENABLED + Cy_SysClk_Pll9Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL10_ENABLED + Cy_SysClk_Pll10Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL11_ENABLED + Cy_SysClk_Pll11Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL12_ENABLED + Cy_SysClk_Pll12Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL13_ENABLED + Cy_SysClk_Pll13Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL14_ENABLED + Cy_SysClk_Pll14Init(); + #endif + + /* Configure HF clocks */ + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + Cy_SysClk_ClkHf1Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + Cy_SysClk_ClkHf2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + Cy_SysClk_ClkHf3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + Cy_SysClk_ClkHf4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + Cy_SysClk_ClkHf5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED + Cy_SysClk_ClkHf6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED + Cy_SysClk_ClkHf7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED + Cy_SysClk_ClkHf8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED + Cy_SysClk_ClkHf9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED + Cy_SysClk_ClkHf10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED + Cy_SysClk_ClkHf11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED + Cy_SysClk_ClkHf12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED + Cy_SysClk_ClkHf13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED + Cy_SysClk_ClkHf14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED + Cy_SysClk_ClkHf15Init(); + #endif + + /* Configure miscellaneous clocks */ + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + Cy_SysClk_ClkTimerInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + Cy_SysClk_ClkPumpInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + Cy_SysClk_ClkBakInit(); + #endif + + /* Configure default enabled clocks */ + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + Cy_SysClk_IloInit(); + #endif + + #ifndef CY_CFG_SYSCLK_IMO_ENABLED + #error the IMO must be enabled for proper chip operation + #endif + + #endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ + + #ifdef CY_CFG_SYSCLK_MFO_ENABLED + Cy_SysClk_MfoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED + Cy_SysClk_ClkMfInit(); + #endif + + #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) + /* Set accurate flash wait states */ + #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) + Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); + #endif + + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ + SystemCoreClockUpdate(); + #ifndef CY_CFG_SYSCLK_ILO_ENABLED + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + /* Wait 4 ILO cycles in case of unfinished CLKLF clock source transition */ + Cy_SysLib_DelayUs(200U); + #endif + Cy_SysClk_IloDisable(); + Cy_SysClk_IloHibernateOn(false); + #endif + + #endif /* ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) */ + #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 5789141016d..2bbe49e15da 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -5,7 +5,7 @@ * System configuration * This file was automatically generated and should not be modified. * Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* Device Support Library (../../../psoc6pdl): 1.6.0.4266 * ******************************************************************************** * Copyright 2017-2019 Cypress Semiconductor Corporation @@ -29,9 +29,11 @@ #include "cycfg_notices.h" #include "cy_sysclk.h" +#include "cy_pra.h" +#include "cy_pra_cfg.h" #include "cy_systick.h" #if defined (CY_USING_HAL) -#include "cyhal_hwmgr.h" + #include "cyhal_hwmgr.h" #endif //defined (CY_USING_HAL) #if defined(__cplusplus) @@ -45,14 +47,18 @@ extern "C" { #define srss_0_clock_0_fastclk_0_ENABLED 1U #define srss_0_clock_0_hfclk_0_ENABLED 1U #define CY_CFG_SYSCLK_CLKHF0 0UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 1UL #define srss_0_clock_0_hfclk_2_ENABLED 1U #define CY_CFG_SYSCLK_CLKHF2 2UL +#define CY_CFG_SYSCLK_CLKHF2_CLKPATH_NUM 1UL #define srss_0_clock_0_hfclk_4_ENABLED 1U #define CY_CFG_SYSCLK_CLKHF4 4UL +#define CY_CFG_SYSCLK_CLKHF4_CLKPATH_NUM 1UL #define srss_0_clock_0_ilo_0_ENABLED 1U #define srss_0_clock_0_imo_0_ENABLED 1U #define srss_0_clock_0_lfclk_0_ENABLED 1U #define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000 +#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_ILO #define srss_0_clock_0_pathmux_0_ENABLED 1U #define srss_0_clock_0_pathmux_1_ENABLED 1U #define srss_0_clock_0_periclk_0_ENABLED 1U @@ -61,10 +67,10 @@ extern "C" { #define srss_0_clock_0_timerclk_0_ENABLED 1U #if defined (CY_USING_HAL) -extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj; + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) -extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj; + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj; #endif //defined (CY_USING_HAL) void init_cycfg_system(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list index eb12959c7d2..96ca19956cb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -1,4 +1,4 @@ -[Device=CY8C624AFNI-D43] +[Device=CY8C624AFNI-S2D43] [Blocks] # WIFI diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus index b65c07862f3..93773a77c20 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -2,7 +2,7 @@ - + @@ -10,111 +10,8 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + @@ -150,19 +47,6 @@ - - - - - - - - - - - - - @@ -258,38 +142,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c index 58fbf17f102..1e051ac3b78 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,9 +29,10 @@ #include "cybsp.h" #if defined(CY_USING_HAL) #include "cyhal_hwmgr.h" +#include "cyhal_syspm.h" #endif -#if !defined (CY_CFG_PWR_SYS_IDLE_MODE) +#if !defined (CY_CFG_PWR_SYS_IDLE_MODE) && defined(__MBED__) #include "mbed_power_mgmt.h" #endif @@ -45,13 +46,13 @@ extern "C" { * Doing so minimizes the time spent on low power mode entry and exit. */ #ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER -#define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) + #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) #endif #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) static cyhal_sdio_t sdio_obj; -cyhal_sdio_t *cybsp_get_wifi_sdio_obj(void) +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) { return &sdio_obj; } @@ -73,7 +74,8 @@ static cy_rslt_t cybsp_register_sysclk_pm_callback(void) .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER }; - if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) { + if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) + { result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; } return result; @@ -84,21 +86,31 @@ cy_rslt_t cybsp_init(void) /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ #if defined(CY_USING_HAL) cy_rslt_t result = cyhal_hwmgr_init(); + + if (CY_RSLT_SUCCESS == result) + { + result = cyhal_syspm_init(); + } #else cy_rslt_t result = CY_RSLT_SUCCESS; #endif -#if defined(COMPONENT_BSP_DESIGN_MODUS) +#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) init_cycfg_all(); #endif - if (CY_RSLT_SUCCESS == result) { + if (CY_RSLT_SUCCESS == result) + { result = cybsp_register_sysclk_pm_callback(); } #if !defined(CY_CFG_PWR_SYS_IDLE_MODE) +#ifdef __MBED__ /* Disable deep-sleep. */ sleep_manager_lock_deep_sleep(); +#else + cyhal_syspm_lock_deepsleep(); +#endif #endif /* Reserve clock dividers used by NP. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h index a54284bdcd2..1ec5ff5a603 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,9 +26,6 @@ #include "cy_result.h" #include "cybsp_types.h" -#if defined(COMPONENT_BSP_DESIGN_MODUS) -#include "cycfg.h" -#endif #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) #include "cyhal_sdio.h" #endif @@ -66,7 +63,7 @@ cy_rslt_t cybsp_init(void); * \note This function should only be called after cybsp_init(); * \returns The initialized sdio object. */ -cyhal_sdio_t *cybsp_get_wifi_sdio_obj(void); +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); #endif /* defined(CYBSP_WIFI_CAPABLE) */ /** \} group_bsp_functions */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h index 19ab4067483..9f0ff31decb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h @@ -1,13 +1,13 @@ /***************************************************************************//** -* \file CYSBSYSKIT_01/cybsp_types.h +* \file CYSBSYSKIT-01/cybsp_types.h * * Description: * Provides APIs for interacting with the hardware contained on the Cypress -* CYSBSYSKIT_01 kit. +* CYSBSYSKIT-01 kit. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,6 +28,9 @@ #if defined(CY_USING_HAL) #include "cyhal_pin_package.h" #endif +#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) +#include "cycfg.h" +#endif #if defined(__cplusplus) extern "C" { @@ -66,14 +69,22 @@ extern "C" { */ /** Pin state for the LED on. */ +#ifndef CYBSP_LED_STATE_ON #define CYBSP_LED_STATE_ON (0U) +#endif /** Pin state for the LED off. */ +#ifndef CYBSP_LED_STATE_OFF #define CYBSP_LED_STATE_OFF (1U) +#endif /** Pin state for when a button is pressed. */ +#ifndef CYBSP_BTN_PRESSED #define CYBSP_BTN_PRESSED (0U) +#endif /** Pin state for when a button is released. */ +#ifndef CYBSP_BTN_OFF #define CYBSP_BTN_OFF (1U) +#endif /** \} group_bsp_pin_state */ @@ -90,7 +101,9 @@ extern "C" { */ /** BSP user LED1 reference designator to pin mapping */ +#ifndef CYBSP_USER_LED1 #define CYBSP_USER_LED1 (P11_1) +#endif /** \} group_bsp_pins_led */ @@ -100,7 +113,9 @@ extern "C" { */ /** BSP user button reference designator to pin mapping */ +#ifndef CYBSP_USER_BTN #define CYBSP_USER_BTN (P0_4) +#endif /** \} group_bsp_pins_btn */ @@ -110,50 +125,91 @@ extern "C" { */ /** Pin: UART RX */ +#ifndef CYBSP_DEBUG_UART_RX #define CYBSP_DEBUG_UART_RX (P5_4) +#endif /** Pin: UART TX */ +#ifndef CYBSP_DEBUG_UART_TX #define CYBSP_DEBUG_UART_TX (P5_5) +#endif /** Pin: UART_RTS */ +#ifndef CYBSP_DEBUG_UART_RTS #define CYBSP_DEBUG_UART_RTS (P5_6) +#endif /** Pin: UART_CTS */ +#ifndef CYBSP_DEBUG_UART_CTS #define CYBSP_DEBUG_UART_CTS (P5_7) +#endif /** Pin: SWDIO */ +#ifndef CYBSP_SWDIO #define CYBSP_SWDIO (P6_6) +#endif /** Pin: SWDCK */ +#ifndef CYBSP_SWDCK #define CYBSP_SWDCK (P6_7) +#endif /** Pin: QUAD SPI SS */ +#ifndef CYBSP_QSPI_SS #define CYBSP_QSPI_SS (P11_2) +#endif /** Pin: QUAD SPI D3 */ +#ifndef CYBSP_QSPI_D3 #define CYBSP_QSPI_D3 (P11_3) +#endif /** Pin: QUAD SPI D2 */ +#ifndef CYBSP_QSPI_D2 #define CYBSP_QSPI_D2 (P11_4) +#endif /** Pin: QUAD SPI D1 */ +#ifndef CYBSP_QSPI_D1 #define CYBSP_QSPI_D1 (P11_5) +#endif /** Pin: QUAD SPI D0 */ +#ifndef CYBSP_QSPI_D0 #define CYBSP_QSPI_D0 (P11_6) +#endif /** Pin: QUAD SPI SCK */ +#ifndef CYBSP_QSPI_SCK #define CYBSP_QSPI_SCK (P11_7) +#endif /** Pin: I2C SCL */ +#ifndef CYBSP_I2C_SCL #define CYBSP_I2C_SCL (P6_0) +#endif + /** Pin: I2C SDA */ +#ifndef CYBSP_I2C_SDA #define CYBSP_I2C_SDA (P6_1) +#endif /** Pin: SPI MOSI */ +#ifndef CYBSP_SPI_MOSI #define CYBSP_SPI_MOSI (P5_0) +#endif /** Pin: SPI MISO */ +#ifndef CYBSP_SPI_MISO #define CYBSP_SPI_MISO (P5_1) +#endif /** Pin: SPI CLK */ +#ifndef CYBSP_SPI_CLK #define CYBSP_SPI_CLK (P5_2) +#endif /** Pin: SPI CS */ +#ifndef CYBSP_SPI_CS #define CYBSP_SPI_CS (P5_3) +#endif /** Pin: FEATHER UART RX */ +#ifndef CYBSP_FEATHER_UART_RX #define CYBSP_FEATHER_UART_RX (P6_4) +#endif /** Pin: FEATHER UART TX */ +#ifndef CYBSP_FEATHER_UART_TX #define CYBSP_FEATHER_UART_TX (P6_5) +#endif /** \} group_bsp_pins_comm */ @@ -163,10 +219,13 @@ extern "C" { */ /** Pin: Thermister VDD */ +#ifndef CYBSP_THERM_VDD #define CYBSP_THERM_VDD (P10_6) +#endif /** Pin: Thermister output */ +#ifndef CYBSP_THERM_OUT #define CYBSP_THERM_OUT (P10_7) - +#endif /** \} group_bsp_pins_therm */ /** @@ -175,9 +234,13 @@ extern "C" { */ /** Pin: ECO IN */ +#ifndef CYBSP_ECO_IN #define CYBSP_ECO_IN (P12_6) +#endif /** Pin: ECO IN */ +#ifndef CYBSP_ECO_OUT #define CYBSP_ECO_OUT (P12_7) +#endif /** \} group_bsp_pins_eco */ @@ -187,31 +250,57 @@ extern "C" { */ /** GPIOA0 */ +#ifndef CYBSP_GPIOA0 #define CYBSP_GPIOA0 (P10_0) +#endif /** GPIOA1 */ +#ifndef CYBSP_GPIOA1 #define CYBSP_GPIOA1 (P10_1) +#endif /** GPIOA2 */ +#ifndef CYBSP_GPIOA2 #define CYBSP_GPIOA2 (P10_2) +#endif /** GPIOA3 */ +#ifndef CYBSP_GPIOA3 #define CYBSP_GPIOA3 (P10_3) +#endif /** GPIOA4 */ +#ifndef CYBSP_GPIOA4 #define CYBSP_GPIOA4 (P10_4) +#endif /** GPIOA5 */ +#ifndef CYBSP_GPIOA5 #define CYBSP_GPIOA5 (P10_5) +#endif /** GPIO5 */ +#ifndef CYBSP_GPIO5 #define CYBSP_GPIO5 (P8_4) +#endif /** GPIO6 */ +#ifndef CYBSP_GPIO6 #define CYBSP_GPIO6 (P9_7) +#endif /** GPIO9 */ +#ifndef CYBSP_GPIO9 #define CYBSP_GPIO9 (P9_4) +#endif /** GPIO10 */ +#ifndef CYBSP_GPIO10 #define CYBSP_GPIO10 (P9_3) +#endif /** GPIO11 */ +#ifndef CYBSP_GPIO11 #define CYBSP_GPIO11 (P9_2) +#endif /** GPIO12 */ +#ifndef CYBSP_GPIO12 #define CYBSP_GPIO12 (P9_1) +#endif /** GPIO13 */ +#ifndef CYBSP_GPIO13 #define CYBSP_GPIO13 (P9_0) +#endif /** \} group_bsp_pins_feather */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct index ea1cfaefe9a..439fffbfeab 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cy8c6xxa_cm4_dual.sct -;* \version 2.60 +;* \version 2.70.1 ;* ;* Linker file for the ARMCC. ;* @@ -26,7 +26,7 @@ ;* ;******************************************************************************* ;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* Copyright 2016-2020 Cypress Semiconductor Corporation ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -79,7 +79,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif -; Size of the stack section at the end of CM4 SRAM +; The size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S index 88eb1f471d6..114d71efb8f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S @@ -23,7 +23,6 @@ ; * limitations under the License. ; */ - PRESERVE8 THUMB @@ -696,7 +695,6 @@ sdhc_1_interrupt_general_IRQHandler ALIGN - END diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld index 8f5a345f18f..adfe2ea07d7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy8c6xxa_cm4_dual.ld -* \version 2.60 +* \version 2.70.1 * * Linker file for the GNU C compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -76,7 +76,7 @@ ENTRY(Reset_Handler) #define MBED_BOOT_STACK_SIZE 0x400 #endif -/* Size of the stack section at the end of CM4 SRAM */ +/* The size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf index 019967a0c12..e05dce36cdd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -1,6 +1,6 @@ -/***************************************************************************//** +/******************************************************************************* * \file cy8c6xxa_cm4_dual.icf -* \version 2.60 +* \version 2.70.1 * * Linker file for the IAR compiler. * @@ -19,7 +19,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -102,7 +102,7 @@ define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); -/* The following symbols define a 32K flash region used for EEPROM emulation. +/* The following symbols define a 32K flash region used for EEPROM emulation. * This region can also be used as the general purpose flash. * You can assign sections to this memory region for only one of the cores. * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. From 6ba8885ad31e40e3e2cf9047a83d7b138f17f316 Mon Sep 17 00:00:00 2001 From: Dustin Crossman Date: Mon, 10 Aug 2020 16:57:20 -0700 Subject: [PATCH 2/5] Update COMPONENT_SCL. --- .../interface/SclAccessPoint.cpp | 65 +++++++ .../COMPONENT_SCL/interface/SclAccessPoint.h | 74 ++++++++ .../interface/SclSTAInterface.cpp | 144 +++++++++++++++- .../COMPONENT_SCL/interface/SclSTAInterface.h | 19 ++- .../interface/default_wifi_interface.cpp | 3 +- .../COMPONENT_SCL/interface/scl_interface.h | 49 ++++++ .../COMPONENT_SCL/inc/scl_common.h | 6 +- .../COMPONENT_SCL/inc/scl_types.h | 158 +++++++++++++++++- .../COMPONENT_SCL/inc/scl_wifi_api.h | 49 ++++++ .../COMPONENT_SCL/src/IPC/scl_ipc.c | 20 +++ .../COMPONENT_SCL/src/scl_wifi_api.c | 47 ++++++ 11 files changed, 618 insertions(+), 16 deletions(-) create mode 100644 connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/SclAccessPoint.cpp create mode 100644 connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/SclAccessPoint.h create mode 100644 connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/scl_interface.h diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/SclAccessPoint.cpp b/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/SclAccessPoint.cpp new file mode 100644 index 00000000000..02995e95bee --- /dev/null +++ b/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/SclAccessPoint.cpp @@ -0,0 +1,65 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include "SclAccessPoint.h" + +SclAccessPoint::SclAccessPoint(nsapi_wifi_ap_t ap, scl_bss_type_t bss_type, uint8_t *ie_ptr, uint32_t ie_len) : + WiFiAccessPoint(ap), _bss_type(bss_type) +{ + _ie_ptr = (uint8_t *)malloc(ie_len * sizeof(uint8_t)); + if (_ie_ptr != NULL) { + _ie_len = ie_len; + memcpy(_ie_ptr, ie_ptr, ie_len); + } +} + +SclAccessPoint &SclAccessPoint::operator=(SclAccessPoint &&rhs) +{ + if (this != &rhs) { + WiFiAccessPoint::operator=(rhs); + _bss_type = rhs._bss_type; + _ie_ptr = rhs._ie_ptr; + _ie_len = rhs._ie_len; + rhs._ie_ptr = NULL; + rhs._ie_len = 0; + } + return *this; +} + +scl_bss_type_t SclAccessPoint::get_bss_type() const +{ + return _bss_type; +} + +uint8_t *SclAccessPoint::get_ie_data() const +{ + return _ie_ptr; +} + +uint32_t SclAccessPoint::get_ie_len() const +{ + return _ie_len; +} + +SclAccessPoint::~SclAccessPoint() +{ + if (_ie_ptr != NULL) { + free(_ie_ptr); + } +} diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/SclAccessPoint.h b/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/SclAccessPoint.h new file mode 100644 index 00000000000..aea990b4e77 --- /dev/null +++ b/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/SclAccessPoint.h @@ -0,0 +1,74 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SCL_ACCESS_POINT_H +#define SCL_ACCESS_POINT_H + +#include "netsocket/WiFiAccessPoint.h" +#include "scl_types.h" + +/* Enum for scan result type */ +enum scan_result_type { + SRES_TYPE_WIFI_ACCESS_POINT, + SRES_TYPE_SCL_ACCESS_POINT +}; + +/** SclAccessPoint class + * + * Class that represents a Scl Access Point + * which contains additional Scl specific information + */ +class SclAccessPoint : public WiFiAccessPoint { +public: + SclAccessPoint() : WiFiAccessPoint() {}; + SclAccessPoint(nsapi_wifi_ap_t ap, scl_bss_type_t bss_type, uint8_t *ie_ptr, uint32_t ie_len); + + /** Define move assignment and prevent copy-assignment + * + * Due to IE element data could have large memory footprint, + * only move assignment is allowed. + */ + SclAccessPoint &operator=(SclAccessPoint &&rhs); + SclAccessPoint &operator=(const SclAccessPoint &rhs) = delete; + + /** Get SCL access point's bss type + * + * @return The scl_bss_type_t of the access point + */ + scl_bss_type_t get_bss_type() const; + + /** Get SCL access point's IE data + * + * @return The pointer to ie data buffer + */ + uint8_t *get_ie_data() const; + + /** Get SCL access point's IE length + * + * @return The ie data length + */ + uint32_t get_ie_len() const; + + virtual ~SclAccessPoint(); + +private: + scl_bss_type_t _bss_type; + uint8_t *_ie_ptr; /**< Pointer to received Beacon/Probe Response IE(Information Element) */ + uint32_t _ie_len; /**< Length of IE(Information Element) */ +}; + +#endif diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp b/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp index 1fefdee0792..1a244072442 100644 --- a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp +++ b/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp @@ -27,8 +27,8 @@ #include "scl_emac.h" #include "scl_ipc.h" #include "mbed_wait_api.h" - - +#include "SclAccessPoint.h" +#include "scl_buffer_api.h" /** @file * Provides SCL interface functions to be used with WiFiInterface or NetworkInterface Objects */ @@ -43,8 +43,31 @@ struct scl_tx_net_credentials { const char *network_passphrase; } scl_tx_network_credentials; + +struct scl_scan_userdata { + rtos::Semaphore *sema; + scan_result_type sres_type; + WiFiAccessPoint *aps; + std::vector *result_buff; + unsigned count; + unsigned offset; + bool scan_in_progress; +}; + +static scl_scan_userdata interal_scan_data; +static scl_scan_result_t internal_scan_result; network_params_t network_parameter; +/* Internal scan callback that handles the scan results */ +void scl_scan_handler(scl_scan_result_t *result_ptr,void *user_data, scl_scan_status_t status); + +#define CMP_MAC( a, b ) (((((unsigned char*)a)[0])==(((unsigned char*)b)[0]))&& \ + ((((unsigned char*)a)[1])==(((unsigned char*)b)[1]))&& \ + ((((unsigned char*)a)[2])==(((unsigned char*)b)[2]))&& \ + ((((unsigned char*)a)[3])==(((unsigned char*)b)[3]))&& \ + ((((unsigned char*)a)[4])==(((unsigned char*)b)[4]))&& \ + ((((unsigned char*)a)[5])==(((unsigned char*)b)[5]))) + int scl_toerror(scl_result_t res) { switch (res) { @@ -93,14 +116,22 @@ nsapi_security_t scl_tosecurity(scl_security_t sec) case SCL_SECURITY_WEP_SHARED: return NSAPI_SECURITY_WEP; case SCL_SECURITY_WPA_TKIP_PSK: + case SCL_SECURITY_WPA_AES_PSK: case SCL_SECURITY_WPA_TKIP_ENT: + case SCL_SECURITY_WPA_AES_ENT: + case SCL_SECURITY_WPA_MIXED_ENT: return NSAPI_SECURITY_WPA; case SCL_SECURITY_WPA2_MIXED_PSK: + case SCL_SECURITY_WPA2_WPA_PSK: + case SCL_SECURITY_WPA2_WPA_TKIP_PSK: return NSAPI_SECURITY_WPA_WPA2; + case SCL_SECURITY_WPA2_MIXED_ENT: + return NSAPI_SECURITY_WPA2_ENT; case SCL_SECURITY_WPA2_AES_PSK: case SCL_SECURITY_WPA2_AES_ENT: case SCL_SECURITY_WPA2_FBT_PSK: case SCL_SECURITY_WPA2_FBT_ENT: + case SCL_SECURITY_WPA2_TKIP_ENT: return NSAPI_SECURITY_WPA2; default: return NSAPI_SECURITY_UNKNOWN; @@ -125,12 +156,13 @@ scl_security_t scl_fromsecurity(nsapi_security_t sec) } } -SclSTAInterface::SclSTAInterface(SCL_EMAC &emac, OnboardNetworkStack &stack) +SclSTAInterface::SclSTAInterface(SCL_EMAC &emac, OnboardNetworkStack &stack, scl_interface_shared_info_t &shared) : EMACInterface(emac, stack), _ssid("\0"), _pass("\0"), _security(NSAPI_SECURITY_NONE), - _scl_emac(emac) + _scl_emac(emac), + _iface_shared(shared) { } @@ -180,7 +212,7 @@ nsapi_error_t SclSTAInterface::connect() uint32_t connection_status = 0; scl_tx_network_credentials.network_ssid = _ssid; - if ((strlen(_ssid) < MAX_SSID_LENGTH) && (strlen(_ssid) > MIN_SSID_LENGTH)) { + if ((strlen(_ssid) < MAX_SSID_LENGTH) && (strlen(_ssid) > MIN_SSID_LENGTH) ) { scl_tx_network_credentials.ssid_len = strlen(_ssid); } else { return NSAPI_ERROR_PARAMETER; @@ -288,10 +320,106 @@ nsapi_error_t SclSTAInterface::disconnect() return NSAPI_ERROR_OK; } -int SclSTAInterface::scan(WiFiAccessPoint *res, unsigned count) +void scl_scan_handler(scl_scan_result_t *result_ptr, + void *user_data, scl_scan_status_t status) +{ + scl_scan_userdata *data = (scl_scan_userdata *)&interal_scan_data; + scl_scan_result_t *record = result_ptr; + unsigned int i; + nsapi_wifi_ap ap; + uint8_t length; + + /* Even after stopping scan, some results will still come as results are already present in the queue */ + if (data->scan_in_progress == false) { + return; + } + + // finished scan, either succesfully or through an abort + if (status != SCL_SCAN_INCOMPLETE) { + data->scan_in_progress = false; + data->sema->release(); + return; + } + + // can't really keep anymore scan results + if (data->count > 0 && data->offset >= data->count) { + /* We can not abort the scan as this function is getting executed in SCL context, + Note that to call any SCL API, caller function should not in SCL context */ + return; + } + + for (i = 0; i < data->result_buff->size(); i++) { + if (memcmp(((*data->result_buff)[i].BSSID.octet),(record->BSSID.octet),sizeof(scl_mac_t)) == 0) { + return; + } + } + + if (data->count > 0 && (data->aps != NULL)) { + // get ap stats + length = record->SSID.length; + if (length < (sizeof(ap.ssid) - 1)) { + length = sizeof(ap.ssid) - 1; + } + memcpy(ap.ssid, record->SSID.value, length); + ap.ssid[length] = '\0'; + + memcpy(ap.bssid, record->BSSID.octet, sizeof(ap.bssid)); + + ap.security = scl_tosecurity(record->security); + ap.rssi = record->signal_strength; + ap.channel = record->channel; + if (data->sres_type == SRES_TYPE_WIFI_ACCESS_POINT) { + data->aps[data->offset] = WiFiAccessPoint(ap); + } else if (data->sres_type == SRES_TYPE_SCL_ACCESS_POINT) { + SclAccessPoint *aps_sres = static_cast(data->aps); + aps_sres[data->offset] = std::move(SclAccessPoint(ap, record->bss_type, + record->ie_ptr, record->ie_len)); + } + } + + // store to result_buff for future duplication removal + data->result_buff->push_back(*record); + data->offset = data->result_buff->size(); +} + +int SclSTAInterface::internal_scan(WiFiAccessPoint *aps, unsigned count, scan_result_type sres_type) +{ + ScopedMutexLock lock(_iface_shared.mutex); + scl_result_t scl_res; + int res; + + // initialize wifi, this is noop if already init + if (!_scl_emac.powered_up) { + if(!_scl_emac.power_up()) { + return NSAPI_ERROR_DEVICE_ERROR; + } + } + + interal_scan_data.sema = new Semaphore(); + interal_scan_data.sres_type = sres_type; + interal_scan_data.aps = aps; + interal_scan_data.count = count; + interal_scan_data.offset = 0; + interal_scan_data.scan_in_progress = true; + interal_scan_data.result_buff = new std::vector(); + + scl_res = (scl_result_t)scl_wifi_scan(SCL_SCAN_TYPE_ACTIVE, SCL_BSS_TYPE_ANY, + NULL, NULL, NULL, NULL, scl_scan_handler, &internal_scan_result, &interal_scan_data); + if (scl_res != SCL_SUCCESS) { + res = scl_toerror(scl_res); + } else { + /* This semaphore will be released in scan callback once the scan is completed */ + interal_scan_data.sema->acquire(); + res = interal_scan_data.offset; + } + delete interal_scan_data.sema; + delete interal_scan_data.result_buff; + return res; +} + +int SclSTAInterface::scan(WiFiAccessPoint *aps, unsigned count) { - /* To Do */ - return NSAPI_ERROR_UNSUPPORTED; + return internal_scan(aps, count, SRES_TYPE_WIFI_ACCESS_POINT); } int8_t SclSTAInterface::get_rssi() diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.h b/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.h index 801a9a5dfc7..e88d0dc6bb9 100644 --- a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.h +++ b/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.h @@ -29,6 +29,8 @@ #include "scl_emac.h" #include "scl_wifi_api.h" #include "scl_types.h" +#include "SclAccessPoint.h" +#include "scl_interface.h" #define MAX_SSID_LENGTH (33) /**< Maximum ssid length */ #define MAX_PASSWORD_LENGTH (64) /**< Maximum password length */ @@ -40,7 +42,8 @@ class SclSTAInterface : public WiFiInterface, public EMACInterface { SclSTAInterface( SCL_EMAC &emac = SCL_EMAC::get_instance(), - OnboardNetworkStack &stack = OnboardNetworkStack::get_default_instance()); + OnboardNetworkStack &stack = OnboardNetworkStack::get_default_instance(), + scl_interface_shared_info_t &shared = scl_iface_shared); /** Gets the current instance of the SclSTAInterface * @@ -127,11 +130,16 @@ class SclSTAInterface : public WiFiInterface, public EMACInterface { */ int8_t get_rssi(); - /** Scans for available networks - NOT SUPPORTED + /** Scan for available networks in WiFiAccessPoint format * - * @return NSAPI_ERROR_UNSUPPORTED + * This function will block. + * + * @param aps Pointer to allocated array of WiFiAccessPoint format for discovered AP + * @param count Size of allocated @a res array, or 0 to only count available AP + * @return Number of entries in @a, or if @a count was 0 number of available networks, negative on error + * see @a nsapi_error */ - int scan(WiFiAccessPoint *res, unsigned count); + int scan(WiFiAccessPoint *aps, unsigned count); /** This function is used to indicate if the device is connected to the network. * @@ -154,6 +162,8 @@ class SclSTAInterface : public WiFiInterface, public EMACInterface { * @return SCL_SUCCESS if the Wi-Fi interface is set up successfully. */ int wifi_set_up(void); +protected: + int internal_scan(WiFiAccessPoint *aps, unsigned count, scan_result_type sres_type); private: @@ -161,5 +171,6 @@ class SclSTAInterface : public WiFiInterface, public EMACInterface { char _pass[MAX_PASSWORD_LENGTH]; /**< The longest allowed passphrase + 1 */ nsapi_security_t _security; /**< Security type */ SCL_EMAC &_scl_emac; /**< SCL_EMAC object */ + scl_interface_shared_info_t &_iface_shared; }; #endif /* ifndef SCL_STA_INTERFACE_H */ diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/default_wifi_interface.cpp b/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/default_wifi_interface.cpp index 59cb5ef0ab0..64ec3ea3848 100644 --- a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/default_wifi_interface.cpp +++ b/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/default_wifi_interface.cpp @@ -16,7 +16,7 @@ */ #include "SclSTAInterface.h" - +#include "scl_interface.h" /** @file * Provides function definition to override get_target_default_intance of WiFiInterface and NetworkInterface classes */ @@ -27,6 +27,7 @@ * * @return pointer to WiFiInterface object. */ +scl_interface_shared_info_t scl_iface_shared; WiFiInterface *WiFiInterface::get_target_default_instance() { diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/scl_interface.h b/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/scl_interface.h new file mode 100644 index 00000000000..5f332142ad9 --- /dev/null +++ b/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_SCL/interface/scl_interface.h @@ -0,0 +1,49 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SCL_INTERFACE_H +#define SCL_INTERFACE_H + +#include "rtos/Mutex.h" +#include "OnboardNetworkStack.h" + + +/** SclSTAInterface class + * Shared information + */ +#define IF_STATUS_ALL_IF_DOWN 0x0 +#define IF_STATUS_STA_UP 0x1 + +enum scl_default_interface_config +{ + DEFAULT_IF_NOT_SET, + DEFAULT_IF_STA, +}; + +struct scl_interface_shared_info_t { + rtos::Mutex mutex; + scl_default_interface_config default_if_cfg; + uint32_t if_status_flags; + OnboardNetworkStack::Interface *iface_sta; + scl_interface_shared_info_t() : default_if_cfg(DEFAULT_IF_NOT_SET), if_status_flags(IF_STATUS_ALL_IF_DOWN), + iface_sta(NULL) + {} +}; + +extern scl_interface_shared_info_t scl_iface_shared; + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h index f2bc0742232..2fc755e6dff 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h @@ -175,7 +175,8 @@ typedef enum { SCL_RX_TEST_MSG = 1, /**< Test message */ SCL_RX_GET_BUFFER = 2, /**< Get the buffer */ SCL_RX_GET_CONNECTION_STATUS = 3, /**< Get the connection status */ - SCL_RX_VERSION_COMPATIBILITY = 4 /**< Get the SCL version compatibility*/ + SCL_RX_SCAN_STATUS = 4, /**< Get the scan status */ + SCL_RX_VERSION_COMPATIBILITY = 5 /**< Get the SCL version compatibility*/ } scl_ipc_rx_t; /** @@ -197,7 +198,8 @@ typedef enum { SCL_TX_CONNECT = 13, /**< Wi-Fi connect */ SCL_TX_DISCONNECT = 14, /**< Wi-Fi disconnect */ SCL_TX_CONNECTION_STATUS = 15, /**< Transmit connection status */ - SCL_TX_SCL_VERSION_NUMBER = 16 /**< Transmit SCL version number */ + SCL_TX_SCL_VERSION_NUMBER = 16, /**< Transmit SCL version number */ + SCL_TX_SCAN = 17, /**< Wi-Fi scan */ } scl_ipc_tx_t; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_types.h index bda316cb796..e6585583153 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_types.h @@ -22,7 +22,7 @@ #include #include "cy_result.h" - +#include "scl_common.h" #ifndef INCLUDED_SCL_TYPES_H_ #define INCLUDED_SCL_TYPES_H_ @@ -91,6 +91,8 @@ typedef enum { SCL_SECURITY_WPA2_FBT_PSK = (WPA2_SECURITY | AES_ENABLED | FBT_ENABLED), /**< WPA2 FBT PSK Security with AES & TKIP */ SCL_SECURITY_WPA3_SAE = (WPA3_SECURITY | AES_ENABLED), /**< WPA3 Security with AES */ SCL_SECURITY_WPA3_WPA2_PSK = (WPA3_SECURITY | WPA2_SECURITY | AES_ENABLED), /**< WPA3 WPA2 PSK Security with AES */ + SCL_SECURITY_WPA2_WPA_PSK = (WPA2_SECURITY | WPA_SECURITY | AES_ENABLED), /**< WPA2 WPA PSK Security with AES */ + SCL_SECURITY_WPA2_WPA_TKIP_PSK = (WPA2_SECURITY | WPA_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA2 WPA PSK Security with AES & TKIP*/ SCL_SECURITY_WPA_TKIP_ENT = (ENTERPRISE_ENABLED | WPA_SECURITY | TKIP_ENABLED), /**< WPA Enterprise Security with TKIP */ SCL_SECURITY_WPA_AES_ENT = (ENTERPRISE_ENABLED | WPA_SECURITY | AES_ENABLED), /**< WPA Enterprise Security with AES */ @@ -109,6 +111,160 @@ typedef enum { SCL_SECURITY_FORCE_32_BIT = 0x7fffffff /**< Exists only to force scl_security_t type to 32 bits */ } scl_security_t; + + +/** + * Enumeration of 802.11 radio bands + */ +typedef enum +{ + SCL_802_11_BAND_5GHZ = 0, /**< Denotes 5GHz radio band */ + SCL_802_11_BAND_2_4GHZ = 1 /**< Denotes 2.4GHz radio band */ +} scl_802_11_band_t; + +/** Structure for storing 802.11 powersave listen interval values \n + * See @ref scl_wifi_get_listen_interval for more information + */ +typedef struct +{ + uint8_t beacon; /**< Listen interval in beacon periods */ + uint8_t dtim; /**< Listen interval in DTIM periods */ + uint16_t assoc; /**< Listen interval as sent to APs */ +} scl_listen_interval_t; + +/** + * Enumeration of methods of scanning + */ +typedef enum +{ + SCL_SCAN_TYPE_ACTIVE = 0x00, /**< Actively scan a network by sending 802.11 probe(s) */ + SCL_SCAN_TYPE_PASSIVE = 0x01, /**< Passively scan a network by listening for beacons from APs */ + SCL_SCAN_TYPE_PNO = 0x02, /**< Use preferred network offload to detect an AP */ + SCL_SCAN_TYPE_PROHIBITED_CHANNELS = 0x04, /**< Permit (passively) scanning a channel that isn't valid for the current country */ + SCL_SCAN_TYPE_NO_BSSID_FILTER = 0x08 /**< Return a scan record for each beacon or probe response RX'ed */ +} scl_scan_type_t; + +/** + * Enumeration of network types + */ +typedef enum +{ + SCL_BSS_TYPE_INFRASTRUCTURE = 0, /**< Denotes infrastructure network */ + SCL_BSS_TYPE_ADHOC = 1, /**< Denotes an 802.11 ad-hoc IBSS network */ + SCL_BSS_TYPE_ANY = 2, /**< Denotes either infrastructure or ad-hoc network */ + SCL_BSS_TYPE_MESH = 3, /**< Denotes 802.11 mesh network */ + + SCL_BSS_TYPE_UNKNOWN = -1 /**< May be returned by scan function if BSS type is unknown. Do not pass this to the Join function */ +} scl_bss_type_t; + +/** + * Structure for storing a Service Set Identifier (i.e. Name of Access Point) + */ +typedef struct +{ + uint8_t length; /**< SSID length */ + uint8_t value[SSID_NAME_SIZE]; /**< SSID name (AP name) */ +} scl_ssid_t; + +/** + * Structure for storing scan status + */ +typedef enum +{ + SCL_SCAN_INCOMPLETE = 0, /**< Denotes that scan is not finished */ + SCL_SCAN_COMPLETED_SUCCESSFULLY, /**< Successful completion of scan */ + SCL_SCAN_ABORTED, /**< Scan is aborted */ +} scl_scan_status_t; + +/** + * Structure for storing extended scan parameters + */ +typedef struct +{ + int32_t number_of_probes_per_channel; /**< Number of probes to send on each channel */ + int32_t scan_active_dwell_time_per_channel_ms; /**< Period of time to wait on each channel when active scanning */ + int32_t scan_passive_dwell_time_per_channel_ms; /**< Period of time to wait on each channel when passive scanning */ + int32_t scan_home_channel_dwell_time_between_channels_ms; /**< Period of time to wait on the home channel when scanning. Only relevant if associated. */ +} scl_scan_extended_params_t; + +/** + * Structure for storing scan results + */ +#pragma pack(1) +typedef struct scl_scan_result +{ + scl_ssid_t SSID; /**< Service Set Identification (i.e. Name of Access Point) */ + scl_mac_t BSSID; /**< Basic Service Set Identification (i.e. MAC address of Access Point) */ + int16_t signal_strength; /**< Receive Signal Strength Indication in dBm. <-90=Very poor, >-30=Excellent */ + uint32_t max_data_rate; /**< Maximum data rate in kilobits/s */ + scl_bss_type_t bss_type; /**< Network type */ + scl_security_t security; /**< Security type */ + uint8_t channel; /**< Radio channel that the AP beacon was received on */ + scl_802_11_band_t band; /**< Radio band */ + uint8_t ccode[2]; /**< Two letter ISO country code from AP */ + uint8_t flags; /**< flags */ + struct scl_scan_result *next; /**< Pointer to the next scan result */ + uint8_t *ie_ptr; /**< Pointer to received Beacon/Probe Response IE(Information Element) */ + uint32_t ie_len; /**< Length of IE(Information Element) */ +} scl_scan_result_t; +#pragma pack() + +/** + * Structure to store scan result parameters for each AP + */ +typedef struct scl_simple_scan_result +{ + scl_ssid_t SSID; /**< Service Set Identification (i.e. Name of Access Point) */ + scl_mac_t BSSID; /**< Basic Service Set Identification (i.e. MAC address of Access Point) */ + int16_t signal_strength; /**< Receive Signal Strength Indication in dBm. <-90=Very poor, >-30=Excellent */ + scl_security_t security; /**< Security type */ + uint8_t channel; /**< Radio channel that the AP beacon was received on */ +} scl_sync_scan_result_t; + +typedef uint16_t wl_chanspec_t; /**< Channel specified in uint16_t */ +#define MCSSET_LEN 16 /**< Maximum allowed mcs rate */ + +/** BSS(Basic Service Set) information structure + * + * Applications MUST CHECK ie_offset field and length field to access IEs(Information Elements) and + * next bss_info structure in a vector (in scl_sync_scan_result_t) + */ +typedef struct wl_bss_info_struct +{ + uint32_t version; /**< version field */ + uint32_t length; /**< byte length of data in this record, starting at version and including IEs */ + scl_mac_t BSSID; /**< Unique 6-byte MAC address */ + uint16_t beacon_period; /**< Interval between two consecutive beacon frames. Units are Kusec */ + uint16_t capability; /**< Capability information */ + uint8_t SSID_len; /**< SSID length */ + uint8_t SSID[32]; /**< Array to store SSID */ + struct + { + uint32_t count; /**< Count of rates in this set */ + uint8_t rates[16]; /**< rates in 500kbps units, higher bit set if basic */ + } rateset; /**< supported rates */ + wl_chanspec_t chanspec; /**< Channel specification for basic service set */ + uint16_t atim_window; /**< Announcement traffic indication message window size. Units are Kusec */ + uint8_t dtim_period; /**< Delivery traffic indication message period */ + int16_t RSSI; /**< receive signal strength (in dBm) */ + int8_t phy_noise; /**< noise (in dBm) */ + + uint8_t n_cap; /**< BSS is 802.11N Capable */ + uint32_t nbss_cap; /**< 802.11N BSS Capabilities (based on HT_CAP_*) */ + uint8_t ctl_ch; /**< 802.11N BSS control channel number */ + uint32_t reserved32[1]; /**< Reserved for expansion of BSS properties */ + uint8_t flags; /**< flags */ + uint8_t reserved[3]; /**< Reserved for expansion of BSS properties */ + uint8_t basic_mcs[MCSSET_LEN]; /**< 802.11N BSS required MCS set */ + + uint16_t ie_offset; /**< offset at which IEs start, from beginning */ + uint32_t ie_length; /**< byte length of Information Elements */ + int16_t SNR; /**< Average SNR(signal to noise ratio) during frame reception */ + /* Add new fields here */ + /* variable length Information Elements */ +} wl_bss_info_t; + + #ifdef __cplusplus } /* extern "C" */ #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_wifi_api.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_wifi_api.h index f880559a52b..62f8cf81a44 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_wifi_api.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_wifi_api.h @@ -26,6 +26,7 @@ #include #include "scl_common.h" +#include "scl_types.h" #ifndef INCLUDED_SCL_WIFI_API_H #define INCLUDED_SCL_WIFI_API_H @@ -145,6 +146,54 @@ extern void scl_network_process_ethernet_data(scl_buffer_t buffer); */ extern void scl_emac_wifi_link_state_changed(bool state_up); +/** Scan result callback function pointer type + * + * @param result_ptr A pointer to the pointer that indicates where to put the next scan result + * @param user_data User provided data + * @param status Status of scan process + */ +typedef void (*scl_scan_result_callback_t)(scl_scan_result_t *result_ptr, void *user_data, scl_scan_status_t status); + +/** Initiates a scan to search for 802.11 networks. + * + * The scan progressively accumulates results over time, and may take between 1 and 10 seconds to complete. + * The results of the scan will be individually provided to the callback function. + * Note: The callback function will be executed in the context of the SCL thread and so must not perform any + * actions that may cause a bus transaction. + * + * @param scan_type Specifies whether the scan should be Active, Passive or scan Prohibited channels + * @param bss_type Specifies whether the scan should search for Infrastructure networks (those using + * an Access Point), Ad-hoc networks, or both types. + * @param optional_ssid If this is non-Null, then the scan will only search for networks using the specified SSID. + * @param optional_mac If this is non-Null, then the scan will only search for networks where + * the BSSID (MAC address of the Access Point) matches the specified MAC address. + * @param optional_channel_list If this is non-Null, then the scan will only search for networks on the + * specified channels - array of channel numbers to search, terminated with a zero + * @param optional_extended_params If this is non-Null, then the scan will obey the specifications about + * dwell times and number of probes. + * @param callback The callback function which will receive and process the result data. + * @param result_ptr Pointer to a pointer to a result storage structure. + * @param user_data user specific data that will be passed directly to the callback function + * + * @note - When scanning specific channels, devices with a strong signal strength on nearby channels may be detected + * - Callback must not use blocking functions, nor use SCL functions, since it is called from the context of the + * SCL thread. + * - The callback, result_ptr and user_data variables will be referenced after the function returns. + * Those variables must remain valid until the scan is complete. + * + * @return SCL_SUCCESS or Error code + */ +extern uint32_t scl_wifi_scan(scl_scan_type_t scan_type, + scl_bss_type_t bss_type, + const scl_ssid_t *optional_ssid, + const scl_mac_t *optional_mac, + const uint16_t *optional_channel_list, + const scl_scan_extended_params_t *optional_extended_params, + scl_scan_result_callback_t callback, + scl_scan_result_t *result_ptr, + void *user_data); + +extern scl_scan_result_callback_t scan_callback; #ifdef __cplusplus } /* extern "C" */ #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/IPC/scl_ipc.c b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/IPC/scl_ipc.c index aa907453334..a24b67a4cf3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/IPC/scl_ipc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/IPC/scl_ipc.c @@ -26,6 +26,8 @@ #include "mbed_wait_api.h" #include "string.h" #include "nsapi_types.h" +#include "scl_wifi_api.h" +#include "scl_types.h" /****************************************************** ** Macros *******************************************************/ @@ -280,6 +282,12 @@ scl_result_t scl_end(void) /** Thread to handle the received buffer */ + +struct scan_callback_data { + scl_scan_result_t *result_ptr; + void *user_data; + scl_scan_status_t status; +}; static void scl_rx_handler(void) { char *buffer = NULL; @@ -289,6 +297,8 @@ static void scl_rx_handler(void) scl_buffer_t cp_buffer; uint32_t rx_ipc_size; int *rx_cp_buffer; + struct scan_callback_data* scan_callback_data_for_cp; + SCL_LOG(("Starting CP Rx thread\r\n")); scl_receive = Cy_IPC_Drv_GetIpcBaseAddress(SCL_RX_CHANNEL); @@ -328,6 +338,16 @@ static void scl_rx_handler(void) SCL_LOG(("connection status = %d\r\n", connection_status)); break; } + case SCL_RX_SCAN_STATUS: { + rx_cp_buffer = (int*) REG_IPC_STRUCT_DATA1(scl_receive); + scan_callback_data_for_cp = (struct scan_callback_data*) scl_buffer_get_current_piece_data_pointer(rx_cp_buffer); + + scan_callback(scan_callback_data_for_cp->result_ptr,scan_callback_data_for_cp->user_data,scan_callback_data_for_cp->status); + scl_buffer_release(rx_cp_buffer,SCL_NETWORK_RX); + REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE; + + break; + } default: { SCL_LOG(("incorrect IPC from Network Processor\r\n")); REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_wifi_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_wifi_api.c index f6fc3dc2ad5..53a2b370904 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_wifi_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_wifi_api.c @@ -17,6 +17,7 @@ #include "scl_wifi_api.h" #include "scl_ipc.h" +#include "scl_types.h" /****************************************************** * Variables Definitions @@ -27,6 +28,20 @@ typedef struct { uint32_t retval; } scl_mac; +typedef struct { + scl_scan_type_t scan_type; + scl_bss_type_t bss_type; + const scl_ssid_t *optional_ssid; + const scl_mac_t *optional_mac; + const uint16_t *optional_channel_list; + const scl_scan_extended_params_t *optional_extended_params; + //scl_scan_result_callback_t callback; + scl_scan_result_t *result_ptr; + void *user_data; +} scl_scan_parameters_for_np_t; + +scl_scan_result_callback_t scan_callback; + /****************************************************** * Function Definitions ******************************************************/ @@ -158,3 +173,35 @@ scl_result_t scl_wifi_get_rssi(int32_t *rssi) return SCL_ERROR; } } + +/* + * NOTE: search references of function wlu_get in wl/exe/wlu.c to find what format the returned IOCTL data is. + */ +uint32_t scl_wifi_scan(scl_scan_type_t scan_type, + scl_bss_type_t bss_type, + const scl_ssid_t *optional_ssid, + const scl_mac_t *optional_mac, + const uint16_t *optional_channel_list, + const scl_scan_extended_params_t *optional_extended_params, + scl_scan_result_callback_t callback, + scl_scan_result_t *result_ptr, + void *user_data + ) +{ + scl_scan_parameters_for_np_t scl_scan_parameters_for_np; + scl_result_t retval = SCL_SUCCESS; + /* fill the scan parameters to a structure and send it to NP */ + scl_scan_parameters_for_np.scan_type = scan_type; + scl_scan_parameters_for_np.bss_type = bss_type; + scl_scan_parameters_for_np.optional_ssid = optional_ssid; + scl_scan_parameters_for_np.optional_mac = optional_mac; + scl_scan_parameters_for_np.optional_channel_list = optional_channel_list; + scl_scan_parameters_for_np.optional_extended_params = optional_extended_params; + scl_scan_parameters_for_np.result_ptr = result_ptr; + scl_scan_parameters_for_np.user_data = user_data; + /* callback to be used when there is a scan result from CP */ + scan_callback = callback; + /* send scan parameters to NP*/ + retval = scl_send_data(SCL_TX_SCAN, (char *)&scl_scan_parameters_for_np, TIMER_DEFAULT_VALUE); + return retval; +} From 522888886b4b4815ccd80abf474976bce81d5ffb Mon Sep 17 00:00:00 2001 From: Dustin Crossman Date: Mon, 10 Aug 2020 16:58:28 -0700 Subject: [PATCH 3/5] Add bootloader info to CYSBSYSKIT_01 targets.json --- targets/targets.json | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index 4667ead2c24..1c978126593 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -6214,20 +6214,28 @@ "MXCRYPTO_02" ], "macros_add": [ - "CY8C624AFNI_D43", - "CYBSP_WIFI_CAPABLE" + "CY8C624AFNI_S2D43" + ], + "macros_remove": [ + "MBED_TICKLESS" + ], + "detect_code": [ + "1912" ], + "device_name": "CY8C624AFNI-S2D43", + "mbed_ram_start": "0x08080000", + "mbed_ram_size": "0x0007F800", + "mbed_rom_start": "0x10180000", + "mbed_rom_size": "0x80000", + "bootloader_supported": true, + "forced_reset_timeout": 5, + "post_binary_hook": { + "function": "PSOC6Code.complete" + }, "overrides": { "network-default-interface-type": "WIFI", "deep-sleep-latency": 0 }, - "detect_code": [ - "1912" - ], - "macros_remove": [ - "CYBSP_WIFI_CAPABLE", - "MBED_TICKLESS" - ], "config": { "np_cloud_disable": { "help": "Value: Tells the np to connect to cloud or not", @@ -6237,10 +6245,6 @@ "help": "Value: Tells the np to connect to wifi with its network credentials or wait till cp provides network credentials to it", "value": false } - }, - "forced_reset_timeout": 5, - "post_binary_hook": { - "function": "PSOC6Code.complete" } }, "GD32_Target": { From 79c7c3d6227a2ec05a8475be8affee8fc6965f3b Mon Sep 17 00:00:00 2001 From: Dustin Crossman Date: Thu, 13 Aug 2020 09:28:55 -0700 Subject: [PATCH 4/5] Add back sectors definition to CYSBSYSKIT_01 target. --- targets/targets.json | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/targets/targets.json b/targets/targets.json index 1c978126593..18203ab1d9d 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -6228,6 +6228,12 @@ "mbed_rom_start": "0x10180000", "mbed_rom_size": "0x80000", "bootloader_supported": true, + "sectors": [ + [ + 270008320, + 512 + ] + ], "forced_reset_timeout": 5, "post_binary_hook": { "function": "PSOC6Code.complete" From fbeae966b2e6479ad9e900e63e5f2ecdaeddeed8 Mon Sep 17 00:00:00 2001 From: Dustin Crossman Date: Tue, 18 Aug 2020 09:45:47 -0700 Subject: [PATCH 5/5] Add sectors info for CYSBSYSKIT to arm_pack_manager/index.json. --- tools/arm_pack_manager/index.json | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index 739fb19fa9c..3e6da656e31 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -41063,6 +41063,12 @@ "version": "1.0.0", "url": "https://github.com/cypresssemiconductorco/cmsis-packs/raw/master/PSoC6_DFP/" }, + "sectors": [ + [ + 0, + 512 + ] + ], "vendor": "Cypress:19", "family": "PSoC 62", "sub_family": null