From cadc32894789ccf25debc3641501352483c83dbf Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Wed, 2 Jun 2021 09:26:29 +0200 Subject: [PATCH] STM32G0: correct voltage scaling control --- .../TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c | 1 + .../TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/system_clock.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c index e2f541a310f..6d20b8a9e4e 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c @@ -99,6 +99,7 @@ uint8_t SetSysClock_PLL_HSI(void) /** Configure the main internal regulator output voltage */ + __HAL_RCC_PWR_CLK_ENABLE(); HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); /** Initializes the CPU, AHB and APB busses clocks */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/system_clock.c b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/system_clock.c index 5b79cdf0582..996533d1156 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/system_clock.c @@ -97,6 +97,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) /** Configure the main internal regulator output voltage */ + __HAL_RCC_PWR_CLK_ENABLE(); HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); /** Initializes the CPU, AHB and APB busses clocks */ @@ -139,6 +140,7 @@ uint8_t SetSysClock_PLL_HSI(void) /** Configure the main internal regulator output voltage */ + __HAL_RCC_PWR_CLK_ENABLE(); HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); /** Initializes the CPU, AHB and APB busses clocks */