From 8e8ccee98e43623e8899ba7274010c5a1674097c Mon Sep 17 00:00:00 2001 From: Mahadevan Mahesh Date: Mon, 22 Aug 2016 13:09:15 -0500 Subject: [PATCH 1/2] KSDK: Updated version of the SAI driver to address code-size issues Signed-off-by: Mahadevan Mahesh --- .../TARGET_K22F/drivers/fsl_sai.c | 42 +++++++++++++------ .../TARGET_K22F/drivers/fsl_sai.h | 9 ++-- .../TARGET_K66F/drivers/fsl_sai.c | 42 +++++++++++++------ .../TARGET_K66F/drivers/fsl_sai.h | 9 ++-- .../TARGET_KL43Z/drivers/fsl_sai.c | 42 +++++++++++++------ .../TARGET_KL43Z/drivers/fsl_sai.h | 9 ++-- .../TARGET_MCU_K64F/drivers/fsl_sai.c | 42 +++++++++++++------ .../TARGET_MCU_K64F/drivers/fsl_sai.h | 9 ++-- 8 files changed, 136 insertions(+), 68 deletions(-) diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c index a45e9e62134..c38165ec045 100755 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.c @@ -40,6 +40,12 @@ enum _sai_transfer_state kSAI_Error /*!< Transfer error occured. */ }; +/*! @brief Typedef for sai tx interrupt handler. */ +typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/*! @brief Typedef for sai rx interrupt handler. */ +typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -98,6 +104,10 @@ static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; /* Clock name array */ static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_tx_isr_t s_saiTxIsr; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_rx_isr_t s_saiRxIsr; /******************************************************************************* * Code @@ -231,12 +241,13 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Configure Master clock output enable */ - base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); - /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ /* Configure audio protocol */ @@ -332,12 +343,13 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Configure Master clock output enable */ - base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); - /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ /* Configure audio protocol */ @@ -663,6 +675,9 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + /* Set the isr pointer */ + s_saiTxIsr = SAI_TransferTxHandleIRQ; + /* Enable Tx irq */ EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); } @@ -676,6 +691,9 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + /* Set the isr pointer */ + s_saiRxIsr = SAI_TransferRxHandleIRQ; + /* Enable Rx irq */ EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); } @@ -1011,24 +1029,24 @@ void I2S0_DriverIRQHandler(void) { if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag))) { - SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); } if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag))) { - SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); } } #else void I2S0_Tx_DriverIRQHandler(void) { assert(s_saiHandle[0][0]); - SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); } void I2S0_Rx_DriverIRQHandler(void) { assert(s_saiHandle[0][1]); - SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); } #endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */ #endif /* I2S0*/ @@ -1037,12 +1055,12 @@ void I2S0_Rx_DriverIRQHandler(void) void I2S1_Tx_DriverIRQHandler(void) { assert(s_saiHandle[1][0]); - SAI_TransferTxHandleIRQ(I2S1, s_saiHandle[1][0]); + s_saiTxIsr(I2S1, s_saiHandle[1][0]); } void I2S1_Rx_DriverIRQHandler(void) { assert(s_saiHandle[1][1]); - SAI_TransferRxHandleIRQ(I2S1, s_saiHandle[1][1]); + s_saiRxIsr(I2S1, s_saiHandle[1][1]); } #endif diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h index 72b6efd06bc..cb38688cd92 100755 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_sai.h @@ -38,7 +38,6 @@ * @{ */ -/*! @file */ /******************************************************************************* * Definitions @@ -46,7 +45,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */ /*@}*/ /*! @brief SAI return status*/ @@ -168,7 +167,7 @@ typedef enum _sai_fifo_packing } sai_fifo_packing_t; #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ -/*! @brief SAI user configure structure */ +/*! @brief SAI user configuration structure */ typedef struct _sai_config { sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ @@ -276,7 +275,7 @@ extern "C" { * because the clock is not enabled. * * @param base SAI base pointer - * @param config SAI configure structure. + * @param config SAI configuration structure. */ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); @@ -292,7 +291,7 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); * because the clock is not enabled. * * @param base SAI base pointer - * @param config SAI configure structure. + * @param config SAI configuration structure. */ void SAI_RxInit(I2S_Type *base, const sai_config_t *config); diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.c b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.c index a45e9e62134..c38165ec045 100644 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.c +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.c @@ -40,6 +40,12 @@ enum _sai_transfer_state kSAI_Error /*!< Transfer error occured. */ }; +/*! @brief Typedef for sai tx interrupt handler. */ +typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/*! @brief Typedef for sai rx interrupt handler. */ +typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -98,6 +104,10 @@ static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; /* Clock name array */ static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_tx_isr_t s_saiTxIsr; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_rx_isr_t s_saiRxIsr; /******************************************************************************* * Code @@ -231,12 +241,13 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Configure Master clock output enable */ - base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); - /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ /* Configure audio protocol */ @@ -332,12 +343,13 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Configure Master clock output enable */ - base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); - /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ /* Configure audio protocol */ @@ -663,6 +675,9 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + /* Set the isr pointer */ + s_saiTxIsr = SAI_TransferTxHandleIRQ; + /* Enable Tx irq */ EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); } @@ -676,6 +691,9 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + /* Set the isr pointer */ + s_saiRxIsr = SAI_TransferRxHandleIRQ; + /* Enable Rx irq */ EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); } @@ -1011,24 +1029,24 @@ void I2S0_DriverIRQHandler(void) { if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag))) { - SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); } if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag))) { - SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); } } #else void I2S0_Tx_DriverIRQHandler(void) { assert(s_saiHandle[0][0]); - SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); } void I2S0_Rx_DriverIRQHandler(void) { assert(s_saiHandle[0][1]); - SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); } #endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */ #endif /* I2S0*/ @@ -1037,12 +1055,12 @@ void I2S0_Rx_DriverIRQHandler(void) void I2S1_Tx_DriverIRQHandler(void) { assert(s_saiHandle[1][0]); - SAI_TransferTxHandleIRQ(I2S1, s_saiHandle[1][0]); + s_saiTxIsr(I2S1, s_saiHandle[1][0]); } void I2S1_Rx_DriverIRQHandler(void) { assert(s_saiHandle[1][1]); - SAI_TransferRxHandleIRQ(I2S1, s_saiHandle[1][1]); + s_saiRxIsr(I2S1, s_saiHandle[1][1]); } #endif diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.h b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.h index 72b6efd06bc..cb38688cd92 100644 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.h +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sai.h @@ -38,7 +38,6 @@ * @{ */ -/*! @file */ /******************************************************************************* * Definitions @@ -46,7 +45,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */ /*@}*/ /*! @brief SAI return status*/ @@ -168,7 +167,7 @@ typedef enum _sai_fifo_packing } sai_fifo_packing_t; #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ -/*! @brief SAI user configure structure */ +/*! @brief SAI user configuration structure */ typedef struct _sai_config { sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ @@ -276,7 +275,7 @@ extern "C" { * because the clock is not enabled. * * @param base SAI base pointer - * @param config SAI configure structure. + * @param config SAI configuration structure. */ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); @@ -292,7 +291,7 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); * because the clock is not enabled. * * @param base SAI base pointer - * @param config SAI configure structure. + * @param config SAI configuration structure. */ void SAI_RxInit(I2S_Type *base, const sai_config_t *config); diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.c b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.c index a45e9e62134..c38165ec045 100644 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.c +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.c @@ -40,6 +40,12 @@ enum _sai_transfer_state kSAI_Error /*!< Transfer error occured. */ }; +/*! @brief Typedef for sai tx interrupt handler. */ +typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/*! @brief Typedef for sai rx interrupt handler. */ +typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -98,6 +104,10 @@ static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; /* Clock name array */ static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_tx_isr_t s_saiTxIsr; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_rx_isr_t s_saiRxIsr; /******************************************************************************* * Code @@ -231,12 +241,13 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Configure Master clock output enable */ - base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); - /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ /* Configure audio protocol */ @@ -332,12 +343,13 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Configure Master clock output enable */ - base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); - /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ /* Configure audio protocol */ @@ -663,6 +675,9 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + /* Set the isr pointer */ + s_saiTxIsr = SAI_TransferTxHandleIRQ; + /* Enable Tx irq */ EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); } @@ -676,6 +691,9 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + /* Set the isr pointer */ + s_saiRxIsr = SAI_TransferRxHandleIRQ; + /* Enable Rx irq */ EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); } @@ -1011,24 +1029,24 @@ void I2S0_DriverIRQHandler(void) { if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag))) { - SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); } if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag))) { - SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); } } #else void I2S0_Tx_DriverIRQHandler(void) { assert(s_saiHandle[0][0]); - SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); } void I2S0_Rx_DriverIRQHandler(void) { assert(s_saiHandle[0][1]); - SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); } #endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */ #endif /* I2S0*/ @@ -1037,12 +1055,12 @@ void I2S0_Rx_DriverIRQHandler(void) void I2S1_Tx_DriverIRQHandler(void) { assert(s_saiHandle[1][0]); - SAI_TransferTxHandleIRQ(I2S1, s_saiHandle[1][0]); + s_saiTxIsr(I2S1, s_saiHandle[1][0]); } void I2S1_Rx_DriverIRQHandler(void) { assert(s_saiHandle[1][1]); - SAI_TransferRxHandleIRQ(I2S1, s_saiHandle[1][1]); + s_saiRxIsr(I2S1, s_saiHandle[1][1]); } #endif diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.h b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.h index 72b6efd06bc..cb38688cd92 100644 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.h +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_sai.h @@ -38,7 +38,6 @@ * @{ */ -/*! @file */ /******************************************************************************* * Definitions @@ -46,7 +45,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */ /*@}*/ /*! @brief SAI return status*/ @@ -168,7 +167,7 @@ typedef enum _sai_fifo_packing } sai_fifo_packing_t; #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ -/*! @brief SAI user configure structure */ +/*! @brief SAI user configuration structure */ typedef struct _sai_config { sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ @@ -276,7 +275,7 @@ extern "C" { * because the clock is not enabled. * * @param base SAI base pointer - * @param config SAI configure structure. + * @param config SAI configuration structure. */ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); @@ -292,7 +291,7 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); * because the clock is not enabled. * * @param base SAI base pointer - * @param config SAI configure structure. + * @param config SAI configuration structure. */ void SAI_RxInit(I2S_Type *base, const sai_config_t *config); diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c index a45e9e62134..c38165ec045 100755 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c @@ -40,6 +40,12 @@ enum _sai_transfer_state kSAI_Error /*!< Transfer error occured. */ }; +/*! @brief Typedef for sai tx interrupt handler. */ +typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/*! @brief Typedef for sai rx interrupt handler. */ +typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -98,6 +104,10 @@ static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; /* Clock name array */ static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_tx_isr_t s_saiTxIsr; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_rx_isr_t s_saiRxIsr; /******************************************************************************* * Code @@ -231,12 +241,13 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config) CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Configure Master clock output enable */ - base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); - /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ /* Configure audio protocol */ @@ -332,12 +343,13 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config) CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) - /* Configure Master clock output enable */ - base->MCR = I2S_MCR_MOE(config->mclkOutputEnable); - /* Master clock source setting */ val = (base->MCR & ~I2S_MCR_MICS_MASK); base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); #endif /* FSL_FEATURE_SAI_HAS_MCR */ /* Configure audio protocol */ @@ -663,6 +675,9 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + /* Set the isr pointer */ + s_saiTxIsr = SAI_TransferTxHandleIRQ; + /* Enable Tx irq */ EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); } @@ -676,6 +691,9 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf handle->callback = callback; handle->userData = userData; + /* Set the isr pointer */ + s_saiRxIsr = SAI_TransferRxHandleIRQ; + /* Enable Rx irq */ EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); } @@ -1011,24 +1029,24 @@ void I2S0_DriverIRQHandler(void) { if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag))) { - SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); } if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag))) { - SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); } } #else void I2S0_Tx_DriverIRQHandler(void) { assert(s_saiHandle[0][0]); - SAI_TransferTxHandleIRQ(I2S0, s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); } void I2S0_Rx_DriverIRQHandler(void) { assert(s_saiHandle[0][1]); - SAI_TransferRxHandleIRQ(I2S0, s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); } #endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */ #endif /* I2S0*/ @@ -1037,12 +1055,12 @@ void I2S0_Rx_DriverIRQHandler(void) void I2S1_Tx_DriverIRQHandler(void) { assert(s_saiHandle[1][0]); - SAI_TransferTxHandleIRQ(I2S1, s_saiHandle[1][0]); + s_saiTxIsr(I2S1, s_saiHandle[1][0]); } void I2S1_Rx_DriverIRQHandler(void) { assert(s_saiHandle[1][1]); - SAI_TransferRxHandleIRQ(I2S1, s_saiHandle[1][1]); + s_saiRxIsr(I2S1, s_saiHandle[1][1]); } #endif diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.h b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.h index 72b6efd06bc..cb38688cd92 100755 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.h +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.h @@ -38,7 +38,6 @@ * @{ */ -/*! @file */ /******************************************************************************* * Definitions @@ -46,7 +45,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */ /*@}*/ /*! @brief SAI return status*/ @@ -168,7 +167,7 @@ typedef enum _sai_fifo_packing } sai_fifo_packing_t; #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ -/*! @brief SAI user configure structure */ +/*! @brief SAI user configuration structure */ typedef struct _sai_config { sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ @@ -276,7 +275,7 @@ extern "C" { * because the clock is not enabled. * * @param base SAI base pointer - * @param config SAI configure structure. + * @param config SAI configuration structure. */ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); @@ -292,7 +291,7 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config); * because the clock is not enabled. * * @param base SAI base pointer - * @param config SAI configure structure. + * @param config SAI configuration structure. */ void SAI_RxInit(I2S_Type *base, const sai_config_t *config); From 38aeb4cdce027d353ec219cf452feb19650ad0d0 Mon Sep 17 00:00:00 2001 From: Mahadevan Mahesh Date: Mon, 22 Aug 2016 13:41:18 -0500 Subject: [PATCH 2/2] KSDK: Updated version for the flexcan driver - Add FlexCAN function pointer handler logic to save code size. - CAN driver enter/exit Freeze mode issue Signed-off-by: Mahadevan Mahesh --- .../TARGET_K66F/drivers/fsl_flexcan.c | 221 ++++++++++-------- .../TARGET_K66F/drivers/fsl_flexcan.h | 35 ++- .../TARGET_MCU_K64F/drivers/fsl_flexcan.c | 221 ++++++++++-------- .../TARGET_MCU_K64F/drivers/fsl_flexcan.h | 35 ++- 4 files changed, 284 insertions(+), 228 deletions(-) diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.c b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.c index 5a1028ba978..15e1f55f437 100644 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.c +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.c @@ -73,6 +73,9 @@ enum _flexcan_mb_code_tx kFLEXCAN_TxMbNotUsed = 0xF, /*!< Not used.*/ }; +/* Typedef for interrupt handler. */ +typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle); + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -86,23 +89,24 @@ enum _flexcan_mb_code_tx uint32_t FLEXCAN_GetInstance(CAN_Type *base); /*! - * @brief Enter FlexCAN Fraze Mode. + * @brief Enter FlexCAN Freeze Mode. * - * This function makes the FlexCAN work under Fraze Mode. + * This function makes the FlexCAN work under Freeze Mode. * * @param base FlexCAN peripheral base address. */ -static void FLEXCAN_EnterFrazeMode(CAN_Type *base); +static void FLEXCAN_EnterFreezeMode(CAN_Type *base); /*! - * @brief Exit FlexCAN Fraze Mode. + * @brief Exit FlexCAN Freeze Mode. * - * This function makes the FlexCAN leave Fraze Mode. + * This function makes the FlexCAN leave Freeze Mode. * * @param base FlexCAN peripheral base address. */ -static void FLEXCAN_ExitFrazeMode(CAN_Type *base); +static void FLEXCAN_ExitFreezeMode(CAN_Type *base); +#if !defined(NDEBUG) /*! * @brief Check if Message Buffer is occupied by Rx FIFO. * @@ -112,6 +116,19 @@ static void FLEXCAN_ExitFrazeMode(CAN_Type *base); * @param mbIdx The FlexCAN Message Buffer index. */ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +/*! + * @brief Get the first valid Message buffer ID of give FlexCAN instance. + * + * This function is a helper function for Errata 5641 workaround. + * + * @param base FlexCAN peripheral base address. + * @return The first valid Message Buffer Number. + */ +static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base); +#endif /*! * @brief Check if Message Buffer interrupt is enabled. @@ -165,6 +182,9 @@ static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS; /* Array of FlexCAN clock name. */ static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS; +/* FlexCAN ISR for transactional APIs. */ +static flexcan_isr_t s_flexcanIsr; + /******************************************************************************* * Code ******************************************************************************/ @@ -187,10 +207,10 @@ uint32_t FLEXCAN_GetInstance(CAN_Type *base) return instance; } -static void FLEXCAN_EnterFrazeMode(CAN_Type *base) +static void FLEXCAN_EnterFreezeMode(CAN_Type *base) { /* Set Freeze, Halt bits. */ - base->MCR |= CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK; + base->MCR |= CAN_MCR_HALT_MASK; /* Wait until the FlexCAN Module enter freeze mode. */ while (!(base->MCR & CAN_MCR_FRZACK_MASK)) @@ -198,10 +218,10 @@ static void FLEXCAN_EnterFrazeMode(CAN_Type *base) } } -static void FLEXCAN_ExitFrazeMode(CAN_Type *base) +static void FLEXCAN_ExitFreezeMode(CAN_Type *base) { /* Clear Freeze, Halt bits. */ - base->MCR &= ~(CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK); + base->MCR &= ~CAN_MCR_HALT_MASK; /* Wait until the FlexCAN Module exit freeze mode. */ while (base->MCR & CAN_MCR_FRZACK_MASK) @@ -209,6 +229,7 @@ static void FLEXCAN_ExitFrazeMode(CAN_Type *base) } } +#if !defined(NDEBUG) static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) { uint8_t lastOccupiedMb; @@ -221,7 +242,11 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) /* Calculate the number of last Message Buffer occupied by Rx FIFO. */ lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + if (mbIdx <= (lastOccupiedMb + 1)) +#else if (mbIdx <= lastOccupiedMb) +#endif { return true; } @@ -232,9 +257,40 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) } else { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + if (0 == mbIdx) + { + return true; + } + else + { + return false; + } +#else return false; +#endif } } +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base) +{ + uint32_t firstValidMbNum; + + if (base->MCR & CAN_MCR_RFEN_MASK) + { + firstValidMbNum = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + firstValidMbNum = ((firstValidMbNum + 1) * 2) + 6; + } + else + { + firstValidMbNum = 0; + } + + return firstValidMbNum; +} +#endif static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx) { @@ -296,7 +352,7 @@ static void FLEXCAN_Reset(CAN_Type *base) base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); #else - base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); + base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); #endif /* Reset CTRL1 and CTRL2 rigister. */ @@ -387,7 +443,7 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc /* Reset to known status. */ FLEXCAN_Reset(base); - /* Save current MCR value. */ + /* Save current MCR value and enable to enter Freeze mode(enabled by default). */ mcrTemp = base->MCR; /* Set the maximum number of Message Buffers */ @@ -448,8 +504,8 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf /* Assertion. */ assert(config); - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Cleaning previous Timing Setting. */ base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | @@ -460,59 +516,55 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) | CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg)); - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } -void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) { - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Setting Rx Message Buffer Global Mask value. */ base->RXMGMASK = mask; base->RX14MASK = mask; base->RX15MASK = mask; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } -void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) { - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Setting Rx FIFO Global Mask value. */ base->RXFGMASK = mask; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } -void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) { assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Setting Rx Individual Mask value. */ base->RXIMR[maskIdx] = mask; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) { /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Inactivate Message Buffer. */ if (enable) @@ -535,14 +587,10 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(((config) || (false == enable))); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp = 0; - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } - /* Inactivate Message Buffer. */ base->MB[mbIdx].CS = 0; @@ -574,7 +622,7 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co } } -void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable) +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable) { /* Assertion. */ assert((config) || (false == enable)); @@ -582,8 +630,8 @@ void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS); uint8_t setup_mb, i, rffn = 0; - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); if (enable) { @@ -675,8 +723,8 @@ void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con FLEXCAN_SetRxMbConfig(base, 5, NULL, false); } - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } #if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) @@ -684,25 +732,25 @@ void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) { if (enable) { - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Enable FlexCAN DMA. */ base->MCR |= CAN_MCR_DMA_MASK; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } else { - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Disable FlexCAN DMA. */ base->MCR &= ~CAN_MCR_DMA_MASK; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } } #endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ @@ -713,14 +761,10 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(txFrame); assert(txFrame->length <= 8); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp = 0; - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } - /* Check if Message Buffer is available. */ if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) { @@ -751,6 +795,11 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t /* Activate Tx Message Buffer. */ base->MB[mbIdx].CS = cs_temp; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif + return kStatus_Success; } else @@ -765,15 +814,11 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(rxFrame); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp; uint8_t rx_code; - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } - /* Read CS field of Rx Message Buffer to lock Message Buffer. */ cs_temp = base->MB[mbIdx].CS; /* Get Rx Message Buffer Code field. */ @@ -819,7 +864,7 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram } } -status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) { /* Assertion. */ assert(rxFrame); @@ -863,7 +908,7 @@ status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) } } -status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame) +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame) { /* Write Tx Message Buffer to initiate a data sending. */ if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame)) @@ -884,7 +929,7 @@ status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra } } -status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) { /* Wait until Rx Message Buffer non-empty. */ while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) @@ -898,7 +943,7 @@ status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_ return FLEXCAN_ReadRxMb(base, mbIdx, rxFrame); } -status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame) +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame) { status_t rxFifoStatus; @@ -908,7 +953,7 @@ status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rx } /* */ - rxFifoStatus = FlEXCAN_ReadRxFifo(base, rxFrame); + rxFifoStatus = FLEXCAN_ReadRxFifo(base, rxFrame); /* Clean Rx Fifo available flag. */ FLEXCAN_ClearMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag); @@ -938,6 +983,8 @@ void FLEXCAN_TransferCreateHandle(CAN_Type *base, handle->callback = callback; handle->userData = userData; + s_flexcanIsr = FLEXCAN_TransferHandleIRQ; + /* We Enable Error & Status interrupt here, because this interrupt just * report current status of FlexCAN module through Callback function. * It is insignificance without a available callback function. @@ -970,11 +1017,7 @@ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handl assert(handle); assert(xfer); assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); /* Check if Message Buffer is idle. */ if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) @@ -1017,11 +1060,7 @@ status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *ha assert(handle); assert(xfer); assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); /* Check if Message Buffer is idle. */ if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) @@ -1073,11 +1112,7 @@ void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t /* Assertion. */ assert(handle); assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Disable Message Buffer Interrupt. */ FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); @@ -1096,11 +1131,7 @@ void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint /* Assertion. */ assert(handle); assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Disable Message Buffer Interrupt. */ FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); @@ -1185,7 +1216,7 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) break; case kFLEXCAN_RxFifoFrameAvlFlag: - status = FlEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); + status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); if (kStatus_Success == status) { status = kStatus_FLEXCAN_RxFifoIdle; @@ -1273,7 +1304,7 @@ void CAN0_DriverIRQHandler(void) { assert(s_flexcanHandle[0]); - FLEXCAN_TransferHandleIRQ(CAN0, s_flexcanHandle[0]); + s_flexcanIsr(CAN0, s_flexcanHandle[0]); } #endif @@ -1282,7 +1313,7 @@ void CAN1_DriverIRQHandler(void) { assert(s_flexcanHandle[1]); - FLEXCAN_TransferHandleIRQ(CAN1, s_flexcanHandle[1]); + s_flexcanIsr(CAN1, s_flexcanHandle[1]); } #endif @@ -1291,7 +1322,7 @@ void CAN2_DriverIRQHandler(void) { assert(s_flexcanHandle[2]); - FLEXCAN_TransferHandleIRQ(CAN2, s_flexcanHandle[2]); + s_flexcanIsr(CAN2, s_flexcanHandle[2]); } #endif @@ -1300,7 +1331,7 @@ void CAN3_DriverIRQHandler(void) { assert(s_flexcanHandle[3]); - FLEXCAN_TransferHandleIRQ(CAN3, s_flexcanHandle[3]); + s_flexcanIsr(CAN3, s_flexcanHandle[3]); } #endif @@ -1309,6 +1340,6 @@ void CAN4_DriverIRQHandler(void) { assert(s_flexcanHandle[4]); - FLEXCAN_TransferHandleIRQ(CAN4, s_flexcanHandle[4]); + s_flexcanIsr(CAN4, s_flexcanHandle[4]); } #endif diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.h b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.h index b0dee77173d..13c28f357d4 100644 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.h +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexcan.h @@ -37,7 +37,6 @@ * @{ */ -/*! @file*/ /****************************************************************************** * Definitions @@ -87,10 +86,8 @@ (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */ #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \ - ( \ - ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ - ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \ - << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \ (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \ @@ -296,13 +293,13 @@ typedef struct _flexcan_frame uint32_t length : 4; /*!< CAN frame payload length in bytes(Range: 0~8). */ uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ - uint32_t reserve1 : 1; /*!< Reserved for placeholder. */ + uint32_t : 1; /*!< Reserved. */ uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */ }; struct { uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ - uint32_t reserve2 : 3; /*!< Reserved for place holder. */ + uint32_t : 3; /*!< Reserved. */ }; union { @@ -366,7 +363,7 @@ typedef struct _flexcan_rx_mb_config flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */ } flexcan_rx_mb_config_t; -/*! @brief FlexCAN Rx FIFO configure structure. */ +/*! @brief FlexCAN Rx FIFO configuration structure. */ typedef struct _flexcan_rx_fifo_config { uint32_t *idFilterTable; /*!< Pointer to FlexCAN Rx FIFO identifier filter table. */ @@ -437,7 +434,7 @@ extern "C" { * to call the FLEXCAN_Init function by passing in these parameters: * @code * flexcan_config_t flexcanConfig; - * flexcanConfig.clkSrc = KFLEXCAN_ClkSrcOsc; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; * flexcanConfig.baudRate = 125000U; * flexcanConfig.maxMbNum = 16; * flexcanConfig.enableLoopBack = false; @@ -466,7 +463,7 @@ void FLEXCAN_Deinit(CAN_Type *base); /*! * @brief Get the default configuration structure. * - * This function initializes the FlexCAN configure structure to default value. The default + * This function initializes the FlexCAN configuration structure to default value. The default * value are: * flexcanConfig->clkSrc = KFLEXCAN_ClkSrcOsc; * flexcanConfig->baudRate = 125000U; @@ -512,7 +509,7 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf * @param base FlexCAN peripheral base address. * @param mask Rx Message Buffer Global Mask value. */ -void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); /*! * @brief Sets the FlexCAN receive FIFO global mask. @@ -522,7 +519,7 @@ void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); * @param base FlexCAN peripheral base address. * @param mask Rx Fifo Global Mask value. */ -void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); /*! * @brief Sets the FlexCAN receive individual mask. @@ -538,7 +535,7 @@ void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); * @param maskIdx The Index of individual Mask. * @param mask Rx Individual Mask value. */ -void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask); +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask); /*! * @brief Configures a FlexCAN transmit message buffer. @@ -580,7 +577,7 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co * - true: Enable Rx FIFO. * - false: Disable Rx FIFO. */ -void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable); +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable); /* @} */ @@ -629,7 +626,7 @@ static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask) * @param txErrBuf Buffer to store Tx Error Counter value. * @param rxErrBuf Buffer to store Rx Error Counter value. */ -static inline void FlEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf) +static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf) { if (txErrBuf) { @@ -890,7 +887,7 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram * @retval kStatus_Success - Read Message from Rx FIFO successfully. * @retval kStatus_Fail - Rx FIFO is not enabled. */ -status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); /* @} */ @@ -910,7 +907,7 @@ status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); * @retval kStatus_Success - Write Tx Message Buffer Successfully. * @retval kStatus_Fail - Tx Message Buffer is currently in use. */ -status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame); +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame); /*! * @brief Performs a polling receive transaction on the CAN bus. @@ -924,7 +921,7 @@ status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. * @retval kStatus_Fail - Rx Message Buffer is empty. */ -status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); /*! * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus. @@ -936,7 +933,7 @@ status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_ * @retval kStatus_Success - Read Message from Rx FIFO successfully. * @retval kStatus_Fail - Rx FIFO is not enabled. */ -status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame); +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame); /*! * @brief Initializes the FlexCAN handle. diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.c b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.c index 5a1028ba978..15e1f55f437 100755 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.c +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.c @@ -73,6 +73,9 @@ enum _flexcan_mb_code_tx kFLEXCAN_TxMbNotUsed = 0xF, /*!< Not used.*/ }; +/* Typedef for interrupt handler. */ +typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle); + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -86,23 +89,24 @@ enum _flexcan_mb_code_tx uint32_t FLEXCAN_GetInstance(CAN_Type *base); /*! - * @brief Enter FlexCAN Fraze Mode. + * @brief Enter FlexCAN Freeze Mode. * - * This function makes the FlexCAN work under Fraze Mode. + * This function makes the FlexCAN work under Freeze Mode. * * @param base FlexCAN peripheral base address. */ -static void FLEXCAN_EnterFrazeMode(CAN_Type *base); +static void FLEXCAN_EnterFreezeMode(CAN_Type *base); /*! - * @brief Exit FlexCAN Fraze Mode. + * @brief Exit FlexCAN Freeze Mode. * - * This function makes the FlexCAN leave Fraze Mode. + * This function makes the FlexCAN leave Freeze Mode. * * @param base FlexCAN peripheral base address. */ -static void FLEXCAN_ExitFrazeMode(CAN_Type *base); +static void FLEXCAN_ExitFreezeMode(CAN_Type *base); +#if !defined(NDEBUG) /*! * @brief Check if Message Buffer is occupied by Rx FIFO. * @@ -112,6 +116,19 @@ static void FLEXCAN_ExitFrazeMode(CAN_Type *base); * @param mbIdx The FlexCAN Message Buffer index. */ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +/*! + * @brief Get the first valid Message buffer ID of give FlexCAN instance. + * + * This function is a helper function for Errata 5641 workaround. + * + * @param base FlexCAN peripheral base address. + * @return The first valid Message Buffer Number. + */ +static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base); +#endif /*! * @brief Check if Message Buffer interrupt is enabled. @@ -165,6 +182,9 @@ static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS; /* Array of FlexCAN clock name. */ static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS; +/* FlexCAN ISR for transactional APIs. */ +static flexcan_isr_t s_flexcanIsr; + /******************************************************************************* * Code ******************************************************************************/ @@ -187,10 +207,10 @@ uint32_t FLEXCAN_GetInstance(CAN_Type *base) return instance; } -static void FLEXCAN_EnterFrazeMode(CAN_Type *base) +static void FLEXCAN_EnterFreezeMode(CAN_Type *base) { /* Set Freeze, Halt bits. */ - base->MCR |= CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK; + base->MCR |= CAN_MCR_HALT_MASK; /* Wait until the FlexCAN Module enter freeze mode. */ while (!(base->MCR & CAN_MCR_FRZACK_MASK)) @@ -198,10 +218,10 @@ static void FLEXCAN_EnterFrazeMode(CAN_Type *base) } } -static void FLEXCAN_ExitFrazeMode(CAN_Type *base) +static void FLEXCAN_ExitFreezeMode(CAN_Type *base) { /* Clear Freeze, Halt bits. */ - base->MCR &= ~(CAN_MCR_FRZ_MASK | CAN_MCR_HALT_MASK); + base->MCR &= ~CAN_MCR_HALT_MASK; /* Wait until the FlexCAN Module exit freeze mode. */ while (base->MCR & CAN_MCR_FRZACK_MASK) @@ -209,6 +229,7 @@ static void FLEXCAN_ExitFrazeMode(CAN_Type *base) } } +#if !defined(NDEBUG) static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) { uint8_t lastOccupiedMb; @@ -221,7 +242,11 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) /* Calculate the number of last Message Buffer occupied by Rx FIFO. */ lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + if (mbIdx <= (lastOccupiedMb + 1)) +#else if (mbIdx <= lastOccupiedMb) +#endif { return true; } @@ -232,9 +257,40 @@ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) } else { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + if (0 == mbIdx) + { + return true; + } + else + { + return false; + } +#else return false; +#endif } } +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base) +{ + uint32_t firstValidMbNum; + + if (base->MCR & CAN_MCR_RFEN_MASK) + { + firstValidMbNum = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + firstValidMbNum = ((firstValidMbNum + 1) * 2) + 6; + } + else + { + firstValidMbNum = 0; + } + + return firstValidMbNum; +} +#endif static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx) { @@ -296,7 +352,7 @@ static void FLEXCAN_Reset(CAN_Type *base) base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); #else - base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); + base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); #endif /* Reset CTRL1 and CTRL2 rigister. */ @@ -387,7 +443,7 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc /* Reset to known status. */ FLEXCAN_Reset(base); - /* Save current MCR value. */ + /* Save current MCR value and enable to enter Freeze mode(enabled by default). */ mcrTemp = base->MCR; /* Set the maximum number of Message Buffers */ @@ -448,8 +504,8 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf /* Assertion. */ assert(config); - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Cleaning previous Timing Setting. */ base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | @@ -460,59 +516,55 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) | CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg)); - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } -void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) { - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Setting Rx Message Buffer Global Mask value. */ base->RXMGMASK = mask; base->RX14MASK = mask; base->RX15MASK = mask; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } -void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) { - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Setting Rx FIFO Global Mask value. */ base->RXFGMASK = mask; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } -void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) { assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Setting Rx Individual Mask value. */ base->RXIMR[maskIdx] = mask; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) { /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Inactivate Message Buffer. */ if (enable) @@ -535,14 +587,10 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(((config) || (false == enable))); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp = 0; - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } - /* Inactivate Message Buffer. */ base->MB[mbIdx].CS = 0; @@ -574,7 +622,7 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co } } -void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable) +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable) { /* Assertion. */ assert((config) || (false == enable)); @@ -582,8 +630,8 @@ void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS); uint8_t setup_mb, i, rffn = 0; - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); if (enable) { @@ -675,8 +723,8 @@ void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con FLEXCAN_SetRxMbConfig(base, 5, NULL, false); } - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } #if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) @@ -684,25 +732,25 @@ void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) { if (enable) { - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Enable FlexCAN DMA. */ base->MCR |= CAN_MCR_DMA_MASK; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } else { - /* Enter Fraze Mode. */ - FLEXCAN_EnterFrazeMode(base); + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); /* Disable FlexCAN DMA. */ base->MCR &= ~CAN_MCR_DMA_MASK; - /* Exit Fraze Mode. */ - FLEXCAN_ExitFrazeMode(base); + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); } } #endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ @@ -713,14 +761,10 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(txFrame); assert(txFrame->length <= 8); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp = 0; - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } - /* Check if Message Buffer is available. */ if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) { @@ -751,6 +795,11 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t /* Activate Tx Message Buffer. */ base->MB[mbIdx].CS = cs_temp; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif + return kStatus_Success; } else @@ -765,15 +814,11 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(rxFrame); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp; uint8_t rx_code; - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } - /* Read CS field of Rx Message Buffer to lock Message Buffer. */ cs_temp = base->MB[mbIdx].CS; /* Get Rx Message Buffer Code field. */ @@ -819,7 +864,7 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram } } -status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) { /* Assertion. */ assert(rxFrame); @@ -863,7 +908,7 @@ status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) } } -status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame) +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame) { /* Write Tx Message Buffer to initiate a data sending. */ if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame)) @@ -884,7 +929,7 @@ status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra } } -status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) { /* Wait until Rx Message Buffer non-empty. */ while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) @@ -898,7 +943,7 @@ status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_ return FLEXCAN_ReadRxMb(base, mbIdx, rxFrame); } -status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame) +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame) { status_t rxFifoStatus; @@ -908,7 +953,7 @@ status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rx } /* */ - rxFifoStatus = FlEXCAN_ReadRxFifo(base, rxFrame); + rxFifoStatus = FLEXCAN_ReadRxFifo(base, rxFrame); /* Clean Rx Fifo available flag. */ FLEXCAN_ClearMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag); @@ -938,6 +983,8 @@ void FLEXCAN_TransferCreateHandle(CAN_Type *base, handle->callback = callback; handle->userData = userData; + s_flexcanIsr = FLEXCAN_TransferHandleIRQ; + /* We Enable Error & Status interrupt here, because this interrupt just * report current status of FlexCAN module through Callback function. * It is insignificance without a available callback function. @@ -970,11 +1017,7 @@ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handl assert(handle); assert(xfer); assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); /* Check if Message Buffer is idle. */ if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) @@ -1017,11 +1060,7 @@ status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *ha assert(handle); assert(xfer); assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, xfer->mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); /* Check if Message Buffer is idle. */ if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) @@ -1073,11 +1112,7 @@ void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t /* Assertion. */ assert(handle); assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Disable Message Buffer Interrupt. */ FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); @@ -1096,11 +1131,7 @@ void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint /* Assertion. */ assert(handle); assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); - - if (FLEXCAN_IsMbOccupied(base, mbIdx)) - { - assert(false); - } + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Disable Message Buffer Interrupt. */ FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); @@ -1185,7 +1216,7 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) break; case kFLEXCAN_RxFifoFrameAvlFlag: - status = FlEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); + status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); if (kStatus_Success == status) { status = kStatus_FLEXCAN_RxFifoIdle; @@ -1273,7 +1304,7 @@ void CAN0_DriverIRQHandler(void) { assert(s_flexcanHandle[0]); - FLEXCAN_TransferHandleIRQ(CAN0, s_flexcanHandle[0]); + s_flexcanIsr(CAN0, s_flexcanHandle[0]); } #endif @@ -1282,7 +1313,7 @@ void CAN1_DriverIRQHandler(void) { assert(s_flexcanHandle[1]); - FLEXCAN_TransferHandleIRQ(CAN1, s_flexcanHandle[1]); + s_flexcanIsr(CAN1, s_flexcanHandle[1]); } #endif @@ -1291,7 +1322,7 @@ void CAN2_DriverIRQHandler(void) { assert(s_flexcanHandle[2]); - FLEXCAN_TransferHandleIRQ(CAN2, s_flexcanHandle[2]); + s_flexcanIsr(CAN2, s_flexcanHandle[2]); } #endif @@ -1300,7 +1331,7 @@ void CAN3_DriverIRQHandler(void) { assert(s_flexcanHandle[3]); - FLEXCAN_TransferHandleIRQ(CAN3, s_flexcanHandle[3]); + s_flexcanIsr(CAN3, s_flexcanHandle[3]); } #endif @@ -1309,6 +1340,6 @@ void CAN4_DriverIRQHandler(void) { assert(s_flexcanHandle[4]); - FLEXCAN_TransferHandleIRQ(CAN4, s_flexcanHandle[4]); + s_flexcanIsr(CAN4, s_flexcanHandle[4]); } #endif diff --git a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h index b0dee77173d..13c28f357d4 100755 --- a/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h +++ b/hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h @@ -37,7 +37,6 @@ * @{ */ -/*! @file*/ /****************************************************************************** * Definitions @@ -87,10 +86,8 @@ (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */ #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \ - ( \ - ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ - ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \ - << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \ (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \ @@ -296,13 +293,13 @@ typedef struct _flexcan_frame uint32_t length : 4; /*!< CAN frame payload length in bytes(Range: 0~8). */ uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ - uint32_t reserve1 : 1; /*!< Reserved for placeholder. */ + uint32_t : 1; /*!< Reserved. */ uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */ }; struct { uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ - uint32_t reserve2 : 3; /*!< Reserved for place holder. */ + uint32_t : 3; /*!< Reserved. */ }; union { @@ -366,7 +363,7 @@ typedef struct _flexcan_rx_mb_config flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */ } flexcan_rx_mb_config_t; -/*! @brief FlexCAN Rx FIFO configure structure. */ +/*! @brief FlexCAN Rx FIFO configuration structure. */ typedef struct _flexcan_rx_fifo_config { uint32_t *idFilterTable; /*!< Pointer to FlexCAN Rx FIFO identifier filter table. */ @@ -437,7 +434,7 @@ extern "C" { * to call the FLEXCAN_Init function by passing in these parameters: * @code * flexcan_config_t flexcanConfig; - * flexcanConfig.clkSrc = KFLEXCAN_ClkSrcOsc; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; * flexcanConfig.baudRate = 125000U; * flexcanConfig.maxMbNum = 16; * flexcanConfig.enableLoopBack = false; @@ -466,7 +463,7 @@ void FLEXCAN_Deinit(CAN_Type *base); /*! * @brief Get the default configuration structure. * - * This function initializes the FlexCAN configure structure to default value. The default + * This function initializes the FlexCAN configuration structure to default value. The default * value are: * flexcanConfig->clkSrc = KFLEXCAN_ClkSrcOsc; * flexcanConfig->baudRate = 125000U; @@ -512,7 +509,7 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf * @param base FlexCAN peripheral base address. * @param mask Rx Message Buffer Global Mask value. */ -void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); /*! * @brief Sets the FlexCAN receive FIFO global mask. @@ -522,7 +519,7 @@ void FlEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); * @param base FlexCAN peripheral base address. * @param mask Rx Fifo Global Mask value. */ -void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); /*! * @brief Sets the FlexCAN receive individual mask. @@ -538,7 +535,7 @@ void FlEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); * @param maskIdx The Index of individual Mask. * @param mask Rx Individual Mask value. */ -void FlEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask); +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask); /*! * @brief Configures a FlexCAN transmit message buffer. @@ -580,7 +577,7 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co * - true: Enable Rx FIFO. * - false: Disable Rx FIFO. */ -void FlEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable); +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable); /* @} */ @@ -629,7 +626,7 @@ static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask) * @param txErrBuf Buffer to store Tx Error Counter value. * @param rxErrBuf Buffer to store Rx Error Counter value. */ -static inline void FlEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf) +static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf) { if (txErrBuf) { @@ -890,7 +887,7 @@ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFram * @retval kStatus_Success - Read Message from Rx FIFO successfully. * @retval kStatus_Fail - Rx FIFO is not enabled. */ -status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); /* @} */ @@ -910,7 +907,7 @@ status_t FlEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); * @retval kStatus_Success - Write Tx Message Buffer Successfully. * @retval kStatus_Fail - Tx Message Buffer is currently in use. */ -status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame); +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame); /*! * @brief Performs a polling receive transaction on the CAN bus. @@ -924,7 +921,7 @@ status_t FlEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. * @retval kStatus_Fail - Rx Message Buffer is empty. */ -status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); /*! * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus. @@ -936,7 +933,7 @@ status_t FlEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_ * @retval kStatus_Success - Read Message from Rx FIFO successfully. * @retval kStatus_Fail - Rx FIFO is not enabled. */ -status_t FlEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame); +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame); /*! * @brief Initializes the FlexCAN handle.