max32655_riscv.cfg

# SPDX-License-Identifier: GPL-2.0-or-later
# Maxim Integrated MAX32655 OpenOCD target configuration file
# www.maximintegrated.com

# Set the reset pin configuration
reset_config srst_only

# set reset delay so ARM core can re-enable RISCV debugger pins
adapter srst delay 100

adapter speed 4000

# Set flash parameters
set FLASH_BASE 0x10000000
set FLASH_SIZE 0x80000
set FLC_BASE 0x40029000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
set FLASH_OPTIONS 0x01

set CHIPNAME max32xxx_riscv

jtag newtap $CHIPNAME cpu -irlen 4 -irmask 0xf -ircapture 0x5 -expected-id 0x16210197 -ignore-version
target create $CHIPNAME.cpu rvmax -chain-position $CHIPNAME.cpu

$CHIPNAME.cpu configure -work-area-phys 0x20010000 -work-area-size 0x1000

flash bank $CHIPNAME.flash max32xxx $FLASH_BASE $FLASH_SIZE 0 0 $CHIPNAME.cpu $FLC_BASE $FLASH_SECTOR $FLASH_CLK $FLASH_OPTIONS

$CHIPNAME.cpu configure -event reset-end {
    # Set the PC to the load address where the interrupt vector is stored
    reg pc Reset_Handler
}