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max32665.cfg
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max32665.cfg
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# SPDX-License-Identifier: GPL-2.0-or-later
# Maxim Integrated MAX32665 OpenOCD target configuration file
# www.maximintegrated.com
# Set the reset pin configuration
reset_config srst_only
adapter srst delay 200
set CHIPNAME max32665
# Set flash parameters
set FLASH_BASE 0x10000000
set FLASH_SIZE 0x80000
set FLC_BASE 0x40029000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
set FLASH_OPTIONS 0x01
# Enable or disable QSPI driver
set QSPI_ENABLE 0
global QSPI_VDDIOH
# 1: Run QSPI at VDDIOH (3.3V)
# 0: Run QSPI at VDDIO (1.8V)
set QSPI_VDDIOH 0
# Setup QSPI options
set QSPI_ADDR_BASE 0x08000000
set QSPI_ADDR_SIZE 0x0800000
set QSPI_OPTIONS 0x0
# Use Serial Wire Debug
transport select swd
source [find target/max32xxx.cfg]
# Add additional flash bank
set FLASH_BASE 0x10080000
set FLC_BASE 0x40029400
flash bank $_CHIPNAME.flash1 max32xxx $FLASH_BASE $FLASH_SIZE 0 0 $_CHIPNAME.cpu \
$FLC_BASE $FLASH_SECTOR $FLASH_CLK $FLASH_OPTIONS
if {$QSPI_ENABLE == 1} {
if {$QSPI_VDDIOH != 0} {
echo "Warning - using VDDIOH (3.3V) for QSPI"
}
# Initialize the flash bank
flash bank $_CHIPNAME.qspi_flash max32xxx_qspi $QSPI_ADDR_BASE $QSPI_ADDR_SIZE \
0 0 $_CHIPNAME.cpu $QSPI_OPTIONS
source [find mem_helper.tcl]
# Setup the hardware to use the QSPI peripheral
proc init_spi {} {
global QSPI_VDDIOH
set CLKDIS0_ADDR 0x40000024
set CLKDIS1_ADDR 0x40000048
set PERRST_ADDR 0x40000044
set GPIO0_EN_ADDR 0x40008000
set GPIO0_OUT_EN_ADDR 0x4000800C
set GPIO0_OUT_SET_ADDR 0x4000801C
set GPIO0_EN1_ADDR 0x40008068
set GPIO0_EN2_ADDR 0x40008074
set GPIO0_DS0_ADDR 0x400080B0
set GPIO0_DS1_ADDR 0x400080B4
set GPIO0_VSSEL_ADDR 0x400080C0
set GPIO0_SPI_MASK 0xFFFFFFC0
set GPIO0_RST_MASK 0x00000030
# Enable SPI and GPIO0 clocks
set TEMP [mrw $CLKDIS0_ADDR]
set TEMP_MOD [expr { $TEMP & 0x3FFFFFF8} ]
mww $CLKDIS0_ADDR $TEMP_MOD
# Enable the SPI XIP cache
set TEMP [mrw $CLKDIS1_ADDR]
set TEMP_MOD [expr { $TEMP & 0xFFFFE7FF} ]
mww $CLKDIS1_ADDR $TEMP_MOD
# Reset the SPI peripheral
mww $PERRST_ADDR 0x18
# Setup the SPI flash GPIO pins to AF1
# Set en0, en1, and en2 registers to 0
set TEMP [mrw $GPIO0_EN_ADDR]
set TEMP_MOD [expr { $TEMP & $GPIO0_SPI_MASK} ]
mww $GPIO0_EN_ADDR $TEMP_MOD
set TEMP [mrw $GPIO0_EN1_ADDR]
set TEMP_MOD [expr { $TEMP & $GPIO0_SPI_MASK} ]
mww $GPIO0_EN1_ADDR $TEMP_MOD
set TEMP [mrw $GPIO0_EN2_ADDR]
set TEMP_MOD [expr { $TEMP & $GPIO0_SPI_MASK} ]
mww $GPIO0_EN2_ADDR $TEMP_MOD
# Set the HOLD/RST and WP lines high
set TEMP [mrw $GPIO0_EN_ADDR]
set TEMP_MOD [expr { $TEMP | $GPIO0_RST_MASK} ]
mww $GPIO0_EN_ADDR $TEMP_MOD
set TEMP [mrw $GPIO0_OUT_EN_ADDR]
set TEMP_MOD [expr { $TEMP | $GPIO0_RST_MASK} ]
mww $GPIO0_OUT_EN_ADDR $TEMP_MOD
mww $GPIO0_OUT_SET_ADDR $GPIO0_RST_MASK
# Max drive strength
set TEMP [mrw $GPIO0_DS0_ADDR]
set TEMP_MOD [expr { $TEMP | $GPIO0_RST_MASK | ~($GPIO0_SPI_MASK) } ]
mww $GPIO0_DS0_ADDR $TEMP_MOD
set TEMP [mrw $GPIO0_DS0_ADDR]
set TEMP_MOD [expr { $TEMP | $GPIO0_RST_MASK | ~($GPIO0_SPI_MASK) } ]
mww $GPIO0_DS1_ADDR $TEMP_MOD
set TEMP [mrw $GPIO0_VSSEL_ADDR]
set TEMP_MOD [expr { $TEMP | $GPIO0_RST_MASK | ~($GPIO0_SPI_MASK) } ]
if {$QSPI_VDDIOH != 0} {
# Use VDDIOH
mww $GPIO0_VSSEL_ADDR $TEMP_MOD
} else {
# Use VDDIO
mww $GPIO0_VSSEL_ADDR [expr { !($TEMP_MOD) } ]
}
# Finish setting up the QSPI, 2 is the flash bank id for the qspi driver
max32xxx_qspi reset_deassert 2
}
$_CHIPNAME.cpu configure -event examine-end {
init_spi
}
$_CHIPNAME.cpu configure -event reset-deassert-post {
init_spi
}
}