diff --git a/base/basic.tex b/base/basic.tex index 5263689..a92c2fc 100644 --- a/base/basic.tex +++ b/base/basic.tex @@ -2,7 +2,7 @@ \chapter{Basic Architecture} \section{Addressing} -The basic addressable unit is the 8-bit byte. +The basic addressable unit is the 8-bit byte. Virtual addresses are 64bits long. \section{Data Type} @@ -29,6 +29,14 @@ \subsubsection{Word} \bitbox{32}{} \end{bytefield} +\subsection{Quadword} + +\begin{bytefield}[% + bitformatting=\fakesfbits, + endianness=big]{16} + \bitheader{0-15} \\ + \bitbox{16}{} +\end{bytefield} \subsection{Signed Integer} @@ -53,6 +61,17 @@ \subsubsection{Signed word} \bitbox{31}{} \end{bytefield} +\subsubsection{Signed quadword} + +\begin{bytefield}[% + bitwidth=\widthof{\tiny ~Sign~}, + bitformatting=\fakesfbits, + endianness=big]{16} +\bitheader{0-15} \\ + \bitbox{1}{Sign} & \bitbox{15}{} +\end{bytefield} + + \section{CPU Registers} An Athena processor includes two types of registers: general purpose registers (GPR) and control/status registers (CRS). @@ -109,6 +128,13 @@ \subsection{Control and Status Registers} \hline N° & name & read & write & Description \\ \hline + \multicolumn{5}{|c|}{Unprivileged Registers} \\ + \hline + \multicolumn{5}{|c|}{Supervisor Registers} \\ + \hline + \hline + \multicolumn{5}{|c|}{Machine Registers} \\ + \hline 0 & isa & \ok & \no & Machine ISA Register \\ 1 & status & \ok & \ok & Status Register \\ 2 & cause & \ok & \no & Cause Register \\ @@ -161,7 +187,6 @@ \subsubsection{Trap Vector Base Address Regiter} \subsection{Processor Id} - \begin{bytefield}{32} \bitheader[endianness=big]{31,1,0} \\ \bitbox{31}{base} diff --git a/base/examples.tex b/base/examples.tex new file mode 100644 index 0000000..abba585 --- /dev/null +++ b/base/examples.tex @@ -0,0 +1,3 @@ +\chapter{Examples} + +\input{base/examples/basic} \ No newline at end of file diff --git a/base/examples/basic.tex b/base/examples/basic.tex new file mode 100644 index 0000000..b2936a3 --- /dev/null +++ b/base/examples/basic.tex @@ -0,0 +1,5 @@ +\section{Basic operations} + +\subsection{Simple loop} + +\lstinputlisting[language={[Athena]Assembler}]{base/examples/loop.S} diff --git a/base/examples/loop.S b/base/examples/loop.S new file mode 100644 index 0000000..05e9d56 --- /dev/null +++ b/base/examples/loop.S @@ -0,0 +1,4 @@ + li r1, loop_count +loop: + subi r1, r1, 1 + bnez r1, loop diff --git a/base/instr.tex b/base/instr.tex index 3991483..939b4b1 100644 --- a/base/instr.tex +++ b/base/instr.tex @@ -2,6 +2,14 @@ \chapter{The Athena Instruction Set} \section{Instruction Format} +There are 4 basic Athena instruction formats: +\begin{itemize} + \item R-Format + \item I-Format + \item J-Format + \item LS-Format +\end{itemize} + \subsection{R-Format} \Rinstr{opcode}{ra}{rb}{rc}{shmat}{func} @@ -23,20 +31,15 @@ \section{Alphabetical List of Instruction} \input{base/instructions/add} \input{base/instructions/addi} \input{base/instructions/addiu} -\input{base/instructions/addu} +\input{base/instructions/addw} \input{base/instructions/and} \input{base/instructions/andi} -\input{base/instructions/b} \input{base/instructions/beq} -\input{base/instructions/beqz} \input{base/instructions/bge} \input{base/instructions/bgeu} -\input{base/instructions/bgez} \input{base/instructions/blt} \input{base/instructions/bltu} -\input{base/instructions/bltz} \input{base/instructions/bne} -\input{base/instructions/bnez} \input{base/instructions/call} \input{base/instructions/div} \input{base/instructions/divu} @@ -46,14 +49,13 @@ \section{Alphabetical List of Instruction} \input{base/instructions/lh} \input{base/instructions/lhu} \input{base/instructions/lih} +\input{base/instructions/lq} \input{base/instructions/lw} -\input{base/instructions/mod} -\input{base/instructions/modu} +\input{base/instructions/lwu} \input{base/instructions/mult} \input{base/instructions/multu} \input{base/instructions/mvsrr} \input{base/instructions/mvsrw} -\input{base/instructions/nop} \input{base/instructions/nor} \input{base/instructions/or} \input{base/instructions/ori} @@ -68,8 +70,10 @@ \section{Alphabetical List of Instruction} \input{base/instructions/sub} \input{base/instructions/subi} \input{base/instructions/subiu} -\input{base/instructions/subu} +\input{base/instructions/subw} +\input{base/instructions/sq} \input{base/instructions/sw} +\input{base/instructions/swu} \input{base/instructions/trap} \input{base/instructions/xor} \input{base/instructions/xori} diff --git a/base/instructions/add.tex b/base/instructions/add.tex index 81ab8b5..7f52b55 100644 --- a/base/instructions/add.tex +++ b/base/instructions/add.tex @@ -4,7 +4,7 @@ \subsection{ADD} \paragraph{Format} ADD ra, rb, rc -\paragraph{Purpose} Add word, Trap on Overflow +\paragraph{Purpose} Add quadword, Trap on Overflow \begin{lstlisting}[language=C] GPR[ra] = GPR[rb] + GPR[rc]; diff --git a/base/instructions/addi.tex b/base/instructions/addi.tex index 6fe8465..623335d 100644 --- a/base/instructions/addi.tex +++ b/base/instructions/addi.tex @@ -4,10 +4,10 @@ \subsection{ADDI} \paragraph{Format} ADDI ra, rb, imm -\paragraph{Purpose} Add immediate word, Trap on Overflow +\paragraph{Purpose} Add immediate sign extended, Trap on Overflow \begin{lstlisting}[language=C] - GPR[ra] = GPR[rb] + (int32_t)(imm); + GPR[ra] = GPR[rb] + SEXT(imm); \end{lstlisting} \paragraph{Exceptions:} Integer Overflow diff --git a/base/instructions/addiu.tex b/base/instructions/addiu.tex index b206dc8..38d44d1 100644 --- a/base/instructions/addiu.tex +++ b/base/instructions/addiu.tex @@ -4,8 +4,8 @@ \subsection{ADDIU} \paragraph{Format} ADDIU ra, rb, imm -\paragraph{Purpose} Add immediate word +\paragraph{Purpose} Add immediate zero extended \begin{lstlisting}[language=C] - GPR[ra] = GPR[rb] + (int32_t)(imm); + GPR[ra] = GPR[rb] + ZEXT(imm); \end{lstlisting} diff --git a/base/instructions/addu.tex b/base/instructions/addw.tex similarity index 55% rename from base/instructions/addu.tex rename to base/instructions/addw.tex index bc196aa..e55902a 100644 --- a/base/instructions/addu.tex +++ b/base/instructions/addw.tex @@ -1,11 +1,11 @@ -\subsection{ADDU} +\subsection{ADDW} \Rinstr{000000}{ra}{rb}{rc}{00000}{000010} -\paragraph{Format} ADDU ra, rb, rc +\paragraph{Format} ADDW ra, rb, rc \paragraph{Purpose} Add word \begin{lstlisting}[language=c] - GPR[ra] = GPR[rb] + GPR[rc]; + GPR[ra] = SEXT((GPR[rb] + GPR[rc])<31:0>); \end{lstlisting} diff --git a/base/instructions/and.tex b/base/instructions/and.tex index 42cfcc5..a8fd416 100644 --- a/base/instructions/and.tex +++ b/base/instructions/and.tex @@ -9,3 +9,5 @@ \subsection{AND} \begin{lstlisting}[language=c] GPR[ra] = GPR[rb] & GPR[rc]; \end{lstlisting} + +\paragraph{Exceptions:} None diff --git a/base/instructions/andi.tex b/base/instructions/andi.tex index 66b4121..a920006 100644 --- a/base/instructions/andi.tex +++ b/base/instructions/andi.tex @@ -6,5 +6,7 @@ \subsection{ANDI} \paragraph{Purpose} Logical and \begin{lstlisting}[language=c] - GPR[ra] = GPR[rb] & (uint32_t)(imm); + GPR[ra] = GPR[rb] & ZEXT(imm); \end{lstlisting} + +\paragraph{Exceptions:} None \ No newline at end of file diff --git a/base/instructions/b.tex b/base/instructions/b.tex deleted file mode 100644 index 22a9ddf..0000000 --- a/base/instructions/b.tex +++ /dev/null @@ -1,11 +0,0 @@ -\subsection{B} - -\Iinstr{001110}{00000}{00000}{offset} - -\paragraph{Format} B offset - -\paragraph{Purpose} Unconditional branch - -\begin{lstlisting}[language=c] - PC += (int32_t)offset * 4; -\end{lstlisting} diff --git a/base/instructions/beq.tex b/base/instructions/beq.tex index 9020a0a..8d99df9 100644 --- a/base/instructions/beq.tex +++ b/base/instructions/beq.tex @@ -9,6 +9,6 @@ \subsection{BEQ} \begin{lstlisting}[language=c] if (GPR[ra] == GPR[rb]) { - PC += (int32_t)offset * 4; + PC += SEXT(offset) * 4; } \end{lstlisting} diff --git a/base/instructions/beqz.tex b/base/instructions/beqz.tex deleted file mode 100644 index 6aa59e0..0000000 --- a/base/instructions/beqz.tex +++ /dev/null @@ -1,14 +0,0 @@ -\subsection{BEQZ} - -\Iinstr{001110}{ra}{00000}{offset} - -\paragraph{Format} BEQZ ra, offset - -\paragraph{Purpose} Branch on Equal Zero - -\begin{lstlisting}[language=c] - if (GPR[ra] == 0) - { - PC += (int32_t)offset * 4; - } -\end{lstlisting} diff --git a/base/instructions/bgez.tex b/base/instructions/bgez.tex deleted file mode 100644 index 6be837d..0000000 --- a/base/instructions/bgez.tex +++ /dev/null @@ -1,12 +0,0 @@ -\subsection{BGEZ} - -\Iinstr{010001}{ra}{00000}{offset} - -\paragraph{Format} BGEZ ra, offset - -\begin{lstlisting}[language=c] - if ((int32_t)GPR[ra] >= 0) - { - PC += (int32_t)offset * 4; - } -\end{lstlisting} diff --git a/base/instructions/bltz.tex b/base/instructions/bltz.tex deleted file mode 100644 index 3432c36..0000000 --- a/base/instructions/bltz.tex +++ /dev/null @@ -1,12 +0,0 @@ -\subsection{BLTZ} - -\Iinstr{010000}{ra}{00000}{offset} - -\paragraph{Format} BLTZ ra, offset - -\begin{lstlisting}[language=c] - if (GPR[ra] < 0) - { - PC += (int32_t)offset * 4; - } -\end{lstlisting} diff --git a/base/instructions/bnez.tex b/base/instructions/bnez.tex deleted file mode 100644 index aa24a5b..0000000 --- a/base/instructions/bnez.tex +++ /dev/null @@ -1,12 +0,0 @@ -\subsection{BNEZ} - -\Iinstr{001111}{ra}{00000}{offset} - -\paragraph{Format} BNEZ ra, offset - -\begin{lstlisting}[language=c] - if (GPR[ra] != 0) - { - PC += (int32_t)offset * 4; - } -\end{lstlisting} diff --git a/base/instructions/lh.tex b/base/instructions/lh.tex index 2e722b3..2e658d8 100644 --- a/base/instructions/lh.tex +++ b/base/instructions/lh.tex @@ -4,7 +4,7 @@ \subsection{LH} \paragraph{Format} LH ra, offset(rb) -\paragraph{Purpose} Loads a 16bit value from memory then sign extended to 32bit before storing to `ra` +\paragraph{Purpose} Loads a 16bit value from memory then sign extended to 64bit before storing to `ra` \begin{lstlisting}[language=C] GPR[ra] = *(int16_t)(GPR[rb] + offset); diff --git a/base/instructions/lq.tex b/base/instructions/lq.tex new file mode 100644 index 0000000..80d9780 --- /dev/null +++ b/base/instructions/lq.tex @@ -0,0 +1,11 @@ +\subsection{LQ} + +\LSinstr{001001}{ra}{rb}{11}{offset} + +\paragraph{Format} LQ ra, offset(rb) + +\paragraph{Purpose} Loads a 64bit value from memory then store to `ra` + +\begin{lstlisting}[language=C] + GPR[ra] = *(int32_t)(GPR[rb] + offset); +\end{lstlisting} \ No newline at end of file diff --git a/base/instructions/lw.tex b/base/instructions/lw.tex index 47aa8b0..f676239 100644 --- a/base/instructions/lw.tex +++ b/base/instructions/lw.tex @@ -7,5 +7,6 @@ \subsection{LW} \paragraph{Purpose} Loads a 32bit value from memory then store to `ra` \begin{lstlisting}[language=C] - GPR[ra] = *(int32_t)(GPR[rb] + offset); + vaddr = GPR[rb] + SEXT(offset); + GPR[ra] = SEXT(*vaddr<31:0>); \end{lstlisting} \ No newline at end of file diff --git a/base/instructions/lwu.tex b/base/instructions/lwu.tex new file mode 100644 index 0000000..d3a727d --- /dev/null +++ b/base/instructions/lwu.tex @@ -0,0 +1,12 @@ +\subsection{LW} + +\LSinstr{001001}{ra}{rb}{10}{offset} + +\paragraph{Format} LW ra, offset(rb) + +\paragraph{Purpose} Loads a 32bit value from memory then store to `ra` + +\begin{lstlisting}[language=C] + vaddr = GPR[rb] + SEXT(offset); + GPR[ra] = ZEXT(*vaddr<31:0>); +\end{lstlisting} \ No newline at end of file diff --git a/base/instructions/mod.tex b/base/instructions/mod.tex deleted file mode 100644 index 2f3f9ba..0000000 --- a/base/instructions/mod.tex +++ /dev/null @@ -1,11 +0,0 @@ -\subsection{MOD} - -\Rinstr{000000}{ra}{rb}{rc}{00000}{010011} - -\paragraph{Format} MOD ra, rb, rc - -\paragraph{Purpose} Perform modulo operation on signed word - -\begin{lstlisting}[language=C] - GPR[ra] = (int32_t)GPR[rb] % (int32_t)GPR[rc]; -\end{lstlisting} diff --git a/base/instructions/modu.tex b/base/instructions/modu.tex deleted file mode 100644 index dba0a42..0000000 --- a/base/instructions/modu.tex +++ /dev/null @@ -1,12 +0,0 @@ -\subsection{MODU} - -\Rinstr{000000}{ra}{rb}{rc}{00000}{010100} - -\paragraph{Format} MODU ra, rb, rc - -\paragraph{Purpose} Perform modulo operation on unsigned word - - -\begin{lstlisting}[language=C] - GPR[ra] = (uint32_t)GPR[rb] % (uint32_t)GPR[rc]; -\end{lstlisting} diff --git a/base/instructions/nop.tex b/base/instructions/nop.tex deleted file mode 100644 index 7d8f65d..0000000 --- a/base/instructions/nop.tex +++ /dev/null @@ -1,7 +0,0 @@ -\subsection{NOP} - -\Rinstr{000000}{00000}{00000}{00000}{00000}{000001} - -\paragraph{Format} NOP - -\paragraph{Purpose} Performs no operation (in fact: ADD r0, r0, r0) \ No newline at end of file diff --git a/base/instructions/ori.tex b/base/instructions/ori.tex index 3020e42..4fc1bca 100644 --- a/base/instructions/ori.tex +++ b/base/instructions/ori.tex @@ -5,5 +5,5 @@ \subsection{ORI} \paragraph{Format} ORI ra, rb, imm \begin{lstlisting}[language=C] - GPR[ra] = GPR[rb] | imm; + GPR[ra] = GPR[rb] | ZEXT(imm); \end{lstlisting} \ No newline at end of file diff --git a/base/instructions/sq.tex b/base/instructions/sq.tex new file mode 100644 index 0000000..52e9d22 --- /dev/null +++ b/base/instructions/sq.tex @@ -0,0 +1,12 @@ +\subsection{SQ} + +\LSinstr{001000}{ra}{rb}{11}{offset} + +\paragraph{Format} SQ offset(ra), rb + +\paragraph{Purpose} Store the 64bit value from the low bits of register `rb` into memory + +\begin{lstlisting}[language=C] + vaddr = GPR[ra] + SEXT(offset); + *vaddr = rb; +\end{lstlisting} \ No newline at end of file diff --git a/base/instructions/sub.tex b/base/instructions/sub.tex index 6e9a816..aaae739 100644 --- a/base/instructions/sub.tex +++ b/base/instructions/sub.tex @@ -5,3 +5,7 @@ \subsection{SUB} \paragraph{Purpose} SUB ra, rb, rc \paragraph{Exceptions:} Integer Overflow + +\begin{lstlisting}[language=C] + GPR[ra] = GPR[rb] - GPR[rc]; +\end{lstlisting} \ No newline at end of file diff --git a/base/instructions/subi.tex b/base/instructions/subi.tex index c041d33..f359212 100644 --- a/base/instructions/subi.tex +++ b/base/instructions/subi.tex @@ -3,3 +3,7 @@ \subsection{SUBI} \Iinstr{000011}{ra}{rb}{imm} \paragraph{Format} SUBI ra, rb, imm + +\begin{lstlisting}[language=C] + GPR[ra] = GPR[rb] - SEXT(imm); +\end{lstlisting} \ No newline at end of file diff --git a/base/instructions/subiu.tex b/base/instructions/subiu.tex index 99e0ec5..be90771 100644 --- a/base/instructions/subiu.tex +++ b/base/instructions/subiu.tex @@ -3,3 +3,7 @@ \subsection{SUBIU} \Iinstr{000100}{ra}{rb}{imm} \paragraph{Format} SUBIU ra, rb, imm + +\begin{lstlisting}[language=C] + GPR[ra] = GPR[rb] - ZEXT(imm); +\end{lstlisting} diff --git a/base/instructions/subu.tex b/base/instructions/subu.tex deleted file mode 100644 index 8be66f3..0000000 --- a/base/instructions/subu.tex +++ /dev/null @@ -1,5 +0,0 @@ -\subsection{SUBU} - -\Rinstr{000000}{ra}{rb}{rc}{00000}{000100} - -\paragraph{Format} SUBU ra, rb, rc \ No newline at end of file diff --git a/base/instructions/subw.tex b/base/instructions/subw.tex new file mode 100644 index 0000000..f24bcf0 --- /dev/null +++ b/base/instructions/subw.tex @@ -0,0 +1,9 @@ +\subsection{SUBW} + +\Rinstr{000000}{ra}{rb}{rc}{00000}{000100} + +\paragraph{Format} SUBW ra, rb, rc + +\begin{lstlisting}[language=c] + GPR[ra] = SEXT((GPR[rb] - GPR[rc])<31:0>); +\end{lstlisting} diff --git a/base/instructions/swu.tex b/base/instructions/swu.tex new file mode 100644 index 0000000..5fa7a6e --- /dev/null +++ b/base/instructions/swu.tex @@ -0,0 +1,11 @@ +\subsection{SW} + +\LSinstr{001000}{ra}{rb}{10}{offset} + +\paragraph{Format} SW offset(ra), rb + +\paragraph{Purpose} Store the 32bit value from the low bits of register `rb` into memory + +\begin{lstlisting}[language=C] + *(int32_t *)(offset + GPR[ra]) = rb; +\end{lstlisting} \ No newline at end of file diff --git a/base/instructions/xori.tex b/base/instructions/xori.tex index a4ae66e..015dfab 100644 --- a/base/instructions/xori.tex +++ b/base/instructions/xori.tex @@ -5,5 +5,5 @@ \subsection{XORI} \paragraph{Format} XORI ra, rb, imm \begin{lstlisting}[language=C] - GPR[ra] = GPR[rb] ^ imm; + GPR[ra] = GPR[rb] ^ ZEXT(imm); \end{lstlisting} \ No newline at end of file diff --git a/base/intro.tex b/base/intro.tex index 89adf03..b179067 100644 --- a/base/intro.tex +++ b/base/intro.tex @@ -1,5 +1,23 @@ \chapter{Introduction} -Athena is a new instruction-set-architecture (ISA) inspired by MIPS, SPARC, RISC-V and designed for fun. +Athena is a new load/store RISC architecture inspired by MIPS, SPARC, +RISC-V and designed for fun. -This document also enforce ABI which may change with ISA revision. \ No newline at end of file + +This manual also enforce ABI which may change with ISA revision. + +\section{Conventions} + +\subsection{Numbering} + +All numbers are decimal or hexadecimal unless orthewise indicated. +Hexadecimal number start with the prefix 0x. + +\subsection{Notations} + +\begin{tabular}{ | c | c | } + \hline + SEXT(x) & X is sign-extended \\ + ZEXT(x) & X is zero-extended \\ + \hline +\end{tabular} \ No newline at end of file diff --git a/base/main.tex b/base/main.tex index a7edf2f..f6817a9 100644 --- a/base/main.tex +++ b/base/main.tex @@ -28,10 +28,51 @@ keywordstyle=\color{magenta}, numberstyle=\tiny\color{codegray}, stringstyle=\color{codepurple}, + captionpos=b, + keepspaces=true, + numbers=left, + numbersep=2pt, + showspaces=false, + showstringspaces=false, + showtabs=false, + tabsize=2 } +\lstdefinelanguage[Athena]{Assembler}{ + morekeywords={li,subi,bnez}, + morekeywords=[2]{ + r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16,r17,r18,r19, + r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30,r31, + zero,a0,a1,a2,a3,a4,a5,a6,a7,v0,v1,s0,s1,s2,s3,s4,s5,s6,t0,t1,t2,t3,t4, + t5,t6,k0,k1,at,sp,go,fp,ra + }, + alsodigit=-, + morecomment=[l]; +}[keywords,comments,strings] + \lstset{style=mystyle} +\newcommand{\fakesfbits}[1]{% + \tiny + \ifnum#1=1234567890 + #1 + \else + \ifnum#1>9 + \count32=#1 + \advance\count32 by 48 + \the\count32% + \else + \ifnum#1<4 + #1% + \else + \ifnum#1=6 + $\cdots$% + \fi + \fi + \fi + \fi +} + \newcommand{\Rinstr}[6]{ \begin{bytefield}{32} \bitheader[endianness=big]{31,26,21,16,11,6,0} \\ @@ -108,6 +149,7 @@ \input{base/memory} \input{base/exception} \input{base/instr} + \input{base/examples} \appendix diff --git a/base/memory.tex b/base/memory.tex index 98ef49c..506afa2 100644 --- a/base/memory.tex +++ b/base/memory.tex @@ -1,3 +1,4 @@ \chapter{Memory Model} -Athena has an address space of $2^{32}$. +Athena has an address space of $2^{64}$. + diff --git a/base/mode.tex b/base/mode.tex index 50a5ec8..16e56fd 100644 --- a/base/mode.tex +++ b/base/mode.tex @@ -8,7 +8,7 @@ \section{Operating Mode} 0 & 00 & User Mode & U \\ 1 & 01 & Supervisor Mode & S \\ 2 & 10 & Reserved & \\ - 3 & 11 & Reserved & \\ + 3 & 11 & Machine & M \\ \hline \end{tabular}