diff --git a/Makefile.mk b/Makefile.mk
index 301a3bc8355..16b65395d60 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -99,7 +99,7 @@ PHONY+= clean-abuild coreboot check-style build_complete
 # site-local Makefile.mk must go first to override default locations (for binaries etc.)
 subdirs-y := site-local
 
-subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi src/superio/common
+subdirs-y += src/lib src/commonlib/ src/console src/device src/acpi src/superio/common
 subdirs-$(CONFIG_EC_ACPI) += src/ec/intel
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/common) $(filter-out $(wildcard src/soc/*/common),$(wildcard src/soc/*/*))
diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
index 39eadc3a7f2..06aa038caac 100644
--- a/src/acpi/acpi.c
+++ b/src/acpi/acpi.c
@@ -1489,6 +1489,16 @@ unsigned long write_acpi_tables(const unsigned long start)
 		current = fw;
 		current = acpi_align_current(current);
 		if (rsdp->xsdt_address == 0) {
+			acpi_rsdt_t *existing_rsdt = (acpi_rsdt_t *)(uintptr_t)rsdp->rsdt_address;
+
+			/*
+			 * Qemu only provides a smaller ACPI 1.0 RSDP, thus
+			 * allocate a bigger ACPI 2.0 RSDP structure.
+			 */
+			rsdp = (acpi_rsdp_t *)current;
+			current += sizeof(acpi_rsdp_t);
+			coreboot_rsdp = (uintptr_t)rsdp;
+
 			xsdt = (acpi_xsdt_t *)current;
 			current += sizeof(acpi_xsdt_t);
 			current = acpi_align_current(current);
@@ -1497,7 +1507,6 @@ unsigned long write_acpi_tables(const unsigned long start)
 			 * Qemu only creates an RSDT.
 			 * Add an XSDT based on the existing RSDT entries.
 			 */
-			acpi_rsdt_t *existing_rsdt = (acpi_rsdt_t *)(uintptr_t)rsdp->rsdt_address;
 			acpi_write_rsdp(rsdp, existing_rsdt, xsdt, oem_id);
 			acpi_write_xsdt(xsdt, oem_id, oem_table_id);
 			/*
@@ -1537,7 +1546,7 @@ unsigned long write_acpi_tables(const unsigned long start)
 
 		acpi_add_table(rsdp, ssdt);
 
-		return fw;
+		return current;
 	}
 
 	dsdt_file = cbfs_map(CONFIG_CBFS_PREFIX "/dsdt.aml", &dsdt_size);
diff --git a/src/acpi/acpigen_ps2_keybd.c b/src/acpi/acpigen_ps2_keybd.c
index 4a05225d6fd..43a1eced597 100644
--- a/src/acpi/acpigen_ps2_keybd.c
+++ b/src/acpi/acpigen_ps2_keybd.c
@@ -57,6 +57,8 @@ static const uint32_t action_keymaps[] = {
 	[PS2_KEY_KBD_BKLIGHT_TOGGLE] = KEYMAP(0x9e, KEY_KBDILLUMTOGGLE),	/* e01e */
 	[PS2_KEY_MENU] = KEYMAP(0xdd, KEY_CONTROLPANEL),	/* e0d5 */
 	[PS2_KEY_DICTATE] = KEYMAP(0xa7, KEY_DICTATE),		/* e027*/
+	[PS2_KEY_ACCESSIBILITY] = KEYMAP(0xa9, KEY_ACCESSIBILITY),	/* e029 */
+	[PS2_KEY_DO_NOT_DISTURB] = KEYMAP(0xa8, KEY_DO_NOT_DISTURB),	/* e028 */
 };
 
 /* Keymap for numeric keypad keys */
diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c
index c8eee7738cc..1c97dcc92db 100644
--- a/src/ec/google/chromeec/ec_acpi.c
+++ b/src/ec/google/chromeec/ec_acpi.c
@@ -234,6 +234,8 @@ static const enum ps2_action_key ps2_enum_val[] = {
 	[TK_MICMUTE] = PS2_KEY_MICMUTE,
 	[TK_MENU] = PS2_KEY_MENU,
 	[TK_DICTATE] = PS2_KEY_DICTATE,
+	[TK_ACCESSIBILITY] = PS2_KEY_ACCESSIBILITY,
+	[TK_DONOTDISTURB] = PS2_KEY_DO_NOT_DISTURB,
 };
 
 static void fill_ssdt_ps2_keyboard(const struct device *dev)
diff --git a/src/include/acpi/acpigen_ps2_keybd.h b/src/include/acpi/acpigen_ps2_keybd.h
index 5a55356c089..deb755bbf81 100644
--- a/src/include/acpi/acpigen_ps2_keybd.h
+++ b/src/include/acpi/acpigen_ps2_keybd.h
@@ -28,6 +28,8 @@ enum ps2_action_key {
 	PS2_KEY_MICMUTE,
 	PS2_KEY_MENU,
 	PS2_KEY_DICTATE,
+	PS2_KEY_ACCESSIBILITY,
+	PS2_KEY_DO_NOT_DISTURB,
 };
 
 #define PS2_MIN_TOP_ROW_KEYS		2
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index 2695451e768..17a5f75597e 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -44,8 +44,6 @@ chip soc/intel/skylake
 	register "SataPortsDevSlp[2]" = "1"
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
-	register "SsicPortEnable" = "0"
-	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
 	register "PmConfigSlpS3MinAssert" = "2"		# 50ms
@@ -100,7 +98,6 @@ chip soc/intel/skylake
 	# Send an extra VR mailbox command for the PS4 exit issue
 	register "SendVrMbxCmd" = "2"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref igpu		on  end
 		device ref sa_thermal	on  end
diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
index 0328ec7244c..8999aa3d638 100644
--- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
+++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
@@ -32,7 +32,6 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2]	= PchSerialIoSkipInit,
 	}"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		subsystemid 0x1025 0x1037 inherit
 		device ref system_agent	on
@@ -244,7 +243,6 @@ chip soc/intel/skylake
 		end
 		device ref heci1	on	end
 		device ref sata		on
-			register "SataMode" = "SATA_AHCI"
 			register "SataSalpSupport" = "1"
 			register "SataPortsEnable[1]" = "1"	# HDD; BIT1 in 92h-93h
 			register "SataPortsEnable[2]" = "1"	# ODD; BIT2 in 92h-93h
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index a6d16f9cdf2..92e4ba78242 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -41,7 +41,6 @@ chip soc/intel/skylake
 	# Send an extra VR mailbox command for the PS4 exit issue
 	register "SendVrMbxCmd" = "2"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref system_agent	on
 			subsystemid 0x1849 0x191f
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
index 765d17c471a..bb896aab2c5 100644
--- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
@@ -35,14 +35,12 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART
 	}"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		subsystemid 0x1558 0x1313 inherit
 		device ref system_agent	on	end
 		device ref igpu 	on	end
 		device ref sa_thermal	on	end
 		device ref south_xhci	on
-			register "SsicPortEnable" = "0"
 			# USB2
 			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A, right
 			register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)"	# 3G / LTE
@@ -60,7 +58,6 @@ chip soc/intel/skylake
 		device ref thermal	on	end
 		device ref heci1	on	end
 		device ref sata		on
-			register "SataSalpSupport" = "0"
 			# Ports
 			register "SataPortsEnable[0]" = "1"
 			register "SataPortsEnable[2]" = "1"
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index 3f71ca9e2e3..4bc61dd6c98 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -40,13 +40,6 @@ chip soc/intel/skylake
 	register "SataSalpSupport" = "1"
 	register "SataPortsEnable" = "{
 		[0] = 1,
-		[1] = 0,
-		[2] = 0,
-		[3] = 0,
-		[4] = 0,
-		[5] = 0,
-		[6] = 0,
-		[7] = 0,
 	}"
 
 	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
@@ -197,8 +190,6 @@ chip soc/intel/skylake
 		[3] = USB3_PORT_DEFAULT(OC_SKIP),	/* USB-C Port 1 */
 	}"
 
-	register "SsicPortEnable" = "0"
-
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
@@ -214,7 +205,6 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoDisabled,
 	}"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref igpu		on  end
 		device ref sa_thermal	on  end
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c b/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
index 78538631e79..be1ba08a1d9 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
@@ -5,44 +5,163 @@
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <drivers/intel/dptf/chip.h>
+#include <ec/google/chromeec/ec.h>
 #include <intelblocks/power_limit.h>
 #include <soc/pci_devs.h>
 
 
 WEAK_DEV_PTR(dptf_policy);
 
+#define SET_PSYSPL2(e, w) ((e) * (w) / 100)
+#define SET_PL2(e, w) ((e - 27) * (w) / 100)
+
+static bool get_sku_index(const struct cpu_power_limits *limits, size_t num_entries,
+					size_t *intel_idx, size_t *brox_idx)
+{
+	uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
+	u8 tdp = get_cpu_tdp();
+	size_t i = 0;
+
+	for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) {
+		if (mchid == cpuid_to_adl[i].cpu_id && tdp == cpuid_to_adl[i].cpu_tdp) {
+			*intel_idx = cpuid_to_adl[i].limits;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(cpuid_to_adl)) {
+		printk(BIOS_ERR, "Cannot find correct intel sku index (mchid = %u).\n", mchid);
+		return false;
+	}
+
+	for (i = 0; i < num_entries; i++) {
+		if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) {
+			*brox_idx = i;
+			break;
+		}
+	}
+
+	if (i == num_entries) {
+		printk(BIOS_ERR, "Cannot find correct brox sku index (mchid = %u).\n", mchid);
+		return false;
+	}
+
+	return true;
+}
+
 void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries)
 {
+	const struct device *policy_dev;
+	size_t intel_idx, brox_idx;
+	struct drivers_intel_dptf_config *config;
+	struct dptf_power_limits *settings;
+	config_t *conf;
+	struct soc_power_limits_config *soc_config;
+
 	if (!num_entries)
 		return;
 
-	const struct device *policy_dev = DEV_PTR(dptf_policy);
+	policy_dev = DEV_PTR(dptf_policy);
 	if (!policy_dev)
 		return;
 
-	struct drivers_intel_dptf_config *config = policy_dev->chip_info;
+	if (!get_sku_index(limits, num_entries, &intel_idx, &brox_idx))
+		return;
 
-	uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
+	config = policy_dev->chip_info;
+	settings = &config->controls.power_limits;
+	conf = config_of_soc();
+	soc_config = &conf->power_limits_config[intel_idx];
+	settings->pl1.min_power = limits[brox_idx].pl1_min_power;
+	settings->pl1.max_power = limits[brox_idx].pl1_max_power;
+	settings->pl2.min_power = limits[brox_idx].pl2_min_power;
+	settings->pl2.max_power = limits[brox_idx].pl2_max_power;
 
-	u8 tdp = get_cpu_tdp();
+	if (soc_config->tdp_pl2_override != 0) {
+		settings->pl2.max_power = soc_config->tdp_pl2_override * 1000;
+		settings->pl2.min_power = settings->pl2.max_power;
+	}
 
-	for (size_t i = 0; i < num_entries; i++) {
-		if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) {
-			struct dptf_power_limits *settings = &config->controls.power_limits;
-			config_t *conf = config_of_soc();
-			struct soc_power_limits_config *soc_config = conf->power_limits_config;
-			settings->pl1.min_power = limits[i].pl1_min_power;
-			settings->pl1.max_power = limits[i].pl1_max_power;
-			settings->pl2.min_power = limits[i].pl2_min_power;
-			settings->pl2.max_power = limits[i].pl2_max_power;
-			soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power,
-							   MILLIWATTS_TO_WATTS);
-			printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n",
-					limits[i].pl1_min_power,
-					limits[i].pl1_max_power,
-					limits[i].pl2_min_power,
-					limits[i].pl2_max_power,
-					limits[i].pl4_power);
-		}
+	if (soc_config->tdp_pl4 == 0)
+		soc_config->tdp_pl4 = DIV_ROUND_UP(limits[brox_idx].pl4_power,
+						MILLIWATTS_TO_WATTS);
+}
+
+/*
+ * Psys calculations
+ *
+ * We use the following:
+ *
+ * For USB C charger (Max Power):
+ * +-------------+-----+------+---------+-------+
+ * | Max Power(W)| TDP | PL2  | PsysPL2 | PL3/4 |
+ * +-------------+-----+------+---------+-------+
+ * |     30      |  15 |  17  |   25    |  25   | <--- not working yet
+ * |     45      |  15 |  26  |   38    |  38   |
+ * |     60      |  15 |  35  |   51    |  51   |
+ * |    110      |  15 |  55  |   94    |  96   |
+ * +-------------+-----+------+---------+-------+
+ */
+void variant_update_psys_power_limits(const struct cpu_power_limits *limits,
+				      const struct system_power_limits *sys_limits,
+				      size_t num_entries,
+				      const struct psys_config *config_psys)
+{
+	struct soc_power_limits_config *soc_config;
+	size_t intel_idx, brox_idx;
+	u16 volts_mv, current_ma;
+	enum usb_chg_type type;
+	u32 pl2;
+	u32 psyspl2 = 0;
+	u32 psyspl3 = 0;
+	u32 pl2_default;
+	config_t *conf;
+	u32 watts = 0;
+	int rv;
+
+	if (!num_entries)
+		return;
+
+	if (!get_sku_index(limits, num_entries, &intel_idx, &brox_idx))
+		return;
+
+	conf = config_of_soc();
+	soc_config = &conf->power_limits_config[intel_idx];
+
+	pl2_default = DIV_ROUND_UP(limits[brox_idx].pl2_max_power, MILLIWATTS_TO_WATTS);
+
+	/* Get AC adapter power */
+	rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv);
+
+	if (rv == 0 && type == USB_CHG_TYPE_PD) {
+		/* Detected USB-PD. Get max value of adapter */
+		watts = ((u32)current_ma * volts_mv) / 1000000;
 	}
+	/* If battery is present and has enough charge, add discharge rate */
+	if (CONFIG(EC_GOOGLE_CHROMEEC) && google_chromeec_is_battery_present_and_above_critical_threshold()) {
+		watts += 65;
+	}
+
+	/* We did not detect a battery or a Type-C charger */
+	if (watts == 0) {
+		return;
+	}
+
+	/* set psyspl2 to efficiency% of adapter rating */
+	psyspl2 = SET_PSYSPL2(config_psys->efficiency, watts);
+	psyspl3 = psyspl2;
+	if (watts > 60)
+		psyspl3 += 2;
+
+	/* Limit PL2 if the adapter is with lower capability */
+	pl2 = (psyspl2 > pl2_default) ? pl2_default : SET_PL2(config_psys->efficiency, watts);
+
+	/* If PL4 > psyspl3, lower it */
+	if (soc_config->tdp_pl4 > psyspl3)
+		soc_config->tdp_pl4 = psyspl3;
+
+	/* now that we're done calculating, set everything */
+	soc_config->tdp_pl2_override = pl2;
+	soc_config->tdp_psyspl2 = psyspl2;
+	soc_config->tdp_psyspl3 = psyspl3;
 }
diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb
index 424d61c6cbd..21774f88d21 100644
--- a/src/mainboard/google/brox/variants/brox/overridetree.cb
+++ b/src/mainboard/google/brox/variants/brox/overridetree.cb
@@ -133,7 +133,7 @@ chip soc/intel/alderlake
 				register "options.fan.fine_grained_control" = "1"
 				register "options.fan.step_size" = "2"
 
-				device generic 0 on end
+				device generic 0 alias dptf_policy on end
 			end
 		end # DTT
 		device ref igpu on
diff --git a/src/mainboard/google/brox/variants/brox/ramstage.c b/src/mainboard/google/brox/variants/brox/ramstage.c
index b4683203563..86418da2ad2 100644
--- a/src/mainboard/google/brox/variants/brox/ramstage.c
+++ b/src/mainboard/google/brox/variants/brox/ramstage.c
@@ -2,17 +2,53 @@
 
 #include <baseboard/variants.h>
 #include <device/pci_ids.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/power_limit.h>
 
-const struct cpu_power_limits limits[] = {
-	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
-	/* All values are for performance config as per document #686872 */
-	{ PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 },
-	{ PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000,  64000,  64000, 126000 },
-	{ PCI_DID_INTEL_RPL_P_ID_3, 15,  6000, 15000,  55000,  55000, 114000 },
+/*
+ * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
+ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
+ * Following values are for performance config as per document #640982
+ */
+
+const struct cpu_power_limits performance_efficient_limits[] = {
+	{
+		.mchid = PCI_DID_INTEL_RPL_P_ID_3,
+		.cpu_tdp = 15,
+		.pl1_min_power = 6000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 55000,
+		.pl2_max_power = 55000,
+		.pl4_power = 114000
+	},
+	{
+		.mchid = PCI_DID_INTEL_RPL_P_ID_4,
+		.cpu_tdp = 15,
+		.pl1_min_power = 6000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 55000,
+		.pl2_max_power = 55000,
+		.pl4_power = 114000
+	},
+};
+
+const struct system_power_limits sys_limits[] = {
+	/* SKU_ID, TDP (Watts), psys_pl2 (Watts) */
+	{ PCI_DID_INTEL_RPL_P_ID_3, 15, 60 },
+	{ PCI_DID_INTEL_RPL_P_ID_4, 15, 60 },
 };
 
-void variant_devtree_update(void)
+const struct psys_config psys_config = {
+	.efficiency = 86,
+};
+
+void __weak variant_devtree_update(void)
 {
-	size_t total_entries = ARRAY_SIZE(limits);
-	variant_update_power_limits(limits, total_entries);
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+
+	const struct cpu_power_limits *limits = performance_efficient_limits;
+	size_t limits_size = ARRAY_SIZE(performance_efficient_limits);
+
+	variant_update_power_limits(limits, limits_size);
+	variant_update_psys_power_limits(limits, sys_limits, limits_size, &psys_config);
 }
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 464f8ce7269..59b09e07b48 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -514,6 +514,14 @@ config BOARD_GOOGLE_TANIKS
 	select DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX
 	select INTEL_GMA_HAVE_VBT
 
+config BOARD_GOOGLE_TEREID
+	select BOARD_GOOGLE_BASEBOARD_NISSA
+	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_GENERIC_BAYHUB_LV2
+	select DRIVERS_GENERIC_GPIO_KEYS
+	select INTEL_GMA_HAVE_VBT
+	select SOC_INTEL_TWINLAKE
+
 config BOARD_GOOGLE_TIVVIKS
 	select BOARD_GOOGLE_BASEBOARD_NISSA
 	select BOARD_ROMSIZE_KB_32768
@@ -675,6 +683,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x1 if BOARD_GOOGLE_TAEKO
 	default 0x3 if BOARD_GOOGLE_TAEKO4ES
 	default 0x1 if BOARD_GOOGLE_TANIKS
+	default 0x0 if BOARD_GOOGLE_TEREID
 	default 0x0 if BOARD_GOOGLE_TIVVIKS
 	default 0x0 if BOARD_GOOGLE_TRULO
 	default 0x0 if BOARD_GOOGLE_ULDREN
@@ -767,6 +776,7 @@ config MAINBOARD_PART_NUMBER
 	default "Taeko" if BOARD_GOOGLE_TAEKO
 	default "Taeko4ES" if BOARD_GOOGLE_TAEKO4ES
 	default "Taniks" if BOARD_GOOGLE_TANIKS
+	default "Tereid" if BOARD_GOOGLE_TEREID
 	default "Tivviks" if BOARD_GOOGLE_TIVVIKS
 	default "Trulo" if BOARD_GOOGLE_TRULO
 	default "Uldren" if BOARD_GOOGLE_ULDREN
@@ -812,6 +822,7 @@ config VARIANT_DIR
 	default "mithrax" if BOARD_GOOGLE_MITHRAX
 	default "moli" if BOARD_GOOGLE_MOLI
 	default "nereid" if BOARD_GOOGLE_NEREID
+	default "nereid" if BOARD_GOOGLE_TEREID
 	default "nivviks" if BOARD_GOOGLE_NIVVIKS
 	default "nivviks" if BOARD_GOOGLE_TIVVIKS
 	default "nokris" if BOARD_GOOGLE_NOKRIS
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 3229b18cd88..a929d0197ad 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -140,6 +140,9 @@ config BOARD_GOOGLE_TAEKO4ES
 config BOARD_GOOGLE_TANIKS
 	bool "->  Taniks"
 
+config BOARD_GOOGLE_TEREID
+	bool "->  Tereid"
+
 config BOARD_GOOGLE_TIVVIKS
 	bool "-> Tivviks"
 
diff --git a/src/mainboard/google/brya/variants/orisa/gpio.c b/src/mainboard/google/brya/variants/orisa/gpio.c
index f8d021a900f..49fc02558e0 100644
--- a/src/mainboard/google/brya/variants/orisa/gpio.c
+++ b/src/mainboard/google/brya/variants/orisa/gpio.c
@@ -122,7 +122,7 @@ static const struct pad_config gpio_table[] = {
 	/* D1  : ISH_GP1 ==> SOC_GSEN2_INT# */
 	PAD_CFG_NF_LOCK(GPP_D1, NONE, NF1, LOCK_CONFIG),
 	/* D2  : ISH_GP2 ==> SEN_MODE_EC_PCH_INT_ODL */
-	PAD_CFG_NF_LOCK(GPP_D2, NONE, NF1, LOCK_CONFIG),
+	PAD_CFG_GPI_LOCK(GPP_D2, NONE, LOCK_CONFIG),
 	/* D3  : NC */
 	PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
 	/* D4  : NC */
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index dfa7a6edd4b..a2b4311d1e9 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -36,11 +36,8 @@ chip soc/intel/skylake
 	register "gen3_dec" = "0x00fc0901"
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
-	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
@@ -228,7 +225,6 @@ chip soc/intel/skylake
 	}"
 	register "tcc_offset" = "10"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref igpu		on  end
 		device ref sa_thermal	on  end
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index 44fc014a9b9..d64a9f91026 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -65,14 +65,11 @@ chip soc/intel/skylake
 	register "s0ix_enable" = true
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[1]" = "1"
 	register "SataPortsDevSlp[1]" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
-	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
@@ -305,7 +302,6 @@ chip soc/intel/skylake
 	}"
 	register "tcc_offset" = "6"     # TCC of 94C
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref igpu		on  end
 		device ref sa_thermal	on  end
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 58b421c19c0..864d73e56d4 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -35,11 +35,8 @@ chip soc/intel/skylake
 	register "dptf_enable" = "1"
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
-	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
@@ -81,7 +78,6 @@ chip soc/intel/skylake
 	# Send an extra VR mailbox command for the PS4 exit issue
 	register "SendVrMbxCmd" = "2"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref igpu		on  end
 		device ref sa_thermal	on  end
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index eb7d660ad58..181c77b9990 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -43,11 +43,8 @@ chip soc/intel/skylake
 	register "CmdTriStateDis" = "1"
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
-	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
@@ -227,7 +224,6 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
 	}"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref system_agent		on  end
 		device ref igpu			on  end
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 2425de24c0d..0317139b7cd 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -31,11 +31,8 @@ chip soc/intel/skylake
 	register "s0ix_enable" = true
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
-	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
@@ -249,7 +246,6 @@ chip soc/intel/skylake
 	# Use default SD card detect GPIO configuration
 	register "sdcard_cd_gpio" = "GPP_E15"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref system_agent		on  end
 		device ref igpu			on  end
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 334250ef5a1..2bb5e112c8b 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -40,10 +40,8 @@ chip soc/intel/skylake
 	register "s0ix_enable" = true
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
@@ -273,7 +271,6 @@ chip soc/intel/skylake
 		.psys_pmax = 101,
 	}"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref system_agent		on  end
 		device ref igpu			on  end
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 4cbc0450f02..29233c9d2a5 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -40,11 +40,8 @@ chip soc/intel/skylake
 	register "s0ix_enable" = true
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
-	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
@@ -280,7 +277,6 @@ chip soc/intel/skylake
 	# Use default SD card detect GPIO configuration
 	register "sdcard_cd_gpio" = "GPP_E15"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref system_agent 	on  end
 		device ref igpu 		on  end
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 188f0e184cc..1ef0b454abd 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -36,11 +36,8 @@ chip soc/intel/skylake
 	register "CmdTriStateDis" = "1"
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
-	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
@@ -244,7 +241,6 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
 	}"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref system_agent 	on  end
 		device ref igpu 		on  end
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 34dd2afbd30..42528cfe0e1 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -43,11 +43,8 @@ chip soc/intel/skylake
 	register "CmdTriStateDis" = "1"
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
-	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
@@ -230,7 +227,6 @@ chip soc/intel/skylake
 	# Use default SD card detect GPIO configuration
 	register "sdcard_cd_gpio" = "GPP_E15"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref system_agent 	on  end
 		device ref igpu 		on  end
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index d64213792f1..fb8aad22368 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -40,11 +40,8 @@ chip soc/intel/skylake
 	register "s0ix_enable" = true
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
-	register "SataPortsEnable[0]" = "0"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "SsicPortEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
@@ -259,7 +256,6 @@ chip soc/intel/skylake
 	# Use default SD card detect GPIO configuration
 	register "sdcard_cd_gpio" = "GPP_E15"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref system_agent		on  end
 		device ref igpu			on  end
diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb
index 3b25a425817..74780d005b5 100644
--- a/src/mainboard/hp/280_g2/devicetree.cb
+++ b/src/mainboard/hp/280_g2/devicetree.cb
@@ -7,7 +7,6 @@ chip soc/intel/skylake
 
 	register "eist_enable" = "1"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		subsystemid 0x103c 0x2b5e inherit
 		device ref peg0		on	end
diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
index b28265779a0..b57deffd857 100644
--- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
@@ -109,7 +109,6 @@ chip soc/intel/skylake
 	# Send an extra VR mailbox command for the PS4 exit issue
 	register "SendVrMbxCmd" = "2"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref igpu		on  end
 		device ref sa_thermal	on  end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
index c5b7e9469bc..ce4bf4b81bb 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
@@ -153,7 +153,6 @@ chip soc/intel/skylake
 	# Use default SD card detect GPIO configuration
 	register "sdcard_cd_gpio" = "GPP_G5"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref i2c2		off end
 		device ref i2c3		off end
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 0d9331b7c01..d09a4d18104 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -161,7 +161,6 @@ chip soc/intel/skylake
 	# Use default SD card detect GPIO configuration
 	register "sdcard_cd_gpio" = "GPP_A7"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref igpu		on  end
 		device ref sa_thermal	on  end
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index f2234a6937a..d888de4a240 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -17,7 +17,6 @@ chip soc/intel/skylake
 	# FSP Configuration
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 
 	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
@@ -196,7 +195,6 @@ chip soc/intel/skylake
 	# Use default SD card detect GPIO configuration
 	#register "sdcard_cd_gpio" = "GPP_A7"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref igpu		on end
 		device ref south_xhci	on end
diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb
index 08b90cee4fc..f5d05b8be95 100644
--- a/src/mainboard/kontron/bsl6/devicetree.cb
+++ b/src/mainboard/kontron/bsl6/devicetree.cb
@@ -63,8 +63,6 @@ chip soc/intel/skylake
 	# Send an extra VR mailbox command for the PS4 exit issue
 	register "SendVrMbxCmd" = "2"
 
-	device cpu_cluster 0 on end
-
 	device domain 0 on
 		device ref igpu		on  end
 		device ref gmm		on  end
diff --git a/src/mainboard/lenovo/m900_tiny/devicetree.cb b/src/mainboard/lenovo/m900_tiny/devicetree.cb
index e9f15d6c713..e6655b536aa 100644
--- a/src/mainboard/lenovo/m900_tiny/devicetree.cb
+++ b/src/mainboard/lenovo/m900_tiny/devicetree.cb
@@ -117,7 +117,6 @@ chip soc/intel/skylake
 	# Send an extra VR mailbox command for the PS4 exit issue
 	register "SendVrMbxCmd" = "2"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		subsystemid 0x17aa 0x30d0 inherit
 		device ref igpu on
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
index aa1f9b2a6da..f4f51b76ee9 100644
--- a/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
+++ b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
@@ -3,7 +3,6 @@
 chip soc/intel/skylake
 	register "eist_enable" = "true"
 
-	device cpu_cluster 0 on  end
 	device domain 0 on
 		device ref peg0         on	# PCIE16X
 			# These configurations are technically for PCIe root
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb
index cdddf3d2e6b..dd2fc6084c7 100644
--- a/src/mainboard/libretrend/lt1000/devicetree.cb
+++ b/src/mainboard/libretrend/lt1000/devicetree.cb
@@ -33,22 +33,14 @@ chip soc/intel/skylake
 	register "dptf_enable" = "0"
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "SataPortsEnable" = "{
 		[0] = 1,
 		[1] = 1,
 		[2] = 1,
 	}"
-	register "SataPortsDevSlp" = "{
-		[0] = 0,
-		[1] = 0,
-		[2] = 0,
-	}"
 	register "SataSpeedLimit" = "2"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "0"
-	register "SsicPortEnable" = "0"
-	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
@@ -159,7 +151,6 @@ chip soc/intel/skylake
 	# Send an extra VR mailbox command for the PS4 exit issue
 	register "SendVrMbxCmd" = "2"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref igpu		on  end
 		device ref sa_thermal	on  end
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index 87bc5de38b5..f57f97832ca 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -28,11 +28,8 @@ chip soc/intel/skylake
 	register "tcc_offset" = "5" # TCC of 95C
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
-	register "SsicPortEnable" = "0"
-	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
 	register "IslVrCmd" = "2"
@@ -112,9 +109,6 @@ chip soc/intel/skylake
 	# Enable SATA ports 1,2
 	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[1]" = "1"
-	register "SataPortsEnable[2]" = "0"
-	register "SataPortsDevSlp[0]" = "0"
-	register "SataPortsDevSlp[1]" = "0"
 
 	# Enable Root ports. 1-6 for LAN and Root Port 9
 	register "PcieRpEnable[0]" = "1"
@@ -189,7 +183,6 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoDisabled,
 	}"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref igpu		on  end
 		device ref south_xhci	on  end
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index 08a88d6a341..03d48faaa15 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -41,16 +41,10 @@ chip soc/intel/skylake
 	register "dptf_enable" = "0"
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
 	register "SataPortsEnable[0]" = "1"
-	register "SataPortsEnable[1]" = "0"
 	register "SataPortsEnable[2]" = "1"
-	register "SataPortsDevSlp[0]" = "0"
-	register "SataPortsDevSlp[2]" = "0"
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
-	register "SsicPortEnable" = "0"
-	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
 	register "PmConfigSlpS3MinAssert" = "2"		# 50ms
@@ -149,7 +143,6 @@ chip soc/intel/skylake
 	# Send an extra VR mailbox command for the PS4 exit issue
 	register "SendVrMbxCmd" = "2"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref igpu		on  end
 		device ref sa_thermal	on  end
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
index 71051be3b7e..da44d22ab44 100644
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -22,16 +22,8 @@ chip soc/intel/skylake
 	register "dptf_enable" = "0"
 
 	# FSP Configuration
-	register "SataSalpSupport" = "0"
-	register "SataPortsEnable" = "{
-		[0] = 0,
-		[1] = 0,
-		[2] = 0,
-	}"
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
-	register "SsicPortEnable" = "0"
-	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
 	register "PmConfigSlpS3MinAssert" = "2"		# 50ms
@@ -150,7 +142,6 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoDisabled,
 	}"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref igpu		on
 			register "gfx" = "GMA_STATIC_DISPLAYS(0)"
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
index 96f7d782c65..42047b256df 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
@@ -46,8 +46,6 @@ chip soc/intel/skylake
 						   LPC_IOE_EC_62_66"
 
 # Actual device tree.
-	device cpu_cluster 0 on end
-
 	device domain 0 on
 		device ref igpu		on  end
 		device ref sa_thermal	on  end
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
index 254486cf6ec..1a8be1dbb4a 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
@@ -26,7 +26,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpSusMinAssert"	= "SLP_SUS_MIN_ASSERT_4S"
 	register "PmConfigSlpAMinAssert"	= "SLP_A_MIN_ASSERT_2S"
 
-	device cpu_cluster 0 on end
 	device domain 0 on
 		device ref sa_thermal on end
 		device ref south_xhci on end
diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb
index da3327ac4c2..38578e06be1 100644
--- a/src/mainboard/system76/kbl-u/devicetree.cb
+++ b/src/mainboard/system76/kbl-u/devicetree.cb
@@ -105,8 +105,6 @@ chip soc/intel/skylake
 		.dc_loadline = 310,
 	}"
 
-	device cpu_cluster 0 on end
-
 	device domain 0 on
 		device ref system_agent on end
 		device ref igpu on end
@@ -130,7 +128,6 @@ chip soc/intel/skylake
 		end
 		device ref thermal on end
 		device ref sata on
-			register "SataSalpSupport" = "0"
 			register "SataSpeedLimit" = "2"
 			register "SataPortsEnable" = "{
 				[0] = 1,
diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb
index 102c55cc268..6538a1475b6 100644
--- a/src/soc/intel/skylake/chipset.cb
+++ b/src/soc/intel/skylake/chipset.cb
@@ -1,4 +1,5 @@
 chip soc/intel/skylake
+	device cpu_cluster 0 on end
 	device domain 0 on
 		ops pci_domain_ops
 		device gpio 0 alias pch_gpio       on  ops block_gpio_ops  end
diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go
index 00b136b03a5..d31cd6b4b61 100644
--- a/util/autoport/bd82x6x.go
+++ b/util/autoport/bd82x6x.go
@@ -194,9 +194,6 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
 			Value: "\\_SB.PCI0.GFX0.DECB",
 		})
 
-	/* SPI init */
-	MainboardIncludes = append(MainboardIncludes, "southbridge/intel/bd82x6x/pch.h")
-
 	FADT := ctx.InfoSource.GetACPI()["FACP"]
 
 	pcieHotplugMap := "{ "
@@ -297,7 +294,6 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
 	sb.WriteString(`#include <bootblock_common.h>
 #include <device/pci_ops.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-
 `)
 	usbPortConfig := "{\n"
 
diff --git a/util/autoport/main.go b/util/autoport/main.go
index 6426dd305c6..99099d51f65 100644
--- a/util/autoport/main.go
+++ b/util/autoport/main.go
@@ -837,8 +837,7 @@ func main() {
 
 	Add_gpl(dsdt)
 	dsdt.WriteString(
-		`
-#include <acpi/acpi.h>
+`#include <acpi/acpi.h>
 
 DefinitionBlock(
 	"dsdt.aml",