From 910f706bbd9aa50fbd168de4ba197547ab00a0dc Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Tue, 8 Oct 2024 10:02:04 +0800
Subject: [PATCH 01/14] MAINTAINERS: Add google/rauru to GOOGLE MEDIATEK-BASED
 MAINBOARDS

Change-Id: Ib3997e8a4fccefeaa316a07c319323e5e979e5fd
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index a418d960d14..b0b313fda20 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -397,6 +397,7 @@ F:	src/mainboard/google/corsola/
 F:	src/mainboard/google/geralt/
 F:	src/mainboard/google/kukui/
 F:	src/mainboard/google/oak/
+F:	src/mainboard/google/rauru/
 
 
 

From 71c8dac9ca9915b7f954c33e128b022f0381dd10 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Thu, 6 Jul 2023 06:20:31 +0300
Subject: [PATCH 02/14] drivers/pc80/tpm: Fix tis_readresponse()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

TPM_RDRESP_NEED_DELAY was introduced in 2018 in CB:25322 after
observing errors with SLB9635 by Infineon. It has been confirmed
also SLB9670 and SLB9672 require a fix or delay here.

Presumably, prior to CB:4388 SLB9635 did not have this problem,
as this particular TPM shipped with samsung/lumpy Chromebook since
2011. In CB:4388 the code changed from polling the status register
(+burst_count) using a 32bit read to separated 8bit reads.

So far, experiments on samsung/lumpy and SLB9635 indicate that
it would be sufficient to add a single tpm_read_status() call
to see TIS_STS_DATA_AVAILABLE as set at the time of evaluating
the loop exit condition.

Change-Id: If5c3e93c7946ebf8226f7bba47b38253f6920c61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Co-authored-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/drivers/pc80/tpm/tis.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c
index 3f863a36da7..93cb2a6163a 100644
--- a/src/drivers/pc80/tpm/tis.c
+++ b/src/drivers/pc80/tpm/tis.c
@@ -286,6 +286,14 @@ static inline tpm_result_t tis_wait_valid_data(int locality)
 static inline int tis_has_valid_data(int locality)
 {
 	const u8 has_data = TIS_STS_DATA_AVAILABLE | TIS_STS_VALID;
+
+	/*
+	 * Certain TPMs require a small delay here, as they have set
+	 * TIS_STS_VALID first and TIS_STS_DATA_AVAILABLE few clocks later.
+	 */
+	if ((tpm_read_status(locality) & has_data) == has_data)
+		return 1;
+
 	return (tpm_read_status(locality) & has_data) == has_data;
 }
 
@@ -635,14 +643,6 @@ static tpm_result_t tis_readresponse(u8 *buffer, size_t *len)
 		if (offset == expected_count)
 			break;	/* We got all we need */
 
-		/*
-		 * Certain TPMs seem to need some delay between tis_wait_valid()
-		 * and tis_has_valid_data(), or some race-condition-related
-		 * issue will occur.
-		 */
-		if (CONFIG(TPM_RDRESP_NEED_DELAY))
-			udelay(10);
-
 	} while (tis_has_valid_data(locality));
 
 	/* * Make sure we indeed read all there was. */

From 135a75826bb1315d641c9a8c0c383f1df7e0ae24 Mon Sep 17 00:00:00 2001
From: Bill XIE <persmule@hardenedlinux.org>
Date: Thu, 10 Oct 2024 09:01:24 +0800
Subject: [PATCH 03/14] drivers/pc80/tpm: Remove flag TPM_RDRESP_NEED_DELAY

After CB:76315, TPM_RDRESP_NEED_DELAY, whose historical mission has
ended, could be removed.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I51e046fb738d2ff7a23225739de62a1a7780bc1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
---
 src/mainboard/system76/addw1/Kconfig  | 1 -
 src/mainboard/system76/adl/Kconfig    | 1 -
 src/mainboard/system76/bonw14/Kconfig | 1 -
 src/mainboard/system76/cml-u/Kconfig  | 1 -
 src/mainboard/system76/gaze15/Kconfig | 1 -
 src/mainboard/system76/kbl-u/Kconfig  | 1 -
 src/mainboard/system76/mtl/Kconfig    | 1 -
 src/mainboard/system76/oryp5/Kconfig  | 1 -
 src/mainboard/system76/oryp6/Kconfig  | 1 -
 src/mainboard/system76/rpl/Kconfig    | 1 -
 src/mainboard/system76/tgl-h/Kconfig  | 1 -
 src/mainboard/system76/tgl-u/Kconfig  | 1 -
 src/mainboard/system76/whl-u/Kconfig  | 1 -
 src/security/tpm/Kconfig              | 9 ---------
 14 files changed, 22 deletions(-)

diff --git a/src/mainboard/system76/addw1/Kconfig b/src/mainboard/system76/addw1/Kconfig
index 46a63835619..089ca7aee0b 100644
--- a/src/mainboard/system76/addw1/Kconfig
+++ b/src/mainboard/system76/addw1/Kconfig
@@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_MEASURED_BOOT
-	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/addw1"
diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig
index 3d364f14828..56860a4bb27 100644
--- a/src/mainboard/system76/adl/Kconfig
+++ b/src/mainboard/system76/adl/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SYSTEM76_ADL_COMMON
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
-	select TPM_RDRESP_NEED_DELAY
 
 config BOARD_SYSTEM76_DARP8
 	select BOARD_SYSTEM76_ADL_COMMON
diff --git a/src/mainboard/system76/bonw14/Kconfig b/src/mainboard/system76/bonw14/Kconfig
index 8412dd12551..b12c514e3e8 100644
--- a/src/mainboard/system76/bonw14/Kconfig
+++ b/src/mainboard/system76/bonw14/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_MEASURED_BOOT
-	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/bonw14"
diff --git a/src/mainboard/system76/cml-u/Kconfig b/src/mainboard/system76/cml-u/Kconfig
index db2f1eac224..4bb47296756 100644
--- a/src/mainboard/system76/cml-u/Kconfig
+++ b/src/mainboard/system76/cml-u/Kconfig
@@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_MEASURED_BOOT
-	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/cml-u"
diff --git a/src/mainboard/system76/gaze15/Kconfig b/src/mainboard/system76/gaze15/Kconfig
index 981a8f9a1f9..09616c9170c 100644
--- a/src/mainboard/system76/gaze15/Kconfig
+++ b/src/mainboard/system76/gaze15/Kconfig
@@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_MEASURED_BOOT
-	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/gaze15"
diff --git a/src/mainboard/system76/kbl-u/Kconfig b/src/mainboard/system76/kbl-u/Kconfig
index 0fccdf738c9..c8410f295e9 100644
--- a/src/mainboard/system76/kbl-u/Kconfig
+++ b/src/mainboard/system76/kbl-u/Kconfig
@@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_MEASURED_BOOT
-	select TPM_RDRESP_NEED_DELAY
 
 config DISABLE_HECI1_AT_PRE_BOOT
 	default y
diff --git a/src/mainboard/system76/mtl/Kconfig b/src/mainboard/system76/mtl/Kconfig
index aef8ec38b15..6f1c23d2d25 100644
--- a/src/mainboard/system76/mtl/Kconfig
+++ b/src/mainboard/system76/mtl/Kconfig
@@ -23,7 +23,6 @@ config BOARD_SYSTEM76_MTL_COMMON
 	select SOC_INTEL_METEORLAKE
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
-	select TPM_RDRESP_NEED_DELAY
 
 config BOARD_SYSTEM76_DARP10
 	select BOARD_SYSTEM76_MTL_COMMON
diff --git a/src/mainboard/system76/oryp5/Kconfig b/src/mainboard/system76/oryp5/Kconfig
index 64c25c14248..91a36f387ba 100644
--- a/src/mainboard/system76/oryp5/Kconfig
+++ b/src/mainboard/system76/oryp5/Kconfig
@@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_MEASURED_BOOT
-	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/oryp5"
diff --git a/src/mainboard/system76/oryp6/Kconfig b/src/mainboard/system76/oryp6/Kconfig
index b9f25939603..b096821fdeb 100644
--- a/src/mainboard/system76/oryp6/Kconfig
+++ b/src/mainboard/system76/oryp6/Kconfig
@@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_MEASURED_BOOT
-	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/oryp6"
diff --git a/src/mainboard/system76/rpl/Kconfig b/src/mainboard/system76/rpl/Kconfig
index 20a09b60925..a61e4efab45 100644
--- a/src/mainboard/system76/rpl/Kconfig
+++ b/src/mainboard/system76/rpl/Kconfig
@@ -23,7 +23,6 @@ config BOARD_SYSTEM76_RPL_COMMON
 	select SOC_INTEL_RAPTORLAKE
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
-	select TPM_RDRESP_NEED_DELAY
 
 config BOARD_SYSTEM76_ADDW3
 	select BOARD_SYSTEM76_RPL_COMMON
diff --git a/src/mainboard/system76/tgl-h/Kconfig b/src/mainboard/system76/tgl-h/Kconfig
index 6ce452f7ba2..9f9ee1dd30f 100644
--- a/src/mainboard/system76/tgl-h/Kconfig
+++ b/src/mainboard/system76/tgl-h/Kconfig
@@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_MEASURED_BOOT
-	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/tgl-h"
diff --git a/src/mainboard/system76/tgl-u/Kconfig b/src/mainboard/system76/tgl-u/Kconfig
index 47602f5209f..4bce9a3f2d4 100644
--- a/src/mainboard/system76/tgl-u/Kconfig
+++ b/src/mainboard/system76/tgl-u/Kconfig
@@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_MEASURED_BOOT
-	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/tgl-u"
diff --git a/src/mainboard/system76/whl-u/Kconfig b/src/mainboard/system76/whl-u/Kconfig
index 08b4948db99..b8cb4fc33c5 100644
--- a/src/mainboard/system76/whl-u/Kconfig
+++ b/src/mainboard/system76/whl-u/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_MEASURED_BOOT
-	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/whl-u"
diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig
index ea13fa43c12..377d6dcb887 100644
--- a/src/security/tpm/Kconfig
+++ b/src/security/tpm/Kconfig
@@ -60,15 +60,6 @@ config DEBUG_TPM
 	help
 	  This option enables additional TPM related debug messages.
 
-config TPM_RDRESP_NEED_DELAY
-	bool "Enable Delay Workaround for TPM"
-	default n
-	depends on MEMORY_MAPPED_TPM
-	help
-	  Certain TPMs seem to need some delay when reading response
-	  to work around a race-condition-related issue, possibly
-	  caused by ill-programmed TPM firmware.
-
 config TPM_STARTUP_IGNORE_POSTINIT
 	bool
 	help

From aa13aeadc05142bd71eb7a6c6742b5a0c8cc9ee9 Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Fri, 9 Aug 2024 14:23:14 -0600
Subject: [PATCH 04/14] util/marvell/doimage_mv: Update CFLAGS to
 CFLAGS_doimage

Because we import the doimage_mv/Makefile.mk directly into the main
coreboot makefile, this was setting a global CFLAGS variable. That's not
a huge issue since coreboot doesn't use the global CFLAGS variable, but
it should be updated anyway.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iebe281ca891745c1f993df274ef75b1440059c85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 util/marvell/doimage_mv/Makefile.mk | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/util/marvell/doimage_mv/Makefile.mk b/util/marvell/doimage_mv/Makefile.mk
index 3f4f528abdf..6f3a401feac 100644
--- a/util/marvell/doimage_mv/Makefile.mk
+++ b/util/marvell/doimage_mv/Makefile.mk
@@ -3,13 +3,13 @@ TOP            = $(abspath ../../..)
 DOIMAGE_FOLDER = marvell/doimage_mv
 DOIMAGE_BINARY = doimage
 
-CFLAGS  = -g -O1 -I./../inc -DMV_CPU_LE -I $(TOP)/src/commonlib/bsd/include
+CFLAGS_doimage  = -g -O1 -I./../inc -DMV_CPU_LE -I $(TOP)/src/commonlib/bsd/include
 
 $(objutil)/$(DOIMAGE_FOLDER):
 	mkdir -p $@
 
 $(objutil)/$(DOIMAGE_FOLDER)/doimage.o: $(top)/util/marvell/doimage_mv/doimage.c $(objutil)/$(DOIMAGE_FOLDER)
-	$(HOSTCC) $(CFLAGS) -c $< -o $@
+	$(HOSTCC) $(CFLAGS_doimage) -c $< -o $@
 
 $(objutil)/$(DOIMAGE_FOLDER)/$(DOIMAGE_BINARY): $(objutil)/$(DOIMAGE_FOLDER)/doimage.o
-	$(HOSTCC) $(CFLAGS) -o $@ $^
+	$(HOSTCC) $(CFLAGS_doimage) -o $@ $^

From 85541960df2c34d0e7c621cc1cfb3c169439d9d0 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Sun, 3 Dec 2023 20:47:30 +0100
Subject: [PATCH 05/14] util/ifdtool/ifdtool.c: Add validation exception

When validating the FMAP against the IFD, the BIOS region is a somewhat
specical case, since the FMAP BIOS region usually does not match the IFD
BIOS region. Instead the FMAP region usually resides somewhere inside
the IFD BIOS region and the where depends on CONFIG_CBFS_SIZE.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I920a0ee246cfd2b4ae0870256357d4f285e1730d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 util/ifdtool/ifdtool.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 5993bfc99ba..36477eef66d 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -1227,6 +1227,19 @@ static void validate_layout(char *image, int size)
 		matches++; // found a match between FMAP and IFD region
 
 		if ((uint)region.base != area->offset || (uint)region.size != area->size) {
+			if (i == REGION_BIOS) {
+				/*
+				 * BIOS FMAP region is a special case
+				 * coreboots FMAP BIOS region depends on the CONFIG_CBFS_SIZE
+				 * while the IFD BIOS region is always of static size.
+				 * Therefore we just make sure that the BIOS region of the FMAP
+				 * is inside the region specified by the IFD
+				 */
+				if ((uint)region.base <= area->offset &&
+				   ((uint)region.base + region.size) >= (area->offset + area->size)) {
+					continue;
+				}
+			}
 			printf("Region mismatch between %s and %s\n", region_names[i].terse, area->name);
 			printf(" Descriptor region %s:\n", region_names[i].terse);
 			printf("  offset: 0x%08x\n", region.base);

From edf390dee50d52cb31f908b2e7959acf2fff54e2 Mon Sep 17 00:00:00 2001
From: Shuo Liu <shuo.liu@intel.com>
Date: Wed, 9 Oct 2024 04:59:07 +0800
Subject: [PATCH 06/14] Documentation/soc/intel/xeon_sp: Add targeted feature
 list

Add targeted feature list for Xeon 6 coreboot. The listed features
are targeted to be supported by Xeon 6 coreboot design, while some
specific items might need fixes and improvements per community
feedback.

Change-Id: Ibecd63dfca10712223ccdd943109ba28ed668200
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84701
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../intel/xeon_sp/community_preview_guide.md  | 84 +++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/Documentation/soc/intel/xeon_sp/community_preview_guide.md b/Documentation/soc/intel/xeon_sp/community_preview_guide.md
index 923a359c517..6a32b4fd8ba 100644
--- a/Documentation/soc/intel/xeon_sp/community_preview_guide.md
+++ b/Documentation/soc/intel/xeon_sp/community_preview_guide.md
@@ -19,6 +19,90 @@ The supported platform status are as below,
 
 - Buildable and bootable with real FSP headers/binaries
 
+## Targeted features list
+
+1. ACPI
+
+- RSDP/RSDT/XSDT/FADT/FACS/DSDT/SSDT
+
+- MCFG/MADT/SRAT/SLIT/HMAT/DMAR/CEDT
+
+- HEPT/SPMI/TPM2
+
+- HEST/EINJ/ERST/BERT
+
+2. SMBIOS
+
+- Type 0 - BIOS information
+
+- Type 1 - system information
+
+- Type 2 - base board information
+
+- Type 3 - chassis information
+
+- Type 4 - processor information
+
+- Type 17 - memory device
+
+3. Hardware related
+
+- Basic PCIe support
+
+  * IIO bifurcation
+
+  * PCIe hot plug
+
+  * VT-d
+
+- Customizable PCIe host bridge bus/MMIO resource window size for smart NIC support
+
+  * To handle the case where a large amount of PFs/VFs will be presented under specific PCIe host bridge
+
+- On-Chip accelerator (QAT, IAA, DSA, DLB)
+
+- CXL 2.0 Type-3 memory
+
+- NUMA and sub-NUMA clustering
+
+- GPIO (with physical pins)
+
+- Virtual GPIO
+
+  * eSPI based, use BMC or CPLD to expand GPIO pin counts on PCH-less SoC
+
+- BMC support
+
+  * IPMI KCS
+
+- Power Sequence
+
+  * ACPI S0/S5
+
+  * Fast cold/warm reset
+
+- CPU OSPM
+
+  * OS native (based on intel p_state/intel_idle OS driver)
+
+- RAS
+
+  * Based on FSP2.4 FSP-SMM
+
+  * APEI support
+
+  * Memory CE/UCE (firmware first mode, e.g. MCA/eMCA)
+
+  * IIO CE/UCE (firmware first mode, e.g. DPC/eDPC)
+
+4. Firmware related
+
+- Boot to various payloads (Linux payload/TianoCore/UniversalPayload)
+
+- Enlarged CBFS (>16MB) for one or multiple cloud payloads
+
+- VPD
+
 ## Build steps
 
 ### Prepare workspace

From 520c6cbfb9bd18d3af000350f5c871560c00d2fc Mon Sep 17 00:00:00 2001
From: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Thu, 10 Oct 2024 13:04:32 +0000
Subject: [PATCH 07/14] Doc/soc/amd/family17h: Fix URL to AGESA Interface
 Specification

The original URL now points to "AMD Documentation Hub" and not the
document.

Change-Id: Icc42943340132843df2387cc1203178a0774a387
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
 Documentation/soc/amd/family17h.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/soc/amd/family17h.md b/Documentation/soc/amd/family17h.md
index fffe25b0235..75d05a70dda 100644
--- a/Documentation/soc/amd/family17h.md
+++ b/Documentation/soc/amd/family17h.md
@@ -254,6 +254,6 @@ for AMD Family 17h Processors* (PID #55758) and *AMD Platform
 Security Processor BIOS Architecture Design Guide* (PID #54267) for
 earlier products
 2. [PSP Integration](psp_integration.md)
-3. [https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf](https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf)
+3. [AGESA Interface Specification for Arch2008](https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/44065_Arch2008.pdf)
 4. [https://en.wikichip.org/wiki/amd/cores/picasso](https://en.wikichip.org/wiki/amd/cores/picasso)
 5. [https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html](https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html)

From 7c57f9aec65506d59313bd6f09ca8c8a2e4edb4c Mon Sep 17 00:00:00 2001
From: Martin Roth <gaumless@gmail.com>
Date: Mon, 19 Feb 2024 17:39:18 -0700
Subject: [PATCH 08/14] Documentation: Update the code of conduct

This change reiterates that the coreboot leadership may revoke a user's
privileges. This does not change anything, as it already says "The
community organizers may take any action they deem appropriate, up to
and including a temporary ban or permanent expulsion from the community
without warning".

Also add a note that the discussions are private. If someone wants to
make the issue public, the coreboot leadership can't stop them, but the
board believes in handling these issues privately.

Finally, add a note that if there's an issue with someone on the
arbitration board, issues may be taken directly to the leadership board.

Change-Id: I5e2010a16f31f892bd1761b56b96ea773877dea0
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
 Documentation/community/code_of_conduct.md | 25 ++++++++++++++++++----
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/Documentation/community/code_of_conduct.md b/Documentation/community/code_of_conduct.md
index e1f512877ed..ffff110c161 100644
--- a/Documentation/community/code_of_conduct.md
+++ b/Documentation/community/code_of_conduct.md
@@ -86,8 +86,13 @@ organizers may take any action they deem appropriate, up to and including
 a temporary ban or permanent expulsion from the community without warning
 (and without refund in the case of a paid event).
 
-Community organizers can be members of the arbitration team, or organizers
-of events and online communities.
+As a part of running the project, coreboot leadership has the right to
+revoke privileges as they see fit. This is not done lightly. Over the
+history of the coreboot project, there have been only a handful of times
+where an action needed to be taken.
+
+Community organizers can be members of the arbitration team, the
+leadership board, or organizers of events and online communities.
 
 ## Addressing Grievances
 
@@ -95,6 +100,11 @@ If you feel you have been falsely or unfairly accused of violating this
 Code of Conduct, you should notify the arbitration team with a concise
 description of your grievance.
 
+Discussions about these actions are not done publicly, for obvious
+reasons. If someone believes that the circumstances that led to an
+action have changed, please send an email to all the members of the
+arbitration team and/or leadership board for discussion.
+
 ## Legal action
 
 Threatening or starting legal action against the project, sibling
@@ -115,11 +125,18 @@ communications pertaining to community business.
 
 ## Contact info
 
-Our arbitration team consists of the following people
-* Stefan Reinauer <stefan.reinauer@coreboot.org> (USA)
+Our arbitration team currently consists of the following people
+* Daniel Pono Takamori <pono@sfconservancy.org> (USA)
 * Ronald Minnich <rminnich@coreboot.org> (USA)
 * Martin Roth <martin@coreboot.org> (USA)
 
+If you have an issue with someone on the arbitration team, please reach
+out to the coreboot leadership board directly.
+
+The leadership board's information can be found on the
+[coreboot Leadership and Admin Boards](https://coreboot.org/leadership.html)
+page on the website.
+
 ## License and attribution
 
 This Code of Conduct is distributed under

From 55a5041fbfcda747db6b24c4c6a292ecb26cac50 Mon Sep 17 00:00:00 2001
From: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Date: Wed, 9 Oct 2024 12:54:41 +0800
Subject: [PATCH 09/14] mb/google/rex: Add SPDX license headers to template
 Makefile

According to CB:68982, add SPDX license headers to rex template
Makefile. Without this patch, build bot may report build failed.

BUG=none
TEST=Run create_coreboot_variant.sh and check Makefile

Change-Id: I7d100a2303be063590f1389a7eed8f9a52071241
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 util/mainboard/google/rex0/template/Makefile.mk | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/util/mainboard/google/rex0/template/Makefile.mk b/util/mainboard/google/rex0/template/Makefile.mk
index 6c293464704..a49954cc351 100644
--- a/util/mainboard/google/rex0/template/Makefile.mk
+++ b/util/mainboard/google/rex0/template/Makefile.mk
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 bootblock-y += gpio.c
 
 romstage-y += gpio.c

From bede28b17df3aa3af4adc9c2396abd4070785cda Mon Sep 17 00:00:00 2001
From: Elyes Haouas <ehaouas@noos.fr>
Date: Sat, 10 Aug 2024 09:52:57 +0200
Subject: [PATCH 10/14] i945: Use nullptr instead of NULL

nullptr was introduced in C11 spec and gcc 4.7.

    https://en.cppreference.com/w/cpp/language/nullptr
    https://stackoverflow.com/questions/16256586/how-to-enable-c11-on-later-versions-of-gcc

coreboot switched to GCC 4.7.2 on October 25, 2021, prior to coreboot v4.1.

    https://review.coreboot.org/c/coreboot/+/1609

GCC-13 implemented nullptr constant: https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3042.htm
So use it insted of NULL macro.

Change-Id: I7d47e692a33d739345a81f589d4329a31beeb8c5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83860
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/apple/macbook21/mptable.c    | 2 +-
 src/mainboard/getac/p470/mptable.c         | 2 +-
 src/mainboard/ibase/mb899/mptable.c        | 4 ++--
 src/mainboard/intel/d945gclf/mptable.c     | 2 +-
 src/mainboard/kontron/986lcd-m/mainboard.c | 2 +-
 src/mainboard/kontron/986lcd-m/mptable.c   | 4 ++--
 src/mainboard/lenovo/t60/mptable.c         | 2 +-
 src/mainboard/lenovo/x60/mptable.c         | 2 +-
 src/mainboard/roda/rk886ex/mptable.c       | 2 +-
 src/northbridge/intel/i945/northbridge.c   | 4 ++--
 src/northbridge/intel/i945/raminit.c       | 2 +-
 src/southbridge/intel/i82801gx/ide.c       | 2 +-
 src/southbridge/intel/i82801gx/pcie.c      | 6 +++---
 src/southbridge/intel/i82801gx/sata.c      | 4 ++--
 14 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c
index fcf46a26e45..38916d3563e 100644
--- a/src/mainboard/apple/macbook21/mptable.c
+++ b/src/mainboard/apple/macbook21/mptable.c
@@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v)
 
 	smp_write_processors(mc);
 
-	mptable_write_buses(mc, NULL, &isa_bus);
+	mptable_write_buses(mc, nullptr, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c
index d7a4af65c3e..6743bda4956 100644
--- a/src/mainboard/getac/p470/mptable.c
+++ b/src/mainboard/getac/p470/mptable.c
@@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v)
 
 	smp_write_processors(mc);
 
-	mptable_write_buses(mc, NULL, &isa_bus);
+	mptable_write_buses(mc, nullptr, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c
index bb4379685ef..e34c7237ac9 100644
--- a/src/mainboard/ibase/mb899/mptable.c
+++ b/src/mainboard/ibase/mb899/mptable.c
@@ -8,7 +8,7 @@
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
-	struct device *riser = NULL, *firewire = NULL;
+	struct device *riser = nullptr, *firewire = nullptr;
 	int firewire_bus = 0, riser_bus = 0, isa_bus;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v)
 		printk(BIOS_SPEW, "Riser bus is %x\n", riser_bus);
 	}
 
-	mptable_write_buses(mc, NULL, &isa_bus);
+	mptable_write_buses(mc, nullptr, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c
index 7ab47b4b376..6c9d12b3224 100644
--- a/src/mainboard/intel/d945gclf/mptable.c
+++ b/src/mainboard/intel/d945gclf/mptable.c
@@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v)
 
 	smp_write_processors(mc);
 
-	mptable_write_buses(mc, NULL, &isa_bus);
+	mptable_write_buses(mc, nullptr, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c
index bd50fc33ca4..56c9ffae2b5 100644
--- a/src/mainboard/kontron/986lcd-m/mainboard.c
+++ b/src/mainboard/kontron/986lcd-m/mainboard.c
@@ -141,7 +141,7 @@ static void mainboard_init(void *chip_info)
 			continue;
 		printk(BIOS_DEBUG, "Disabling Ethernet NIC #%d\n", i);
 		dev = pcidev_on_root(28, i - 1);
-		if (dev == NULL) {
+		if (dev == nullptr) {
 			printk(BIOS_ERR,
 			       "Disabling Ethernet NIC: Cannot find 00:1c.%d!\n",
 			       i - 1);
diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c
index 5ee3288e778..b112ac0ff83 100644
--- a/src/mainboard/kontron/986lcd-m/mptable.c
+++ b/src/mainboard/kontron/986lcd-m/mptable.c
@@ -7,7 +7,7 @@
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
-	struct device *riser = NULL, *firewire = NULL;
+	struct device *riser = nullptr, *firewire = nullptr;
 	int firewire_bus = 0, riser_bus = 0, isa_bus;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -30,7 +30,7 @@ static void *smp_write_config_table(void *v)
 		riser_bus = riser->downstream->secondary;
 	}
 
-	mptable_write_buses(mc, NULL, &isa_bus);
+	mptable_write_buses(mc, nullptr, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c
index f6400858243..aa83105843d 100644
--- a/src/mainboard/lenovo/t60/mptable.c
+++ b/src/mainboard/lenovo/t60/mptable.c
@@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v)
 
 	smp_write_processors(mc);
 
-	mptable_write_buses(mc, NULL, &isa_bus);
+	mptable_write_buses(mc, nullptr, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c
index 73e9c1b8d42..12e88a4a9d2 100644
--- a/src/mainboard/lenovo/x60/mptable.c
+++ b/src/mainboard/lenovo/x60/mptable.c
@@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v)
 
 	smp_write_processors(mc);
 
-	mptable_write_buses(mc, NULL, &isa_bus);
+	mptable_write_buses(mc, nullptr, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c
index 3ce1cbc80bb..a9bfe26cd23 100644
--- a/src/mainboard/roda/rk886ex/mptable.c
+++ b/src/mainboard/roda/rk886ex/mptable.c
@@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v)
 
 	smp_write_processors(mc);
 
-	mptable_write_buses(mc, NULL, &isa_bus);
+	mptable_write_buses(mc, nullptr, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 82f3843d4fb..a268c5b15a0 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -74,14 +74,14 @@ static const char *northbridge_acpi_name(const struct device *dev)
 		return "PCI0";
 
 	if (!is_pci_dev_on_bus(dev, 0))
-		return NULL;
+		return nullptr;
 
 	switch (dev->path.pci.devfn) {
 	case PCI_DEVFN(0, 0):
 		return "MCHC";
 	}
 
-	return NULL;
+	return nullptr;
 }
 
 void northbridge_write_smram(u8 smram)
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index a37754b7f3e..b664fbee08e 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -1142,7 +1142,7 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
 	int i;
 	size_t cum0, cum1, tolud, tom, pci_mmio_size;
 	const struct device *dev;
-	const struct northbridge_intel_i945_config *cfg = NULL;
+	const struct northbridge_intel_i945_config *cfg = nullptr;
 
 	printk(BIOS_DEBUG, "Setting RAM size...\n");
 
diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c
index 71fc738632f..05f1e0a04fb 100644
--- a/src/southbridge/intel/i82801gx/ide.c
+++ b/src/southbridge/intel/i82801gx/ide.c
@@ -18,7 +18,7 @@ static void ide_init(struct device *dev)
 	const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
 
 	printk(BIOS_DEBUG, "i82801gx_ide: initializing...");
-	if (config == NULL) {
+	if (config == nullptr) {
 		printk(BIOS_ERR, "\ni82801gx_ide: Not mentioned in devicetree.cb!\n");
 		// Trying to set somewhat safe defaults instead of bailing out.
 		enable_primary = enable_secondary = 1;
diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index befbf3beb72..f4b3dbd4bb7 100644
--- a/src/southbridge/intel/i82801gx/pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
@@ -138,7 +138,7 @@ static void root_port_commit_config(struct device *dev)
 	int i;
 	bool coalesce = false;
 
-	if (dev->chip_info != NULL) {
+	if (dev->chip_info != nullptr) {
 		const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
 		coalesce = config->pcie_port_coalesce;
 	}
@@ -151,8 +151,8 @@ static void root_port_commit_config(struct device *dev)
 
 		pcie_dev = rpc.ports[i];
 
-		if (pcie_dev == NULL) {
-			printk(BIOS_ERR, "Root Port %d device is NULL?\n", i + 1);
+		if (pcie_dev == nullptr) {
+			printk(BIOS_ERR, "Root Port %d device is nullptr?\n", i + 1);
 			continue;
 		}
 
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index 31aeaf60be5..fbbea7c8973 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -76,7 +76,7 @@ static void sata_init(struct device *dev)
 
 	printk(BIOS_DEBUG, "i82801gx_sata: initializing...\n");
 
-	if (config == NULL) {
+	if (config == nullptr) {
 		printk(BIOS_ERR, "i82801gx_sata: error: device not in devicetree.cb!\n");
 		return;
 	}
@@ -130,7 +130,7 @@ static void sata_init(struct device *dev)
 		pci_write_config8(dev, INTR_LN, 0x0a);
 
 		struct resource *ahci_res = probe_resource(dev, PCI_BASE_ADDRESS_5);
-		if (ahci_res != NULL)
+		if (ahci_res != nullptr)
 			/* write AHCI GHC_PI register */
 			write32(res2mmio(ahci_res, 0xc, 0), config->sata_ports_implemented);
 		break;

From 229d8fa2868a36ded96910df3291de36bfc096f3 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 29 Aug 2024 20:29:44 +0100
Subject: [PATCH 11/14] drivers/usb/acpi: Add AOLD Method for Intel Bluetooth

Add AOLD Method, which returns an integer based on
whether Audio Offload is enabled. Leave the existing
control of Audio Offload in `soc/soc_chip.h`. Add
`cnvi_bt_audio_offload` in the USB ACPI `chip.h` to
control the aforementioned return value.

The value in `soc/soc_chip.h` and `chip.h` should
match.

Change-Id: Idb804fb1cf0edef4a98479a6261ca68255dbf075
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84134
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/drivers/usb/acpi/chip.h            |  3 ++-
 src/drivers/usb/acpi/intel_bluetooth.c | 30 +++++++++++++++++++++++++-
 src/drivers/usb/acpi/usb_acpi.c        |  2 +-
 3 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h
index 5e41d24f50d..afd99715b9b 100644
--- a/src/drivers/usb/acpi/chip.h
+++ b/src/drivers/usb/acpi/chip.h
@@ -49,6 +49,7 @@ struct drivers_usb_acpi_config {
 
 	/* Intel Bluetooth */
 	bool is_intel_bluetooth;
+	bool cnvi_bt_audio_offload;
 
 	/* GPIO used to take device out of reset or to put it into reset. */
 	struct acpi_gpio reset_gpio;
@@ -87,7 +88,7 @@ struct drivers_usb_acpi_config {
 bool usb_acpi_get_pld(const struct device *usb_device, struct acpi_pld *pld);
 
 /* Intel Bluetooth */
-void acpi_device_intel_bt(unsigned int reset_gpio);
+void acpi_device_intel_bt(unsigned int reset_gpio, bool audio_offload);
 void acpi_device_intel_bt_common(void);
 
 #endif /* __USB_ACPI_CHIP_H__ */
diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index 773f1ad7430..1775286be4d 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -53,7 +53,7 @@ static void get_feature_flag(void *arg)
 void (*uuid_callbacks1[])(void *) = { check_reset_delay, set_reset_delay };
 void (*uuid_callbacks2[])(void *) = { get_feature_flag };
 
-void acpi_device_intel_bt(unsigned int reset_gpio)
+void acpi_device_intel_bt(unsigned int reset_gpio, bool audio_offload)
 {
 /*
  *	Name (RDLY, 0x69)
@@ -231,6 +231,34 @@ void acpi_device_intel_bt(unsigned int reset_gpio)
 		acpigen_emit_namestring("BTRT");
 	}
 	acpigen_pop_len();
+
+/*
+ *	Method (AOLD, 0, Serialized)
+ *	{
+ *		Name (AODS, Package (0x03)
+ *		{
+ *			Zero,
+ *			0x12,
+ *			Zero	// Audio Offload - 0: Disabled
+ *						   1: Enabled
+ *		})
+ *		Return (AODS)
+ *	}
+ */
+	acpigen_write_method_serialized("AOLD", 0);
+	{
+		acpigen_write_name("AODS");
+		acpigen_write_package(3);
+		{
+			acpigen_write_integer(0);
+			acpigen_write_integer(0x12);
+			acpigen_write_integer(audio_offload);
+		}
+		acpigen_pop_len();
+
+		acpigen_write_return_namestr("AODS");
+	}
+	acpigen_pop_len();
 }
 
 void acpi_device_intel_bt_common(void)
diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c
index f1622921c90..0087cbed542 100644
--- a/src/drivers/usb/acpi/usb_acpi.c
+++ b/src/drivers/usb/acpi/usb_acpi.c
@@ -108,7 +108,7 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev)
 	}
 
 	if (config->is_intel_bluetooth)
-		acpi_device_intel_bt(config->reset_gpio.pins[0]);
+		acpi_device_intel_bt(config->reset_gpio.pins[0], config->cnvi_bt_audio_offload);
 
 	acpigen_pop_len();
 

From d842e94d35de386cd27fcb3bfca9dd05767c2c77 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 9 Oct 2024 20:38:27 +0100
Subject: [PATCH 12/14] soc/intel/*: Add debug prints for misaligned FSP and
 driver settings

Print a warning when the FSP UPD for CNVi Audio Offload is enabled
without the corresponding USB ACPI driver being enabled.

Throw an error when the USB ACPI driver is enabled without the
corresponding UPD being enabled.

Change-Id: I449c43998dd379dc68a33db47a2fe51cfe5cda2f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
---
 src/soc/intel/alderlake/fsp_params.c  | 25 +++++++++++++++++++++++++
 src/soc/intel/cannonlake/fsp_params.c | 25 +++++++++++++++++++++++++
 src/soc/intel/meteorlake/fsp_params.c | 25 +++++++++++++++++++++++++
 src/soc/intel/tigerlake/fsp_params.c  | 26 ++++++++++++++++++++++++++
 4 files changed, 101 insertions(+)

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 79fa893c729..41d048b68f5 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -11,6 +11,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <drivers/intel/gma/i915_reg.h>
+#include <drivers/usb/acpi/chip.h>
 #include <fsp/api.h>
 #include <fsp/fsp_debug_event.h>
 #include <fsp/fsp_gop_blt.h>
@@ -895,6 +896,23 @@ static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg,
 static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg,
 		const struct soc_intel_alderlake_config *config)
 {
+	struct device *port = NULL;
+	struct drivers_usb_acpi_config *usb_cfg;
+	bool usb_audio_offload = false;
+
+	/* Search through the devicetree for matching USB devices */
+	while ((port = dev_find_path(port, DEVICE_PATH_USB)) != NULL) {
+		/* Skip ports that are not enabled or not of USB type */
+		if (!port->enabled || port->path.type != DEVICE_PATH_USB)
+			continue;
+
+		usb_cfg = port->chip_info;
+		if (usb_cfg && usb_cfg->cnvi_bt_audio_offload) {
+			usb_audio_offload = true;
+			break;
+		}
+	}
+
 	/* CNVi */
 	s_cfg->CnviWifiCore = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI);
 	s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI);
@@ -910,6 +928,13 @@ static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg,
 		s_cfg->CnviBtCore = 0;
 		s_cfg->CnviBtAudioOffload = 0;
 	}
+	if (s_cfg->CnviBtAudioOffload && !usb_audio_offload) {
+		printk(BIOS_WARNING, "CNVi BT Audio offload enabled but not in USB driver.\n");
+	}
+	if (!s_cfg->CnviBtAudioOffload && usb_audio_offload) {
+		printk(BIOS_ERR, "USB BT Audio offload enabled but CNVi BT offload disabled\n");
+		usb_cfg->cnvi_bt_audio_offload = 0;
+	}
 }
 
 static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg,
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index bce1eeb3696..bd3d1495fe8 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -4,6 +4,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <drivers/usb/acpi/chip.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
 #include <option.h>
@@ -529,6 +530,23 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	/* Enable CNVi Wifi if enabled in device tree */
 #if CONFIG(SOC_INTEL_COMETLAKE)
+	struct device *port = NULL;
+	struct drivers_usb_acpi_config *usb_cfg;
+	bool usb_audio_offload = false;
+
+	/* Search through the devicetree for matching USB devices */
+	while ((port = dev_find_path(port, DEVICE_PATH_USB)) != NULL) {
+		/* Skip ports that are not enabled or not of USB type */
+		if (!port->enabled || port->path.type != DEVICE_PATH_USB)
+			continue;
+
+		usb_cfg = port->chip_info;
+		if (usb_cfg && usb_cfg->cnvi_bt_audio_offload) {
+			usb_audio_offload = true;
+			break;
+		}
+	}
+
 	/* CNVi */
 	s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNViWIFI);
 	s_cfg->CnviBtCore = config->CnviBtCore;
@@ -543,6 +561,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		s_cfg->CnviBtCore = 0;
 		s_cfg->CnviBtAudioOffload = 0;
 	}
+	if (s_cfg->CnviBtAudioOffload && !usb_audio_offload) {
+		printk(BIOS_WARNING, "CNVi BT Audio offload enabled but not in USB driver.\n");
+	}
+	if (!s_cfg->CnviBtAudioOffload && usb_audio_offload) {
+		printk(BIOS_ERR, "USB BT Audio offload enabled but CNVi BT offload disabled\n");
+		usb_cfg->cnvi_bt_audio_offload = 0;
+	}
 #else
 	s_cfg->PchCnviMode = is_devfn_enabled(PCH_DEVFN_CNViWIFI);
 #endif
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index 702820a7881..c2770e630c7 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -9,6 +9,7 @@
 #include <cpu/intel/microcode.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <drivers/usb/acpi/chip.h>
 #include <fsp/api.h>
 #include <fsp/fsp_debug_event.h>
 #include <fsp/fsp_gop_blt.h>
@@ -576,6 +577,23 @@ static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg,
 static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg,
 		const struct soc_intel_meteorlake_config *config)
 {
+	struct device *port = NULL;
+	struct drivers_usb_acpi_config *usb_cfg;
+	bool usb_audio_offload = false;
+
+	/* Search through the devicetree for matching USB devices */
+	while ((port = dev_find_path(port, DEVICE_PATH_USB)) != NULL) {
+		/* Skip ports that are not enabled or not of USB type */
+		if (!port->enabled || port->path.type != DEVICE_PATH_USB)
+			continue;
+
+		usb_cfg = port->chip_info;
+		if (usb_cfg && usb_cfg->cnvi_bt_audio_offload) {
+			usb_audio_offload = true;
+			break;
+		}
+	}
+
 	/* CNVi */
 	s_cfg->CnviMode = is_devfn_enabled(PCI_DEVFN_CNVI_WIFI);
 	s_cfg->CnviWifiCore = config->cnvi_wifi_core;
@@ -594,6 +612,13 @@ static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg,
 		s_cfg->CnviBtCore = 0;
 		s_cfg->CnviBtAudioOffload = 0;
 	}
+	if (s_cfg->CnviBtAudioOffload && !usb_audio_offload) {
+		printk(BIOS_WARNING, "CNVi BT Audio offload enabled but not in USB driver\n");
+	}
+	if (!s_cfg->CnviBtAudioOffload && usb_audio_offload) {
+		printk(BIOS_ERR, "USB BT Audio offload enabled but CNVi BT offload disabled\n");
+		usb_cfg->cnvi_bt_audio_offload = 0;
+	}
 }
 
 static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg,
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index fa5a549e7e6..9706ac6d629 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -7,6 +7,7 @@
 #include <device/pci_ops.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <drivers/usb/acpi/chip.h>
 #include <fsp/api.h>
 #include <fsp/ppi/mp_service_ppi.h>
 #include <fsp/util.h>
@@ -493,6 +494,24 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE);
 
 	/* CNVi */
+	struct device *port = NULL;
+	struct drivers_usb_acpi_config *usb_cfg;
+	bool usb_audio_offload = false;
+
+	/* Search through the devicetree for matching USB devices */
+	while ((port = dev_find_path(port, DEVICE_PATH_USB)) != NULL) {
+		/* Skip ports that are not enabled or not of USB type */
+		if (!port->enabled || port->path.type != DEVICE_PATH_USB)
+			continue;
+
+		usb_cfg = port->chip_info;
+		if (usb_cfg && usb_cfg->cnvi_bt_audio_offload) {
+			usb_audio_offload = true;
+			break;
+		}
+
+	}
+
 	params->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI);
 	params->CnviBtCore = config->CnviBtCore;
 	params->CnviBtAudioOffload = config->CnviBtAudioOffload;
@@ -506,6 +525,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->CnviBtCore = 0;
 		params->CnviBtAudioOffload = 0;
 	}
+	if (params->CnviBtAudioOffload && !usb_audio_offload) {
+		printk(BIOS_WARNING, "CNVi BT Audio offload enabled but not in USB driver.\n");
+	}
+	if (!params->CnviBtAudioOffload && usb_audio_offload) {
+		printk(BIOS_ERR, "USB BT Audio offload enabled but CNVi BT offload disabled\n");
+		usb_cfg->cnvi_bt_audio_offload = 0;
+	}
 
 	/* VMD */
 	params->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD);

From 144baae28c84ffb821a9bb69faf012a483f972db Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Oct 2024 13:41:11 +0100
Subject: [PATCH 13/14] drivers/usb/acpi: Add support for RTD3 for Intel
 Bluetooth

Add support for RTD3 for Intel Bluetooth. This is done by
controlling the enable GPIO (GPP_VGPIO_0 for most SOCs) that
exists on all wireless cards since Jefferson Peak.

The exception is GalePeak2, which uses VSEC and this driver doesn't
support that.

Change-Id: Ibea97ab0ae0a9f1eb6aaca43d831bb4ce7bdc02e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
---
 src/drivers/usb/acpi/chip.h            |   6 +-
 src/drivers/usb/acpi/intel_bluetooth.c | 108 +++++++++++++++++++++++--
 src/drivers/usb/acpi/usb_acpi.c        |   6 +-
 3 files changed, 110 insertions(+), 10 deletions(-)

diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h
index afd99715b9b..a27ce4468c1 100644
--- a/src/drivers/usb/acpi/chip.h
+++ b/src/drivers/usb/acpi/chip.h
@@ -88,7 +88,9 @@ struct drivers_usb_acpi_config {
 bool usb_acpi_get_pld(const struct device *usb_device, struct acpi_pld *pld);
 
 /* Intel Bluetooth */
-void acpi_device_intel_bt(unsigned int reset_gpio, bool audio_offload);
-void acpi_device_intel_bt_common(void);
+void acpi_device_intel_bt(unsigned int reset_gpio,
+			  unsigned int enable_gpio,
+			  bool audio_offload);
+void acpi_device_intel_bt_common(unsigned int enable_gpio);
 
 #endif /* __USB_ACPI_CHIP_H__ */
diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index 1775286be4d..49b2138ba74 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -13,10 +13,15 @@
  * BIT(1)	Check Tile Activation
  *
  * Check/Set Reset Delay (aa10f4e0-81ac-4233-abf6-3b2ac50e28d9)
- * Arg2 == 0: Return a package with the following bit set
+ * Arg2 == 0:	Return a package with the following bit set
  * BIT(0)	Indicates whether the device supports other functions
  * BIT(1)	Check Bluetooth reset timing
- * Arg2 == 1: Set the reset delay based on Arg3
+ *
+ * Arg2 == 1:	Set the reset delay based on Arg3
+ *
+ * Arg2 == 3:	Set the reset method based on Arg3 (Not supported by this driver)
+ * WDISABLE2 (BT_RF_KILL_N)
+ * VSEC (PCI Config Space)
  */
 
 static void check_reset_delay(void *arg)
@@ -53,7 +58,7 @@ static void get_feature_flag(void *arg)
 void (*uuid_callbacks1[])(void *) = { check_reset_delay, set_reset_delay };
 void (*uuid_callbacks2[])(void *) = { get_feature_flag };
 
-void acpi_device_intel_bt(unsigned int reset_gpio, bool audio_offload)
+void acpi_device_intel_bt(unsigned int reset_gpio, unsigned int enable_gpio, bool audio_offload)
 {
 /*
  *	Name (RDLY, 0x69)
@@ -129,13 +134,15 @@ void acpi_device_intel_bt(unsigned int reset_gpio, bool audio_offload)
  *	{
  *		Method (_STA, 0, NotSerialized)
  *		{
- *			Return (One)
+ *			Return (\_SB.PCI0.GBTE())
  *		}
  *		Method (_ON, 0, NotSerialized)
  *		{
+ *			\_SB.PCI0.SBTE(1)
  *		}
  *		Method (_OFF, 0, NotSerialized)
  *		{
+ *			\_SB.PCI0.SBTE(0)
  *		}
  *		Method (_RST, 0, NotSerialized)
  *		{
@@ -155,14 +162,34 @@ void acpi_device_intel_bt(unsigned int reset_gpio, bool audio_offload)
 	{
 		acpigen_write_method("_STA", 0);
 		{
-			acpigen_write_return_integer(1);
+			if (enable_gpio) {
+				acpigen_write_store();
+				acpigen_emit_namestring("\\_SB.PCI0.GBTE");
+				acpigen_emit_byte(LOCAL0_OP);
+
+				acpigen_write_return_op(LOCAL0_OP);
+			} else {
+				acpigen_write_return_integer(1);
+			}
 		}
 		acpigen_pop_len();
 
 		acpigen_write_method("_ON", 0);
+		{
+			if (enable_gpio) {
+				acpigen_emit_namestring("\\_SB.PCI0.SBTE");
+				acpigen_emit_byte(1);
+			}
+		}
 		acpigen_pop_len();
 
 		acpigen_write_method("_OFF", 0);
+		{
+			if (enable_gpio) {
+				acpigen_emit_namestring("\\_SB.PCI0.SBTE");
+				acpigen_emit_byte(0);
+			}
+		}
 		acpigen_pop_len();
 
 		acpigen_write_method("_RST", 0);
@@ -232,6 +259,32 @@ void acpi_device_intel_bt(unsigned int reset_gpio, bool audio_offload)
 	}
 	acpigen_pop_len();
 
+/*
+ *	Name (_PR0, Package (0x01)
+ *	{
+ *		BTRT
+ *	})
+ */
+	acpigen_write_name("_PR0");
+	{
+		acpigen_write_package(1);
+		acpigen_emit_namestring("BTRT");
+	}
+	acpigen_pop_len();
+
+/*
+ *	Name (_PR3, Package (0x01)
+ *	{
+ *		BTRT
+ *	})
+ */
+	acpigen_write_name("_PR3");
+	{
+		acpigen_write_package(1);
+		acpigen_emit_namestring("BTRT");
+	}
+	acpigen_pop_len();
+
 /*
  *	Method (AOLD, 0, Serialized)
  *	{
@@ -261,7 +314,7 @@ void acpi_device_intel_bt(unsigned int reset_gpio, bool audio_offload)
 	acpigen_pop_len();
 }
 
-void acpi_device_intel_bt_common(void)
+void acpi_device_intel_bt_common(unsigned int enable_gpio)
 {
 	acpigen_write_scope("\\_SB.PCI0");
 /*
@@ -269,5 +322,48 @@ void acpi_device_intel_bt_common(void)
  */
 	acpigen_write_mutex("CNMT", 0);
 
+/*
+ *	Method (SBTE, 1, Serialized)
+ *	{
+ *		If (Arg0 == 1)
+ *		{
+ *			STXS(enable_gpio)
+ *		} Else {
+ *			CTXS(enable_gpio)
+ *		}
+ *	}
+ */
+	acpigen_write_method_serialized("SBTE", 1);
+	{
+		if (enable_gpio) {
+			acpigen_write_if_lequal_op_int(ARG0_OP, 1);
+			{
+				acpigen_soc_set_tx_gpio(enable_gpio);
+			}
+			acpigen_write_else();
+			{
+				acpigen_soc_clear_tx_gpio(enable_gpio);
+			}
+			acpigen_pop_len();
+		}
+	}
+	acpigen_pop_len();
+
+/*
+ *	Method (GBTE, 0, NotSerialized)
+ *	{
+ *		Return (GTXS (enable_gpio))
+ *	}
+ */
+	acpigen_write_method("GBTE", 0);
+	{
+		acpigen_emit_byte(RETURN_OP);
+		if (enable_gpio)
+			acpigen_soc_get_tx_gpio(enable_gpio);
+		else
+			acpigen_emit_byte(0);
+	}
+	acpigen_pop_len();
+
 	acpigen_pop_len();
 }
diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c
index 0087cbed542..8960e3d05b1 100644
--- a/src/drivers/usb/acpi/usb_acpi.c
+++ b/src/drivers/usb/acpi/usb_acpi.c
@@ -108,7 +108,9 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev)
 	}
 
 	if (config->is_intel_bluetooth)
-		acpi_device_intel_bt(config->reset_gpio.pins[0], config->cnvi_bt_audio_offload);
+		acpi_device_intel_bt(config->reset_gpio.pins[0],
+				     config->enable_gpio.pins[0],
+				     config->cnvi_bt_audio_offload);
 
 	acpigen_pop_len();
 
@@ -117,7 +119,7 @@ static void usb_acpi_fill_ssdt_generator(const struct device *dev)
 	 * other code to access it i.e. CNVi driver.
 	 */
 	if (config->is_intel_bluetooth)
-		acpi_device_intel_bt_common();
+		acpi_device_intel_bt_common(config->enable_gpio.pins[0]);
 
 	printk(BIOS_INFO, "%s: %s at %s\n", path,
 	       config->desc ? : dev->chip_ops->name, dev_path(dev));

From 2cd06b79b1f9a76b675af3bc2aeb1f559d484bcc Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 2 Oct 2024 12:43:06 +0100
Subject: [PATCH 14/14] drivers/usb/acpi: Remove Tile Activation Method in
 Intel Bluetooth driver

Linux has never supported this feature, and according to our FAE, the
Windows driver dropped support for it in 2022 so remove it.

Change-Id: I4f0b6108bb5db657490a8b9395bb99378fc63c4d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
---
 src/drivers/usb/acpi/intel_bluetooth.c | 42 --------------------------
 1 file changed, 42 deletions(-)

diff --git a/src/drivers/usb/acpi/intel_bluetooth.c b/src/drivers/usb/acpi/intel_bluetooth.c
index 49b2138ba74..2cd06b22d91 100644
--- a/src/drivers/usb/acpi/intel_bluetooth.c
+++ b/src/drivers/usb/acpi/intel_bluetooth.c
@@ -6,12 +6,6 @@
 /*
  * Intel Bluetooth DSM
  *
- * Check Tile Activation (2d19d3e1-5708-4696-bd5b-2c3dbae2d6a9)
- *
- * Arg2 == 0: Return a package with the following bits set
- * BIT(0)	Indicates whether the device supports other functions
- * BIT(1)	Check Tile Activation
- *
  * Check/Set Reset Delay (aa10f4e0-81ac-4233-abf6-3b2ac50e28d9)
  * Arg2 == 0:	Return a package with the following bit set
  * BIT(0)	Indicates whether the device supports other functions
@@ -42,21 +36,7 @@ static void set_reset_delay(void *arg)
 	acpigen_write_store_op_to_namestr(ARG3_OP, "RDLY");
 }
 
-static void get_feature_flag(void *arg)
-{
-	acpigen_write_if_lequal_op_int(ARG1_OP, 0);
-	{
-		acpigen_write_return_singleton_buffer(0x03);
-	}
-	acpigen_write_else();
-	{
-		acpigen_write_return_singleton_buffer(0x00);
-	}
-	acpigen_pop_len();
-}
-
 void (*uuid_callbacks1[])(void *) = { check_reset_delay, set_reset_delay };
-void (*uuid_callbacks2[])(void *) = { get_feature_flag };
 
 void acpi_device_intel_bt(unsigned int reset_gpio, unsigned int enable_gpio, bool audio_offload)
 {
@@ -93,27 +73,6 @@ void acpi_device_intel_bt(unsigned int reset_gpio, unsigned int enable_gpio, boo
  *			}
  *			Return (Zero)
  *		}
- *		ElseIf ((Arg0 == ToUUID ("2d19d3e1-5708-4696-bd5b-2c3dbae2d6a9")))
- *		{
- *			If ((Arg2 == Zero))
- *			{
- *				If ((Arg1 == Zero))
- *				{
- *					Return (Buffer (One)
- *					{
- *						0x00
- *					})
- *				}
- *				Else
- *				{
- *					Return (Buffer (One)
- *					{
- *						0x00
- *					})
- *				}
- *			}
- *			Return (Zero)
- *		}
  *		Else
  *		{
  *			Return (Buffer (One)
@@ -125,7 +84,6 @@ void acpi_device_intel_bt(unsigned int reset_gpio, unsigned int enable_gpio, boo
  */
 	struct dsm_uuid uuid_callbacks[] = {
 		DSM_UUID("aa10f4e0-81ac-4233-abf6-3b2ac50e28d9", uuid_callbacks1, 2, NULL),
-		DSM_UUID("2d19d3e1-5708-4696-bd5b-2c3dbae2d6a9", uuid_callbacks2, 1, NULL),
 	};
 
 	acpigen_write_dsm_uuid_arr(uuid_callbacks, ARRAY_SIZE(uuid_callbacks));