From a03e5456e68d8937f4c43ec112c1495ae26a6356 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Mon, 30 Sep 2024 14:45:48 +0800 Subject: [PATCH 01/15] libpayload/endian: Add read32p/write32p macros and friends Add {read,write}{8,16,32,64}p macros and similar macros for clrsetbits, setbits and clrbits. Change-Id: If01e38663ffc1c08c553850d3210604c9b240655 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/84592 Tested-by: build bot (Jenkins) Reviewed-by: Yidi Lin --- payloads/libpayload/include/endian.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index 35fe0fd283a..fd59af1b5c4 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -193,6 +193,16 @@ static inline void le64enc(void *pp, uint32_t u) #define letohl(in) le32toh(in) #define letohll(in) le64toh(in) +/* read/write with uintptr_t address */ +#define read8p(addr) read8((void *)((uintptr_t)(addr))) +#define read16p(addr) read16((void *)((uintptr_t)(addr))) +#define read32p(addr) read32((void *)((uintptr_t)(addr))) +#define read64p(addr) read64((void *)((uintptr_t)(addr))) +#define write8p(addr, value) write8((void *)((uintptr_t)(addr)), value) +#define write16p(addr, value) write16((void *)((uintptr_t)(addr)), value) +#define write32p(addr, value) write32((void *)((uintptr_t)(addr)), value) +#define write64p(addr, value) write64((void *)((uintptr_t)(addr)), value) + /* Handy bit manipulation macros */ #define __clrsetbits(endian, bits, addr, clear, set) \ @@ -238,4 +248,19 @@ static inline void le64enc(void *pp, uint32_t u) #define clrbits32(addr, clear) clrsetbits32(addr, clear, 0) #define clrbits64(addr, clear) clrsetbits64(addr, clear, 0) +#define clrsetbits8p(addr, clear, set) clrsetbits8((void *)((uintptr_t)(addr)), clear, set) +#define clrsetbits16p(addr, clear, set) clrsetbits16((void *)((uintptr_t)(addr)), clear, set) +#define clrsetbits32p(addr, clear, set) clrsetbits32((void *)((uintptr_t)(addr)), clear, set) +#define clrsetbits64p(addr, clear, set) clrsetbits64((void *)((uintptr_t)(addr)), clear, set) + +#define setbits8p(addr, set) clrsetbits8((void *)((uintptr_t)(addr)), 0, set) +#define setbits16p(addr, set) clrsetbits16((void *)((uintptr_t)(addr)), 0, set) +#define setbits32p(addr, set) clrsetbits32((void *)((uintptr_t)(addr)), 0, set) +#define setbits64p(addr, set) clrsetbits64((void *)((uintptr_t)(addr)), 0, set) + +#define clrbits8p(addr, clear) clrsetbits8((void *)((uintptr_t)(addr)), clear, 0) +#define clrbits16p(addr, clear) clrsetbits16((void *)((uintptr_t)(addr)), clear, 0) +#define clrbits32p(addr, clear) clrsetbits32((void *)((uintptr_t)(addr)), clear, 0) +#define clrbits64p(addr, clear) clrsetbits64((void *)((uintptr_t)(addr)), clear, 0) + #endif /* _ENDIAN_H_ */ From 995e763f0921be994992b21dfdce0510003e0659 Mon Sep 17 00:00:00 2001 From: Elyes Haouas Date: Sun, 13 Oct 2024 07:50:10 +0200 Subject: [PATCH 02/15] payloads/libpayload: Add Wno-address-of-packed-member flag Change-Id: I47d7b5af67563de96fb5d8c200ce186a3443728b Signed-off-by: Elyes Haouas Reviewed-on: https://review.coreboot.org/c/coreboot/+/84756 Tested-by: build bot (Jenkins) Reviewed-by: Jakub Czapiga --- payloads/libpayload/Makefile.mk | 2 +- payloads/libpayload/tests/Makefile.mk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/Makefile.mk b/payloads/libpayload/Makefile.mk index c9cefb31eca..079fa325fea 100644 --- a/payloads/libpayload/Makefile.mk +++ b/payloads/libpayload/Makefile.mk @@ -79,7 +79,7 @@ CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer CFLAGS += -ffunction-sections -fdata-sections CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wvla CFLAGS += -Wwrite-strings -Wredundant-decls -Wimplicit-fallthrough -CFLAGS += -Wstrict-aliasing -Wshadow -Werror +CFLAGS += -Wstrict-aliasing -Wshadow -Wno-address-of-packed-member -Werror ifeq ($(CONFIG_LP_LTO),y) CFLAGS += -flto diff --git a/payloads/libpayload/tests/Makefile.mk b/payloads/libpayload/tests/Makefile.mk index 01f0a9ec8d1..a6cee5f480f 100644 --- a/payloads/libpayload/tests/Makefile.mk +++ b/payloads/libpayload/tests/Makefile.mk @@ -44,7 +44,7 @@ TEST_CFLAGS += -I$(cmockasrc)/include # Minimal subset of warnings and errors. Tests can be less strict than actual build. TEST_CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wvla -TEST_CFLAGS += -Wwrite-strings -Wimplicit-fallthrough +TEST_CFLAGS += -Wwrite-strings -Wno-address-of-packed-member -Wimplicit-fallthrough TEST_CFLAGS += -Wstrict-aliasing -Wshadow -Werror TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type From 9fe0ad0e21fcea6aa1417578794ffbfca58da395 Mon Sep 17 00:00:00 2001 From: Daniel Peng Date: Tue, 15 Oct 2024 09:34:40 +0800 Subject: [PATCH 03/15] mb/google/brya/var/glassway: Add Stylus Function 1. Add STYLUS fw_config setting. 2. Enable stylus device settings. 3. Disable the stylus GPIO pins based on fw_config. BUG=b:364798563 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot 2. Confirm command evtest for stylus PRP0001:00 and workable. Change-Id: Ifa8555eed1c31e9342a50a735fc618106f26d41a Signed-off-by: Daniel Peng Reviewed-on: https://review.coreboot.org/c/coreboot/+/84713 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Daniel Peng Reviewed-by: Paul Menzel --- .../google/brya/variants/glassway/Makefile.mk | 1 + .../google/brya/variants/glassway/fw_config.c | 22 +++++++++++++++++++ .../google/brya/variants/glassway/gpio.c | 4 ---- .../brya/variants/glassway/overridetree.cb | 18 +++++++++++++++ 4 files changed, 41 insertions(+), 4 deletions(-) create mode 100644 src/mainboard/google/brya/variants/glassway/fw_config.c diff --git a/src/mainboard/google/brya/variants/glassway/Makefile.mk b/src/mainboard/google/brya/variants/glassway/Makefile.mk index e409037840d..b4698058ab6 100644 --- a/src/mainboard/google/brya/variants/glassway/Makefile.mk +++ b/src/mainboard/google/brya/variants/glassway/Makefile.mk @@ -3,6 +3,7 @@ bootblock-y += gpio.c romstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/glassway/fw_config.c b/src/mainboard/google/brya/variants/glassway/fw_config.c new file mode 100644 index 00000000000..b4dfc508046 --- /dev/null +++ b/src/mainboard/google/brya/variants/glassway/fw_config.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static const struct pad_config stylus_disable_pads[] = { + /* F13 : SOC_PEN_DETECT_R_ODL */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : SOC_PEN_DETECT_ODL */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) { + printk(BIOS_INFO, "Disable Stylus GPIO pins.\n"); + gpio_padbased_override(padbased_table, stylus_disable_pads, + ARRAY_SIZE(stylus_disable_pads)); + } +} diff --git a/src/mainboard/google/brya/variants/glassway/gpio.c b/src/mainboard/google/brya/variants/glassway/gpio.c index 79697d533ba..f9e5c417cf7 100644 --- a/src/mainboard/google/brya/variants/glassway/gpio.c +++ b/src/mainboard/google/brya/variants/glassway/gpio.c @@ -32,10 +32,6 @@ static const struct pad_config override_gpio_table[] = { PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), /* F12 : WWAN_RST_L */ PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), - /* F13 : GSXSLOAD ==> NC */ - PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), - /* F15 : GSXSRESET# ==> NC */ - PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), /* H19 : SOC_I2C_SUB_INT_ODL */ PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), /* H22 : IMGCLKOUT3 ==> NC */ diff --git a/src/mainboard/google/brya/variants/glassway/overridetree.cb b/src/mainboard/google/brya/variants/glassway/overridetree.cb index 9e0f742f038..9e2738eef5e 100644 --- a/src/mainboard/google/brya/variants/glassway/overridetree.cb +++ b/src/mainboard/google/brya/variants/glassway/overridetree.cb @@ -21,6 +21,10 @@ fw_config option WIFI_SAR_ID_0 0 option WIFI_SAR_ID_1 1 end + field STYLUS 14 + option STYLUS_ABSENT 0 + option STYLUS_PRESENT 1 + end field WFC 16 17 option WFC_ABSENT 0 option WFC_PRESENT 1 @@ -368,6 +372,20 @@ chip soc/intel/alderlake probe TOUCHSCREEN_SOURCE TOUCHSCREEN_GTCH7503 end end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)" + register "key.wake_gpe" = "GPE0_DW2_15" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on + probe STYLUS STYLUS_PRESENT + end + end end #I2C1 device ref i2c3 on chip drivers/i2c/generic From a53b77effb84b7b3781275e7c37ec58e0c0ac148 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 21 Jul 2024 12:47:34 +0200 Subject: [PATCH 04/15] device/azalia: Clear busy bit after failed verb command The spec tells us to clear the busy bit manually after a timeout. Do that and wait immediately, to detect further issues early. Also fix some related comments and prints: Failures shouldn't be debug messa- ges. And we are talking to the PIO interface of the controller, not the codec. So this was never about the codec being ready. Change-Id: I4b737f8259157c01bfcd9e6631cc15d39c653d06 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/83592 Reviewed-by: Nicholas Sudsgaard Tested-by: build bot (Jenkins) --- src/device/azalia_device.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index c1673737642..dadcda918e6 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -155,10 +155,8 @@ u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, co } /* - * Wait 50usec for the codec to indicate it is ready. - * No response would imply that the codec is non-operative. + * Wait 50usec for the controller to indicate it is ready. */ - static int wait_for_ready(u8 *base) { struct stopwatch sw; @@ -179,7 +177,6 @@ static int wait_for_ready(u8 *base) * Wait for the codec to indicate that it accepted the previous command. * No response would imply that the codec is non-operative. */ - static int wait_for_valid(u8 *base) { struct stopwatch sw; @@ -206,6 +203,16 @@ static int wait_for_valid(u8 *base) udelay(1); } + /* + * HDA spec 1.0a "3.4.3 Offset 68h: Immediate Command Status" + * tells us to clear the busy bit explicitly, then poll until + * the controller is ready. + */ + write32(base + HDA_ICII_REG, 0); + if (wait_for_ready(base) < 0) { + printk(BIOS_WARNING, "azalia_audio: controller is unresponsive.\n"); + return -2; + } return -1; } @@ -238,7 +245,7 @@ __weak void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) static bool codec_is_operative(u8 *base, const int addr) { if (wait_for_ready(base) < 0) { - printk(BIOS_DEBUG, "azalia_audio: codec #%d not ready\n", addr); + printk(BIOS_WARNING, "azalia_audio: controller not ready\n"); return false; } @@ -246,7 +253,7 @@ static bool codec_is_operative(u8 *base, const int addr) write32(base + HDA_IC_REG, reg32); if (wait_for_valid(base) < 0) { - printk(BIOS_DEBUG, "azalia_audio: codec #%d not valid\n", addr); + printk(BIOS_NOTICE, "azalia_audio: codec #%d doesn't respond\n", addr); return false; } return true; From d11ee4952194934ebdea4ef5481b9095958eb247 Mon Sep 17 00:00:00 2001 From: Yang Wu Date: Mon, 14 Oct 2024 10:56:51 +0800 Subject: [PATCH 05/15] drivers/mipi: Update brightness for IVO_T109NW41 panel The current panel brightness is only 360 nits. Adjust the power and gamma to optimize the panel brightness. The brightness after adjustment is 390 nits. BUG=b:320892589 TEST=boot ciri with IVO_T109NW41 panel and see firmware screen BRANCH=geralt Change-Id: I760c37bf915bb40ad2efa7c947034cb168938f2a Signed-off-by: Yang Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/84758 Reviewed-by: Yidi Lin Reviewed-by: cong yang Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Yu-Ping Wu --- src/drivers/mipi/panel-IVO_T109NW41.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/drivers/mipi/panel-IVO_T109NW41.c b/src/drivers/mipi/panel-IVO_T109NW41.c index 97a69d3ea30..f604953aedd 100644 --- a/src/drivers/mipi/panel-IVO_T109NW41.c +++ b/src/drivers/mipi/panel-IVO_T109NW41.c @@ -21,7 +21,7 @@ struct panel_serializable_data IVO_T109NW41 = { .init = { PANEL_DELAY(60), PANEL_DCS(0xB9, 0x83, 0x10, 0x21, 0x55, 0x00), - PANEL_DCS(0xB1, 0x2C, 0xED, 0xED, 0x0F, 0xCF, 0x42, 0xF5, 0x39, + PANEL_DCS(0xB1, 0x2C, 0xED, 0xED, 0x27, 0xE7, 0x52, 0xF5, 0x39, 0x36, 0x36, 0x36, 0x36, 0x32, 0x8B, 0x11, 0x65, 0x00, 0x88, 0xFA, 0xFF, 0xFF, 0x8F, 0xFF, 0x08, 0xD6, 0x33), PANEL_DCS(0xB2, 0x00, 0x47, 0xB0, 0x80, 0x00, 0x12, 0x71, 0x3C, @@ -65,11 +65,11 @@ struct panel_serializable_data IVO_T109NW41 = { 0xAA, 0xAA, 0xAA, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - PANEL_DCS(0xE0, 0x04, 0X04, 0X06, 0X0A, 0X0A, 0X05, 0X12, 0X14, - 0X17, 0X13, 0X2C, 0X33, 0X39, 0X4B, 0X4C, 0X56, 0X61, 0X78, - 0X7A, 0X41, 0X50, 0X68, 0X73, 0X04, 0X04, 0X06, 0X0A, 0X0A, - 0X05, 0X12, 0X14, 0X17, 0X13, 0X2C, 0X33, 0X39, 0X4B, 0X4C, - 0X56, 0X61, 0X78, 0X7A, 0X41, 0X50, 0X68, 0X73), + PANEL_DCS(0xE0, 0x00, 0x07, 0x10, 0x17, 0x1C, 0x33, 0x48, 0x50, + 0x57, 0x50, 0x68, 0x6E, 0x71, 0x7F, 0x81, 0x8A, 0x8E, 0x9B, + 0x9C, 0x4D, 0x56, 0x5D, 0x73, 0x00, 0x07, 0x10, 0x17, 0x1C, + 0x33, 0x48, 0x50, 0x57, 0x50, 0x68, 0x6E, 0x71, 0x7F, 0x81, + 0x8A, 0x8E, 0x9B, 0x9C, 0x4D, 0x56, 0x5D, 0x73), PANEL_DCS(0xE7, 0x07, 0x10, 0x10, 0x1A, 0x26, 0x9E, 0x00, 0x4F, 0xA0, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x0A, 0x02, 0x02, 0x00, 0x33, 0x02, 0x04, 0x18, 0x01), From 1d18513ad5d10034effb0b10e7db11487fa7e6cf Mon Sep 17 00:00:00 2001 From: Naresh Solanki Date: Fri, 11 Oct 2024 22:51:38 +0530 Subject: [PATCH 06/15] soc/intel/xeon_sp: Allow Memory POR independent of RMT TEST=Build & boot in IBM SBP1 system. Verified the settings are effective in FSP logs. Change-Id: I4341ead89a2683f64c834a6981ba316fcfef4f9a Signed-off-by: Naresh Solanki Reviewed-on: https://review.coreboot.org/c/coreboot/+/84741 Reviewed-by: Shuo Liu Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/spr/Kconfig | 3 +-- src/soc/intel/xeon_sp/spr/romstage.c | 4 ++-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index b84a8ff2677..6fad812941a 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -174,10 +174,9 @@ config ENABLE_RMT Enable Rank Margining Tool. This option is intended for debugging and validation and should normally be disabled. -config RMT_MEM_POR_FREQ +config MEM_POR_FREQ bool "Enforce Plan Of Record restrictions for DDR5 frequency and voltage" default n - depends on ENABLE_RMT help When RMT is enabled. Select this option to enforce Intel Plan Of Record(POR) restriction on DDR5 frequency & voltage settings. diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index b05c7e76fdb..4d95a33365e 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -241,9 +241,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mupd->FspmConfig.serialDebugMsgLvl = 0x3; mupd->FspmConfig.AllowedSocketsInParallel = 0x1; mupd->FspmConfig.EnforcePopulationPor = 0x1; - if (CONFIG(RMT_MEM_POR_FREQ)) - mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0; } + if (CONFIG(MEM_POR_FREQ)) + mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0; /* SPR-FSP has no UPD to disable HDA, so do it manually here... */ if (!is_devfn_enabled(PCH_DEVFN_HDA)) From ad0d2cad8b6c6cc8f4f5e1cc698a597251638036 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 14 Oct 2024 09:07:47 +0200 Subject: [PATCH 07/15] smbios: Add slot types Add slot types found in SMBIOS spec 3.8.0. Change-Id: I705529efcbf2add420fb6f4a720ec33444d46efa Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/84760 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/include/smbios.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/include/smbios.h b/src/include/smbios.h index b5b9e7a83fd..fd44e098d4e 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -870,7 +870,10 @@ enum misc_slot_type { SlotTypePciExpressGen5x2 = 0xC0, SlotTypePciExpressGen5x4 = 0xC1, SlotTypePciExpressGen5x8 = 0xC2, - SlotTypePciExpressGen5x16 = 0xC3 + SlotTypePciExpressGen5x16 = 0xC3, + SlotTypePciExpressGen6AndBeyond = 0xC4, + SlotTypeEDSFF_E1 = 0xC5, + SlotTypeEDSFF_E3 = 0xC6, }; /* System Slots - Slot Data Bus Width. */ From f6ecfbc12b4d4c02cc33b1d854ec9a473fe3f2fb Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 26 Sep 2024 16:58:47 +0200 Subject: [PATCH 08/15] mb/ibm/sbp1: Add SMBIOS slots Add the BMC and all PCIe slots that the board implements. There are 32 RSSDs and 2 M.2 slots. Change-Id: Id7d72990d6997d1e8b9ce75477ce3dc571c99839 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/84560 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/ibm/sbp1/devicetree.cb | 133 ++++++++++++++++++++++++++- 1 file changed, 131 insertions(+), 2 deletions(-) diff --git a/src/mainboard/ibm/sbp1/devicetree.cb b/src/mainboard/ibm/sbp1/devicetree.cb index 2f8b4a4cb74..1b4bfc67209 100644 --- a/src/mainboard/ibm/sbp1/devicetree.cb +++ b/src/mainboard/ibm/sbp1/devicetree.cb @@ -1,13 +1,22 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip soc/intel/xeon_sp/spr - device domain 0 on device pci 16.3 off end # Serial controller: Intel Corporation Device 1be3 device pci 17.0 off end # Intel device 1ba2: PCH SATA controller 0 (AHCI) device pci 18.0 off end # Intel device 1bf2: PCH SATA controller 1 (AHCI) device pci 19.0 off end # Intel device 1bd2: PCH SATA controller 2 (AHCI) - + device pci 0a.0 on # M.2_1 + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthLong" "M.2_1" "SlotDataBusWidth4X" + end + device pci 0f.0 on + device pci 0 on # BMC + device pci 0 on end # VGA + end + end + device pci 10.0 on # M.2_2 + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthLong" "M.2_2" "SlotDataBusWidth4X" + end device pci 1f.0 on # Intel device 1b81: PCH eSPI controller chip drivers/ipmi # BMC KCS device pnp ca2.0 on end @@ -21,4 +30,124 @@ chip soc/intel/xeon_sp/spr device pci 1f.3 off end # Intel device 1bc8: PCH audio device pci 1f.6 off end # Intel device 1bcb: PCH GbE controller end + device domain 226 on + device pci 00.0 on end # VTD + device pci 01.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD12" "SlotDataBusWidth4X" + end + device pci 03.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD11" "SlotDataBusWidth4X" + end + device pci 05.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD10" "SlotDataBusWidth4X" + end + device pci 07.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD09" "SlotDataBusWidth4X" + end + end + device domain 337 on + device pci 00.0 on end # VTD + device pci 01.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD13" "SlotDataBusWidth4X" + end + device pci 03.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD14" "SlotDataBusWidth4X" + end + device pci 05.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD15" "SlotDataBusWidth4X" + end + device pci 07.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD16" "SlotDataBusWidth4X" + end + end + device domain 102a7 on + device pci 00.0 on end # VTD + device pci 01.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD28" "SlotDataBusWidth4X" + end + device pci 03.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD27" "SlotDataBusWidth4X" + end + device pci 05.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD26" "SlotDataBusWidth4X" + end + device pci 07.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD25" "SlotDataBusWidth4X" + end + end + device domain 103b7 on + device pci 00.0 on end # VTD + device pci 01.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD29" "SlotDataBusWidth4X" + end + device pci 03.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD30" "SlotDataBusWidth4X" + end + device pci 05.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD31" "SlotDataBusWidth4X" + end + device pci 07.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD32" "SlotDataBusWidth4X" + end + end + device domain 20448 on + device pci 00.0 on end # VTD + device pci 01.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD17" "SlotDataBusWidth4X" + end + device pci 03.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD18" "SlotDataBusWidth4X" + end + device pci 05.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD19" "SlotDataBusWidth4X" + end + device pci 07.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD20" "SlotDataBusWidth4X" + end + end + device domain 20559 on + device pci 00.0 on end # VTD + device pci 01.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD24" "SlotDataBusWidth4X" + end + device pci 03.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD23" "SlotDataBusWidth4X" + end + device pci 05.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD22" "SlotDataBusWidth4X" + end + device pci 07.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD21" "SlotDataBusWidth4X" + end + end + device domain 304c7 on + device pci 00.0 on end # VTD + device pci 01.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD01" "SlotDataBusWidth4X" + end + device pci 03.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD02" "SlotDataBusWidth4X" + end + device pci 05.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD03" "SlotDataBusWidth4X" + end + device pci 07.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD04" "SlotDataBusWidth4X" + end + end + device domain 305d7 on + device pci 00.0 on end # VTD + device pci 01.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD08" "SlotDataBusWidth4X" + end + device pci 03.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD07" "SlotDataBusWidth4X" + end + device pci 05.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD06" "SlotDataBusWidth4X" + end + device pci 07.0 on + smbios_slot_desc "SlotTypeEDSFF_E1" "SlotLengthLong" "RSSD05" "SlotDataBusWidth4X" + end + end end From 6d1dbe12d2f869388ddb51e0cef7bf30ce80b255 Mon Sep 17 00:00:00 2001 From: Naresh Solanki Date: Fri, 17 Nov 2023 02:21:57 +0530 Subject: [PATCH 09/15] mb/arm/rdn2: Add support for Arm Neoverse N2 Add support for Arm Neoverse N2 Reference design. Based on Arm Neoverse N2 reference design Revision: Release D TEST=Build Arm Neoverse N2 & make sure there is no error. Change-Id: I17908d3ce773d4a88924bafb1d0e9e2a043c7fbc Signed-off-by: Naresh Solanki Reviewed-on: https://review.coreboot.org/c/coreboot/+/79103 Tested-by: build bot (Jenkins) Reviewed-by: Maximilian Brune Reviewed-by: Julius Werner --- src/mainboard/arm/Kconfig | 18 ++ src/mainboard/arm/Kconfig.name | 4 + src/mainboard/arm/rdn2/Kconfig | 64 +++++ src/mainboard/arm/rdn2/Kconfig.name | 8 + src/mainboard/arm/rdn2/Makefile.mk | 19 ++ src/mainboard/arm/rdn2/acpi.c | 207 ++++++++++++++++ src/mainboard/arm/rdn2/board_info.txt | 3 + src/mainboard/arm/rdn2/bootblock.c | 37 +++ src/mainboard/arm/rdn2/bootblock_custom.S | 31 +++ src/mainboard/arm/rdn2/cbmem.c | 11 + src/mainboard/arm/rdn2/chip.h | 11 + src/mainboard/arm/rdn2/devicetree.cb | 10 + src/mainboard/arm/rdn2/dsdt.asl | 227 ++++++++++++++++++ src/mainboard/arm/rdn2/flash.fmd | 9 + .../arm/rdn2/include/mainboard/addressmap.h | 97 ++++++++ src/mainboard/arm/rdn2/mainboard.c | 156 ++++++++++++ src/mainboard/arm/rdn2/media.c | 13 + src/mainboard/arm/rdn2/memlayout.ld | 27 +++ src/mainboard/arm/rdn2/pptt.c | 218 +++++++++++++++++ src/mainboard/arm/rdn2/uart.c | 9 + 20 files changed, 1179 insertions(+) create mode 100644 src/mainboard/arm/Kconfig create mode 100644 src/mainboard/arm/Kconfig.name create mode 100644 src/mainboard/arm/rdn2/Kconfig create mode 100644 src/mainboard/arm/rdn2/Kconfig.name create mode 100644 src/mainboard/arm/rdn2/Makefile.mk create mode 100644 src/mainboard/arm/rdn2/acpi.c create mode 100644 src/mainboard/arm/rdn2/board_info.txt create mode 100644 src/mainboard/arm/rdn2/bootblock.c create mode 100644 src/mainboard/arm/rdn2/bootblock_custom.S create mode 100644 src/mainboard/arm/rdn2/cbmem.c create mode 100644 src/mainboard/arm/rdn2/chip.h create mode 100644 src/mainboard/arm/rdn2/devicetree.cb create mode 100644 src/mainboard/arm/rdn2/dsdt.asl create mode 100644 src/mainboard/arm/rdn2/flash.fmd create mode 100644 src/mainboard/arm/rdn2/include/mainboard/addressmap.h create mode 100644 src/mainboard/arm/rdn2/mainboard.c create mode 100644 src/mainboard/arm/rdn2/media.c create mode 100644 src/mainboard/arm/rdn2/memlayout.ld create mode 100644 src/mainboard/arm/rdn2/pptt.c create mode 100644 src/mainboard/arm/rdn2/uart.c diff --git a/src/mainboard/arm/Kconfig b/src/mainboard/arm/Kconfig new file mode 100644 index 00000000000..f962b346211 --- /dev/null +++ b/src/mainboard/arm/Kconfig @@ -0,0 +1,18 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_ARM + +choice + prompt "Mainboard model" + default BOARD_ARM_RDN2 + +source "src/mainboard/arm/*/Kconfig.name" + +endchoice + +source "src/mainboard/arm/*/Kconfig" + +config MAINBOARD_VENDOR + default "Arm" + +endif # VENDOR_ARM diff --git a/src/mainboard/arm/Kconfig.name b/src/mainboard/arm/Kconfig.name new file mode 100644 index 00000000000..a6a7f784c30 --- /dev/null +++ b/src/mainboard/arm/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config VENDOR_ARM + bool "Arm" diff --git a/src/mainboard/arm/rdn2/Kconfig b/src/mainboard/arm/rdn2/Kconfig new file mode 100644 index 00000000000..106684ccb03 --- /dev/null +++ b/src/mainboard/arm/rdn2/Kconfig @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_ARM_RDN2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARM64_USE_ARCH_TIMER + select BOARD_ROMSIZE_KB_65536 + select BOOTBLOCK_CUSTOM + select DRIVERS_UART_PL011 + select HAVE_ACPI_TABLES + select ACPI_GTDT + select ACPI_COMMON_MADT_GICC_V3 + select MISSING_BOARD_RESET + select PCI + select PROBE_RAM + select ACPI_IORT + select ACPI_GTDT + select ACPI_COMMON_MADT_GICC_V3 + select ACPI_PPTT + select GENERATE_SMBIOS_TABLES + +config ARM64_CURRENT_EL + default 2 + +config ECAM_MMCONF_BASE_ADDRESS + default 0x1010000000 + +config ECAM_MMCONF_BUS_NUMBER + default 256 + +config MEMLAYOUT_LD_FILE + string + default "src/mainboard/arm/rdn2/memlayout.ld" + +config FATAL_ASSERTS + default y + +config FMDFILE + default "src/mainboard/arm/rdn2/flash.fmd" + +config MAINBOARD_DIR + default "arm/rdn2" + +config MAINBOARD_PART_NUMBER + default "Neoverse N2" + +config MAX_CPUS + int + default 128 + +config MAINBOARD_VENDOR + string + default "Arm" + +config DRAM_SIZE_MB + int + default 2048 + +endif # BOARD_ARM_RDN2 diff --git a/src/mainboard/arm/rdn2/Kconfig.name b/src/mainboard/arm/rdn2/Kconfig.name new file mode 100644 index 00000000000..1a9eed5f82f --- /dev/null +++ b/src/mainboard/arm/rdn2/Kconfig.name @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_ARM_RDN2 + bool "Neoverse N2" + help + To execute, do: + FVP_RD_N2\models\Win64_VC2019\FVP_RD_N2 -C board.flashloader0.fname=coreboot.rom \ + -C css.trustedBootROMloader.fname=bl1.bin diff --git a/src/mainboard/arm/rdn2/Makefile.mk b/src/mainboard/arm/rdn2/Makefile.mk new file mode 100644 index 00000000000..efc6de97f92 --- /dev/null +++ b/src/mainboard/arm/rdn2/Makefile.mk @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +romstage-y += cbmem.c + +bootblock-y += media.c +romstage-y += media.c +ramstage-y += media.c + +bootblock-y += uart.c +romstage-y += uart.c +ramstage-y += uart.c +ramstage-y += acpi.c +ramstage-$(CONFIG_ACPI_PPTT) += pptt.c + +bootblock-y += bootblock_custom.S + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/arm/rdn2/acpi.c b/src/mainboard/arm/rdn2/acpi.c new file mode 100644 index 00000000000..941c2f47670 --- /dev/null +++ b/src/mainboard/arm/rdn2/acpi.c @@ -0,0 +1,207 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + return current; +} + +uintptr_t platform_get_gicd_base(void) +{ + return RDN2_GIC_DIST; +} + +uintptr_t platform_get_gicr_base(void) +{ + return RDN2_GIC_REDIST; +} + +void platform_fill_gicc(acpi_madt_gicc_t *gicc) +{ + gicc->physical_base_address = platform_get_gicd_base(); + gicc->gicv = RDN2_VGIC_BASE; + gicc->gich = RDN2_HGIC_BASE; + + if (gicc->mpidr >> 16 == 0xf) + gicc->trbe_interrupt = 0x180c; + else + gicc->trbe_interrupt = 0x500b; +} + +static uintptr_t gic_its[] = { + RDN2_GIC_ITS(0), + RDN2_GIC_ITS(1), + RDN2_GIC_ITS(2), + RDN2_GIC_ITS(3), + RDN2_GIC_ITS(4), + RDN2_GIC_ITS(5) +}; + +int platform_get_gic_its(uintptr_t **base) +{ + *base = gic_its; + return ARRAY_SIZE(gic_its); +} + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_DESKTOP; + fadt->ARM_boot_arch = 1; +} + +void acpi_soc_fill_gtdt(acpi_gtdt_t *gtdt) +{ + /* his value is optional if the system implements EL3 (Security + Extensions). If not provided, this field must be 0xFFFFFFFFFFFFFFFF. */ + gtdt->counter_block_address = UINT64_MAX; + gtdt->secure_el1_interrupt = SEC_EL1_TIMER_GISV; + gtdt->secure_el1_flags = RDN2_TIMER_FLAGS; + gtdt->non_secure_el1_interrupt = NONSEC_EL1_TIMER_GSIV; + gtdt->non_secure_el1_flags = RDN2_TIMER_FLAGS; + gtdt->virtual_timer_interrupt = VIRTUAL_TIMER_GSIV; + gtdt->virtual_timer_flags = RDN2_TIMER_FLAGS; + gtdt->non_secure_el2_interrupt = NONSEC_EL2_TIMER_GSIV; + gtdt->non_secure_el2_flags = RDN2_TIMER_FLAGS; + /* his value is optional if the system implements EL3 + (Security Extensions). If not provided, this field must be + 0xFFFFFFFFFFFFFFF. */ + gtdt->counter_read_block_address = UINT64_MAX; +} + +unsigned long acpi_soc_gtdt_add_timers(uint32_t *count, unsigned long current) +{ + struct acpi_gtdt_timer_entry timers[2]; + + memset(timers, 0, sizeof(timers)); + (*count)++; + timers[0].frame_number = 0; + timers[0].base_address = RDN2_GT_FRAME1_CTL_BASE; + timers[0].el0_base_address = UINT64_MAX; + timers[0].timer_interrupt = RDN2_GT_FRAME1_GSIV; + timers[0].timer_flags = 0; + timers[0].virtual_timer_interrupt = 0; + timers[0].virtual_timer_flags = 0; + timers[0].common_flags = ACPI_GTDT_GT_ALWAYS_ON; + + + (*count)++; + timers[1].frame_number = 1; + timers[1].base_address = RDN2_GT_FRAME0_CTL_BASE; + timers[1].el0_base_address = UINT64_MAX; + timers[1].timer_interrupt = RDN2_GT_FRAME0_GSIV; + timers[1].timer_flags = 0; + timers[1].virtual_timer_interrupt = 0; + timers[1].virtual_timer_flags = 0; + timers[1].common_flags = ACPI_GTDT_GT_ALWAYS_ON | ACPI_GTDT_GT_IS_SECURE_TIMER; + + current = acpi_gtdt_add_timer_block(current, RDN2_GT_CTL_BASE, timers, 2); + + (*count)++; + current = acpi_gtdt_add_watchdog(current, RDN2_GWDT_REFRESH, RDN2_GWDT_CONTROL, + RDN2_GWDT_WS0_GSIV, 0); + /* Secure */ + current = acpi_gtdt_add_watchdog(current, RDN2_GWDT_REFRESH, RDN2_GWDT_CONTROL, + RDN2_GWDT_WS1_GSIV, ACPI_GTDT_WATCHDOG_SECURE); + + return current; +} + +static unsigned long acpi_soc_fill_iort_tcu4(acpi_iort_t *iort, unsigned long current) +{ + acpi_iort_node_t *its, *smmu_v3, *named_comp; + u32 identifiers[] = {4}; + u32 its_reference, smmuv3_reference; + + current = acpi_iort_its_entry(current, iort, &its, 1, identifiers); + its_reference = (unsigned long)its - (unsigned long)iort; + + current = acpi_iort_smmuv3_entry(current, iort, &smmu_v3, RDN2_SMMU_V3(4), ACPI_IORT_SMMU_V3_FLAGS); + smmuv3_reference = (unsigned long)smmu_v3 - (unsigned long)iort; + + /* Individual maps here */ + current = acpi_iort_id_map_entry(current, smmu_v3, 0, 1, 0x80000, its_reference, + ACPI_IORT_ID_SINGLE_MAPPING); + + current = acpi_iort_id_map_entry(current, smmu_v3, 0x10000, 10, 0x10000, its_reference, 0); + + current = acpi_iort_id_map_entry(current, smmu_v3, 0x30000, 10, 0x30000, its_reference, 0); + + /* SMMUV3 entry length includes mapping */ + + for (int n = 0 ; n < 2 ; n++) { + /* DMA */ + char dma[32]; + snprintf(dma, sizeof(dma), "\\_SB_.DMA%d", n); + + current = acpi_iort_nc_entry(current, iort, &named_comp, 0, 0, 0x30, dma); + + for (int i = 0 ; i < 9 ; i++) { + /* ID */ + current = acpi_iort_id_map_entry(current, named_comp, i, 1, 0x10000 + n * 0x20000 + i, + smmuv3_reference, ACPI_IORT_ID_SINGLE_MAPPING); + } + } + + + return current; +} + +static unsigned long acpi_soc_fill_iort_tcu(u32 i, u16 id_count, u32 *smmu_offset, + acpi_iort_t *iort, unsigned long current) +{ + + acpi_iort_node_t *its, *smmu_v3; + static u32 id_base = 0x30000; + u32 its_reference; + + current = acpi_iort_its_entry(current, iort, &its, 1, &i); + its_reference = (unsigned long)its - (unsigned long)iort; + + current = acpi_iort_smmuv3_entry(current, iort, &smmu_v3, RDN2_SMMU_V3(i), ACPI_IORT_SMMU_V3_FLAGS); + + *smmu_offset = (unsigned long)smmu_v3 - (unsigned long)iort; + + /* Individual maps here */ + current = acpi_iort_id_map_entry(current, smmu_v3, 0, 1, 0x80000, its_reference, + ACPI_IORT_ID_SINGLE_MAPPING); + + current = acpi_iort_id_map_entry(current, smmu_v3, id_base, id_count, id_base, its_reference, 0); + id_base += id_count; + + /* SMMUV3 entry length includes mapping */ + + return current; +} + +unsigned long acpi_soc_fill_iort(acpi_iort_t *iort, unsigned long current) +{ + acpi_iort_node_t *root_comp; + u32 smmu_offset[4]; + uint32_t id_count[] = {768, 256, 256, 256}; + + for (int i = 0; i < 4; i++) + current = acpi_soc_fill_iort_tcu(i, id_count[i], &smmu_offset[i], iort, current); + + current = acpi_soc_fill_iort_tcu4(iort, current); + + current = acpi_iort_rc_entry(current, iort, &root_comp, 0, ACPI_IORT_ATS_SUPPORTED, 0, + 0x30, 0); + + u32 base = 0; + for (int i = 0 ; i < 4 ; i++) { + current = acpi_iort_id_map_entry(current, root_comp, base, id_count[i], 0x30000 + base, + smmu_offset[i], 0); + base += id_count[i]; + } + + return current; +} diff --git a/src/mainboard/arm/rdn2/board_info.txt b/src/mainboard/arm/rdn2/board_info.txt new file mode 100644 index 00000000000..1338ec2c9bc --- /dev/null +++ b/src/mainboard/arm/rdn2/board_info.txt @@ -0,0 +1,3 @@ +Board name: Neoverse N2 +Category: emulation +Board URL: https://developer.arm.com/documentation/102337/latest/ diff --git a/src/mainboard/arm/rdn2/bootblock.c b/src/mainboard/arm/rdn2/bootblock.c new file mode 100644 index 00000000000..5b59e7e033c --- /dev/null +++ b/src/mainboard/arm/rdn2/bootblock.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +DECLARE_REGION(dev_mem) + +void bootblock_mainboard_init(void) +{ + mmu_init(); + + /* NOR Flash 0 */ + mmu_config_range((void *)RDN2_FLASH_BASE, (uintptr_t)RDN2_FLASH_SIZE, + MA_MEM | MA_RO | MA_MEM_NC); + + /* device memory */ + mmu_config_range(_dev_mem, _dram - _dev_mem, MA_DEV | MA_RW); + + /* Set a dummy value for DRAM. ramstage should update the mapping. */ + mmu_config_range(_dram, ((size_t) 2 * GiB) - 16*MiB, MA_MEM | MA_RW); + + mmu_config_range((void *)RDN2_DRAM2_BASE, RDN2_DRAM2_SIZE, MA_MEM | MA_RW); + + mmu_config_range(_ttb, REGION_SIZE(ttb), MA_MEM | MA_S | MA_RW); + + mmu_config_range(_stack, REGION_SIZE(stack), MA_MEM | MA_S | MA_RW); + mmu_config_range(_cbfs_mcache, REGION_SIZE(cbfs_mcache), MA_MEM | MA_S | MA_RW); + mmu_config_range(_fmap_cache, REGION_SIZE(fmap_cache), MA_MEM | MA_S | MA_RW); + mmu_config_range(_timestamp, REGION_SIZE(timestamp), MA_MEM | MA_S | MA_RW); + + mmu_config_range((void *)CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, + MA_DEV | MA_RW); + mmu_enable(); +} diff --git a/src/mainboard/arm/rdn2/bootblock_custom.S b/src/mainboard/arm/rdn2/bootblock_custom.S new file mode 100644 index 00000000000..f8cca02d9fc --- /dev/null +++ b/src/mainboard/arm/rdn2/bootblock_custom.S @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +/* + * Note: This board uses boot flow: TFA -> coreboot. + */ +ENTRY(_start) + + /* TF-A arg which contains a pointer to fdt */ + ldr x1, =_fdt_pointer + str x0, [x1] + + msr SPSel, #0 /* use SP_EL0 */ + + /* ==== stack init from arm64_init_cpu ==== */ + ldr x2, =0xdeadbeefdeadbeef + ldr x0, =_stack + ldr x1, =_estack +1: + stp x2, x2, [x0], #16 + cmp x0, x1 + bne 1b + + sub sp, x0, #16 + + /* ==== END ==== */ + + /* Jump to main() in DRAM. */ + bl main +ENDPROC(_start) diff --git a/src/mainboard/arm/rdn2/cbmem.c b/src/mainboard/arm/rdn2/cbmem.c new file mode 100644 index 00000000000..a8ad03399ca --- /dev/null +++ b/src/mainboard/arm/rdn2/cbmem.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +uintptr_t cbmem_top_chipset(void) +{ + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); +} diff --git a/src/mainboard/arm/rdn2/chip.h b/src/mainboard/arm/rdn2/chip.h new file mode 100644 index 00000000000..ae19df9763e --- /dev/null +++ b/src/mainboard/arm/rdn2/chip.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_ARM_RDN2_CHIP_H +#define MAINBOARD_ARM_RDN2_CHIP_H + +#include + +struct mainboard_arm_rdn2_config { +}; + +#endif diff --git a/src/mainboard/arm/rdn2/devicetree.cb b/src/mainboard/arm/rdn2/devicetree.cb new file mode 100644 index 00000000000..f85d243e48c --- /dev/null +++ b/src/mainboard/arm/rdn2/devicetree.cb @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip mainboard/arm/rdn2 + + device cpu_cluster 0 on ops rdn2_aarch64_cpu_ops end + + device domain 0 on ops rdn2_aarch64_pci_domain_ops + device pci 00.0 on end + end +end diff --git a/src/mainboard/arm/rdn2/dsdt.asl b/src/mainboard/arm/rdn2/dsdt.asl new file mode 100644 index 00000000000..2e795b8eedd --- /dev/null +++ b/src/mainboard/arm/rdn2/dsdt.asl @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20230621 // OEM revision +) +{ + #include + + Device (COM0) + { + Name (_HID, "ARMH0011") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + RDN2_UART_NS_BASE, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + RDN2_UART_NS_GSIV, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0xf) + } + } + + Device (VR00) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0C130000, // Address Base + 0x00010000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x000001CA, + } + }) + } + + Device (VR01) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0C150000, // Address Base + 0x00010000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x000001CC, + } + }) + } + + + Device (\_SB.DMA0) + { + Name (_HID, "ARMH0330") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_STA, 0x0F) // _STA: Status + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0x0000000000000001, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000000000002, // Length + ,, _Y02, AddressRangeMemory, TypeStatic) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x000001ED, + 0x000001EE, + 0x000001EF, + 0x000001F0, + 0x000001F1, + 0x000001F2, + 0x000001F3, + 0x000001F4, + 0x000001F5, + } + }) + CreateQWordField (RBUF, \_SB.DMA0._CRS._Y02._MIN, MIN2) // _MIN: Minimum Base Address + CreateQWordField (RBUF, \_SB.DMA0._CRS._Y02._MAX, MAX2) // _MAX: Maximum Base Address + CreateQWordField (RBUF, \_SB.DMA0._CRS._Y02._LEN, LEN2) // _LEN: Length + MIN2 = RDN2_DMA0_BASE + MAX2 = (MIN2 + 0xFFFF) + LEN2 = 0x00010000 + Return (RBUF) /* \_SB_.DMA0._CRS.RBUF */ + } + } + + Device (\_SB.DMA1) + { + Name (_HID, "ARMH0330") // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_STA, 0x0F) // _STA: Status + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0x0000000000000001, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000000000002, // Length + ,, _Y03, AddressRangeMemory, TypeStatic) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x000001F7, + 0x000001F8, + 0x000001F9, + 0x000001FA, + 0x000001FB, + 0x000001FC, + 0x000001FD, + 0x000001FE, + 0x000001FF, + } + }) + CreateQWordField (RBUF, \_SB.DMA1._CRS._Y03._MIN, MIN2) // _MIN: Minimum Base Address + CreateQWordField (RBUF, \_SB.DMA1._CRS._Y03._MAX, MAX2) // _MAX: Maximum Base Address + CreateQWordField (RBUF, \_SB.DMA1._CRS._Y03._LEN, LEN2) // _LEN: Length + MIN2 = RDN2_DMA1_BASE + MAX2 = (MIN2 + 0xFFFF) + LEN2 = 0x00010000 + Return (RBUF) /* \_SB_.DMA1._CRS.RBUF */ + } + } + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08")) // PCI Express Bus _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03")) // PCI Bus _CID: Compatible ID + Name (_SEG, Zero) // _SEG: PCI Segment + Name (_BBN, Zero) // _BBN: BIOS Bus Number + Name (_UID, "PCI0") // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0xf) + } + + Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address + { + Return (RDN2_PCIE_ECAM_BASE) + } + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + RDN2_PCIE_MMIO_BASE, // Range Minimum + RDN2_PCIE_MMIO_LIMIT, // Range Maximum + 0x00000000, // Translation Offset + RDN2_PCIE_MMIO_SIZE, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + RDN2_PCIE_MMIO_HIGH_BASE, // Range Minimum + RDN2_PCIE_MMIO_HIGH_LIMIT, // Range Maximum + 0x0000000000000000, // Translation Offset + RDN2_PCIE_MMIO_HIGH_SIZE, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x007FFFFF, // Range Maximum + 0x77800000, // Translation Offset + 0x00800000, // Length + ,, , TypeTranslation, DenseTranslation) + }) + Return (RBUF) /* \PCI0._CRS.RBUF */ + } + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + RDN2_PCIE_ECAM_BASE, // Range Minimum + RDN2_PCIE_ECAM_LIMIT, // Range Maximum + 0x0000000000000000, // Translation Offset + RDN2_PCIE_ECAM_SIZE, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0xf) + } + } + } +} diff --git a/src/mainboard/arm/rdn2/flash.fmd b/src/mainboard/arm/rdn2/flash.fmd new file mode 100644 index 00000000000..2b75d355d18 --- /dev/null +++ b/src/mainboard/arm/rdn2/flash.fmd @@ -0,0 +1,9 @@ +FLASH@0x08000000 CONFIG_ROM_SIZE { + + BIOS@0x0 CONFIG_ROM_SIZE { + + BOOTBLOCK 128K + FMAP@0x20000 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/arm/rdn2/include/mainboard/addressmap.h b/src/mainboard/arm/rdn2/include/mainboard/addressmap.h new file mode 100644 index 00000000000..5d218c2585b --- /dev/null +++ b/src/mainboard/arm/rdn2/include/mainboard/addressmap.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Memory map for Neoverse N2 + * See Technical Reference: Table 5-2: FVP board peripherals + */ + +#define RDN2_FLASH_BASE 0x08000000 +#define RDN2_FLASH_SIZE (64 * MiB) + +/* Actual DRAM size should be probed */ +#define RDN2_DRAM_BASE 0x80000000 +#define RDN2_DRAM_SIZE (2 * GiB) + +#define RDN2_SECMEM_BASE 0xff000000 +#define RDN2_SECMEM_SIZE (16 * MiB) + +#define RDN2_DRAM2_BASE 0x8080000000 +#define RDN2_DRAM2_SIZE (6UL * GiB) + +#define RDN2_GIC_DIST 0x30000000 +#define RDN2_GIC_REDIST 0x301C0000 +#define RDN2_VGIC_BASE 0x2c020000 +#define RDN2_HGIC_BASE 0x2c010000 + +#define RDN2_GIC_ITS_BASE 0x30040000 +#define RDN2_GIC_ITS_SIZE 0x40000 +#define RDN2_GIC_ITS(i) (RDN2_GIC_ITS_BASE + i * RDN2_GIC_ITS_SIZE) + +#define SEC_EL1_TIMER_GISV 29 +#define NONSEC_EL1_TIMER_GSIV 30 +#define VIRTUAL_TIMER_GSIV 27 +#define NONSEC_EL2_TIMER_GSIV 26 + +#define RDN2_TIMER_FLAGS (ACPI_GTDT_INTERRUPT_POLARITY) +#define RDN2_GT_CTL_BASE 0x2A810000 +#define RDN2_GT_FRAME0_CTL_BASE 0x2A820000 +#define RDN2_GT_FRAME0_EL0_BASE -1 +#define RDN2_GT_FRAME0_GSIV 0x6c + +#define RDN2_GT_FRAME1_CTL_BASE 0x2A830000 +#define RDN2_GT_FRAME1_EL0_BASE -1 +#define RDN2_GT_FRAME1_GSIV 0x6d + +#define RDN2_GWDT_REFRESH 0x2a450000 +#define RDN2_GWDT_CONTROL 0x2a440000 +#define RDN2_GWDT_WS0_GSIV 0x6e +#define RDN2_GWDT_WS1_GSIV 0x6f + +#define RDN2_UART_CLK_HZ 7372800 +#define RDN2_UART_NS_BASE 0x2a400000 +#define RDN2_UART_NS_GSIV 112 +#define RDN2_SECURE_UART_BASE 0x2a410000 +#define RDN2_SECURE_UART_GSIV 81 + +#define RDN2_RTC_BASE 0x0C170000 +#define RDN2_RTC1_BASE 0x0C180000 +#define RDN2_GPIO_BASE 0x0c1d0000 +#define RDN2_GPIO1_BASE 0x0c1e0000 + +#define RDN2_SMMU_BASE 0x40000000 +#define RDN2_SMMU_SIZE 0x2000000 + + + + +#define RDN2_SMMU_V3(i) (RDN2_SMMU_BASE + i * RDN2_SMMU_SIZE) +#define ACPI_IORT_SMMU_V3_FLAGS (ACPI_IORT_SMMU_V3_COHACC_OVERRIDE | ACPI_IORT_SMMU_V3_DEVICEID_VALID) + +#define RDN2_DMA0_BASE 0x1090000000 +#define RDN2_DMA1_BASE 0x10B0000000 +/* Virtio block device */ +#define RDN2_AHCI_BASE 0x0C130000 +#define RDN2_AHCI_INT 458 + +/* Virtio net */ +#define RDN2_VNET_BASE 0x0C150000 +#define RDN2_VNET_INT 460 + +/* Arm Dual-Timer Module */ +#define RDN2_DUAL_TIMER 0x0C110000 +#define RDN2_DUAL_TIMER_INT 486 + +#define RDN2_GPIO0 0x0C1D0000 +#define RDN2_GPIO0_INT 392 + +#define RDN2_EHCI_BASE 0x60110000 + +#define RDN2_PCIE_MMIO_BASE 0x60000000 +#define RDN2_PCIE_MMIO_LIMIT 0x7fffffff +#define RDN2_PCIE_MMIO_SIZE 0x20000000 +#define RDN2_PCIE_ECAM_BASE 0x1010000000 +#define RDN2_PCIE_ECAM_LIMIT 0x101FFFFFFF +#define RDN2_PCIE_ECAM_SIZE 0x10000000 +#define RDN2_PCIE_MMIO_HIGH_BASE 0x4000000000 +#define RDN2_PCIE_MMIO_HIGH_LIMIT 0x807fffffff +#define RDN2_PCIE_MMIO_HIGH_SIZE 0x4080000000 diff --git a/src/mainboard/arm/rdn2/mainboard.c b/src/mainboard/arm/rdn2/mainboard.c new file mode 100644 index 00000000000..d5f7df4e7ba --- /dev/null +++ b/src/mainboard/arm/rdn2/mainboard.c @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "chip.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static size_t ram_size(void) +{ + return (size_t)cbmem_top() - (uintptr_t)_dram; +} + +static size_t ram2_size(void) +{ + return (size_t)probe_ramsize((uintptr_t)RDN2_DRAM2_BASE, RDN2_DRAM2_SIZE) * MiB; +} + +static void mainboard_init(void *chip_info) +{ + mmu_config_range(_dram, ram_size(), MA_MEM | MA_RW); + mmu_config_range((void *)RDN2_DRAM2_BASE, ram2_size(), MA_MEM | MA_RW); +} + +DECLARE_REGION(fdt_pointer) + +void smbios_cpu_get_core_counts(u16 *core_count, u16 *thread_count) +{ + *core_count = 0; + struct device *dev = NULL; + while ((dev = dev_find_path(dev, DEVICE_PATH_GICC_V3))) + *core_count += 1; + + *thread_count = 1; +} + + +static void rdn2_aarch64_init(struct device *dev) +{ + struct memory_info *mem_info; + + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) + return; + + memset(mem_info, 0, sizeof(*mem_info)); + + mem_info->ecc_type = MEMORY_ARRAY_ECC_UNKNOWN; + mem_info->max_capacity_mib = 0x800000; + mem_info->number_of_devices = mem_info->dimm_cnt = 1; + + mem_info->dimm[0].dimm_size = (ram_size() + ram2_size()) / MiB; + mem_info->dimm[0].ddr_type = MEMORY_TYPE_DRAM; + mem_info->dimm[0].ddr_frequency = 0; + mem_info->dimm[0].channel_num = mem_info->dimm[0].dimm_num = 0; + mem_info->dimm[0].bank_locator = 0; + + mem_info->dimm[0].bus_width = 0x03; // 64-bit, no parity + mem_info->dimm[0].vdd_voltage = 0; + mem_info->dimm[0].max_speed_mts = mem_info->dimm[0].configured_speed_mts = 0; +} + +static unsigned long mb_write_acpi_tables(const struct device *dev, unsigned long current, + acpi_rsdp_t *rsdp) +{ + printk(BIOS_DEBUG, "ACPI: * DBG2\n"); + return acpi_pl011_write_dbg2_uart(rsdp, current, RDN2_UART_NS_BASE, "\\_SB.COM0"); +} + + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = rdn2_aarch64_init; + dev->ops->write_acpi_tables = mb_write_acpi_tables; +} + + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; + +struct chip_operations mainboard_arm_rdn2_ops = { }; + +static void rdn2_aarch64_domain_read_resources(struct device *dev) +{ + struct resource *res; + int index = 0; + + /* Initialize the system-wide I/O space constraints. */ + res = new_resource(dev, index++); + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; + + /* Initialize the system-wide memory resources constraints. */ + res = new_resource(dev, index++); + res->base = RDN2_PCIE_MMIO_BASE; + res->limit = RDN2_PCIE_MMIO_LIMIT; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + + res = new_resource(dev, index++); + res->base = RDN2_PCIE_MMIO_HIGH_BASE; + res->limit = RDN2_PCIE_MMIO_HIGH_LIMIT; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + + ram_range(dev, index++, (uintptr_t)_dram, ram_size()); + reserved_ram_range(dev, index++, (uintptr_t)RDN2_SECMEM_BASE, RDN2_SECMEM_SIZE); + + ram_range(dev, index++, (uintptr_t)RDN2_DRAM2_BASE, ram2_size()); + + mmio_range(dev, index++, RDN2_FLASH_BASE, RDN2_FLASH_SIZE); +} + +struct device_operations rdn2_aarch64_pci_domain_ops = { + .read_resources = rdn2_aarch64_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_host_bridge_scan_bus, +}; + +static void rdn2_fill_cpu_ssdt(const struct device *dev) +{ + acpigen_write_processor_device(dev->path.gicc_v3.mpidr); + acpigen_write_processor_device_end(); +} + +struct device_operations rdn2_cpu_ops = { + .acpi_fill_ssdt = rdn2_fill_cpu_ssdt, +}; + +static void rdn2_aarch64_scan_bus(struct device *dev) +{ + u16 i = 0; + struct bus *bus = alloc_bus(dev); + + for (i = 0; i < 16; i++) { + printk(BIOS_DEBUG, "Allocating CPU %d\n", i); + struct device_path devpath = { .type = DEVICE_PATH_GICC_V3, + .gicc_v3 = { .mpidr = i << 16, + .vgic_mi = 0x19, + .pi_gsiv = 0x17, }, + }; + struct device *cpu = alloc_dev(bus, &devpath); + assert(cpu); + cpu->ops = &rdn2_cpu_ops; + } + +} + +struct device_operations rdn2_aarch64_cpu_ops = { + .scan_bus = rdn2_aarch64_scan_bus, +}; diff --git a/src/mainboard/arm/rdn2/media.c b/src/mainboard/arm/rdn2/media.c new file mode 100644 index 00000000000..cf6ab06789b --- /dev/null +++ b/src/mainboard/arm/rdn2/media.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +/* Maps directly to NOR flash up to ROM size. */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT((void *)RDN2_FLASH_BASE, RDN2_FLASH_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/arm/rdn2/memlayout.ld b/src/mainboard/arm/rdn2/memlayout.ld new file mode 100644 index 00000000000..de7aad5086a --- /dev/null +++ b/src/mainboard/arm/rdn2/memlayout.ld @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +/* + * Memory map for Neoverse N2 + * See Technical Reference: Table 5-2: FVP board peripherals + */ +SECTIONS +{ + REGION(flash, 0x8000000, CONFIG_ROM_SIZE, 8) + + REGION(dev_mem, 0x0c010000, 2M, 8) + DRAM_START(0x80000000) + BOOTBLOCK(0xe0000000, 64K) + STACK(0xe0010000, 64K) + CBFS_MCACHE(0xe0020000, 8K) + FMAP_CACHE(0xe0022000 , 4K) + TIMESTAMP(0xe0023000, 4K) + ROMSTAGE(0xe0024000, 128K) + TTB(0xe0060000, 128K) + RAMSTAGE(0xe00a0000, 16M) + REGION(fdt_pointer, 0xe10a0000, ARCH_POINTER_ALIGN_SIZE, ARCH_POINTER_ALIGN_SIZE) + + POSTRAM_CBFS_CACHE(0xe11f0000, 1M) +} diff --git a/src/mainboard/arm/rdn2/pptt.c b/src/mainboard/arm/rdn2/pptt.c new file mode 100644 index 00000000000..ca06cc8c942 --- /dev/null +++ b/src/mainboard/arm/rdn2/pptt.c @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define CACHE_NODE_FLAGS 0xd7 // everything valid except, write-policy and allocation type +#define CLUSTER_FLAGS 0x11 // physical package, ID invalid, no thread, no leaf, identical impl. +#define CORE_FLAGS 0x0a // no physical package, ID valid, no thread, leaf. +#define CORE_FLAGS_1 0x12 // no physical package, ID valid, no thread, identical i. + +/* + * L2 cache (LLC) + */ +struct pptt_cache l2 = { + + .next_level = NULL +}; + +/* + * L1D cache + */ +struct pptt_cache l1d = { + .next_level = &l2 +}; + +/* + * L1I cache + */ +struct pptt_cache l1i = { + //.sibling = &l1d, + .next_level = &l2 +}; + +/* + * private resources of a cpu core. Same for + * each core, thus we can reuse this struture + * instead of creating it dynamically. + */ +struct pptt_cpu_resources core_resources = { + .cache = &l1i, +}; + +struct pptt_topology root_topology = { + + .flags.raw = CLUSTER_FLAGS, + .resources = NULL, + .sibling = NULL, + + .child = &(struct pptt_topology) { + + .processor_id = 0, + .flags.raw = CORE_FLAGS_1, + + .resources = NULL, + + .child = &(struct pptt_topology) { + .processor_id = 0, + .flags.raw = CORE_FLAGS, + + .resources = &(struct pptt_cpu_resources) { + + .cache = &l1i, + + }, + + .sibling = NULL, + .child = NULL, + }, + .sibling = NULL, // updated in runtime + } +}; + +/* --- Helpers --- */ + +static u8 cache_attributes(const enum cache_type type) +{ + /* + * 'write-policy' and 'allocation type' currently + * unsupported. cache flags set accordingly. + * + * maybe a todo for the future. + */ + + u8 attr = 0x0; + + if (type == CACHE_INSTRUCTION) + attr |= (0x1 << 2); + else if (type == CACHE_UNIFIED) + attr |= (0x1 << 3); + + return attr; +} + +/* --- ACPI hook --- */ + +struct pptt_topology *acpi_get_pptt_topology(void) +{ + struct cache_info info; + + /* Dump Cache info */ + for (int cache_level = CACHE_L1; cache_level <= CACHE_L7; cache_level++) { + int cache_type = cpu_get_cache_type(cache_level); + if (cache_type == NO_CACHE) + continue; + + if (cache_type == CACHE_SEPARATE) { + printk(BIOS_DEBUG, "Fetching cache info for: level:%d, type:%d\n", + cache_level, cache_type); + cpu_get_cache_info(cache_level, cache_type, &info); + printk(BIOS_DEBUG, "Size: %lld, associativity: %lld\n", info.size, + info.associativity); + + cache_type = CACHE_INSTRUCTION; + + printk(BIOS_DEBUG, "Fetching cache info for: level:%d, type:%d\n", + cache_level, cache_type); + cpu_get_cache_info(cache_level, cache_type, &info); + printk(BIOS_DEBUG, "Size: %lld, associativity: %lld\n", info.size, + info.associativity); + + cache_type = CACHE_DATA; + } + + printk(BIOS_DEBUG, "Fetching cache info for: level:%d, type:%d\n", cache_level, + cache_type); + cpu_get_cache_info(cache_level, cache_type, &info); + printk(BIOS_DEBUG, "Size: %lld, associativity: %lld\n", info.size, + info.associativity); + } + + /* update cache information (L1I) */ + + cpu_get_cache_info(CACHE_L1, CACHE_INSTRUCTION, &info); + + l1i.size = info.size; + l1i.associativity = info.associativity; + l1i.numsets = info.numsets; + l1i.line_size = info.line_bytes; + l1i.attributes = cache_attributes(CACHE_INSTRUCTION); + l1i.flags.raw = CACHE_NODE_FLAGS | 0xff; + + /* update cache information (L1D) */ + + cpu_get_cache_info(CACHE_L1, CACHE_DATA, &info); + + l1d.size = info.size; + l1d.associativity = info.associativity; + l1d.numsets = info.numsets; + l1d.line_size = info.line_bytes; + l1d.attributes = cache_attributes(CACHE_DATA) | (0x2); + l1d.flags.raw = CACHE_NODE_FLAGS | 0xff; + + /* update cache information (L2) */ + + cpu_get_cache_info(CACHE_L2, CACHE_UNIFIED, &info); + + l2.size = info.size; + l2.associativity = info.associativity; + l2.numsets = info.numsets; + l2.line_size = info.line_bytes; + l2.attributes = cache_attributes(CACHE_UNIFIED) | (0x2); + l2.flags.raw = CACHE_NODE_FLAGS | 0xff; + + /* add secondary CPUs */ + + u32 cpu_id = 0; + + struct device *dev = NULL; + struct pptt_topology **it = &root_topology.child->sibling; + struct pptt_topology **sibling; + + while ((dev = dev_find_path(dev, DEVICE_PATH_GICC_V3))) { + if (cpu_id == 0) { + + cpu_id += 1; + continue; + } + + if ((*it = malloc(sizeof(struct pptt_topology))) == NULL) { + + printk(BIOS_ERR, "Could not allocate pptt structure!\n"); + break; + } + + memset(*it, 0, sizeof(struct pptt_topology)); + + (*it)->processor_id = cpu_id; + (*it)->flags.raw = CORE_FLAGS_1; + (*it)->resources = NULL; + + //sibling = (*it)->sibling; + sibling = &(*it)->sibling; + + it = &(*it)->child; + + if ((*it = malloc(sizeof(struct pptt_topology))) == NULL) { + + printk(BIOS_ERR, "Could not allocate pptt structure!\n"); + break; + } + + memset(*it, 0, sizeof(struct pptt_topology)); + + (*it)->processor_id = cpu_id; + (*it)->flags.raw = CORE_FLAGS; + (*it)->resources = &core_resources; + + //it = &(*it)->sibling; + it = sibling; + + cpu_id += 1; + } + + return &root_topology; +} diff --git a/src/mainboard/arm/rdn2/uart.c b/src/mainboard/arm/rdn2/uart.c new file mode 100644 index 00000000000..1b872056d0c --- /dev/null +++ b/src/mainboard/arm/rdn2/uart.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +uintptr_t uart_platform_base(unsigned int idx) +{ + return RDN2_UART_NS_BASE; +} From ed73b3f2f783a79eae4f7385f9f843043f3158fb Mon Sep 17 00:00:00 2001 From: Daniel Maslowski Date: Mon, 14 Oct 2024 22:44:51 +0200 Subject: [PATCH 10/15] util/amdtools: update K8 BKDG URL The document was moved. The current URL gives a 404. Change-Id: If6ca74a8bf47382100da048667976958961b9320 Signed-off-by: Daniel Maslowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/84764 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Nicholas Chin --- util/amdtools/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/amdtools/README.md b/util/amdtools/README.md index 0e48d89fdcb..cb84cbc5fd0 100644 --- a/util/amdtools/README.md +++ b/util/amdtools/README.md @@ -15,7 +15,7 @@ Before you can use them, you need to massage the relevant BKDG sections into useable data. Here's how. 1. First, you need to acquire a copy of the K8 BKDG. Go here: - Rev F: http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf + Rev F: https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/programmer-references/32559.pdf 2. Make sure pdftotext is installed (it's in the poppler-utils package on Debian/Ubuntu). 3. Run the bkdg through pdftotext: From 7d569573958f29d1aef80f023e92ac40ad9c9f86 Mon Sep 17 00:00:00 2001 From: Kun Liu Date: Sun, 13 Oct 2024 12:38:10 +0800 Subject: [PATCH 11/15] mb/google/brya: Create telith variant Create the telith variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0) BUG=372506691 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_TELITH Change-Id: I4971b9691d3dd293ca640795967c36472afef9c9 Signed-off-by: Kun Liu Reviewed-on: https://review.coreboot.org/c/coreboot/+/84759 Reviewed-by: Dinesh Gehlot Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Jian Tong Reviewed-by: Eric Lai --- src/mainboard/google/brya/Kconfig | 14 + src/mainboard/google/brya/Kconfig.name | 3 + .../google/brya/variants/telith/Makefile.mk | 8 + .../google/brya/variants/telith/gpio.c | 125 ++++ .../brya/variants/telith/include/variant/ec.h | 8 + .../variants/telith/include/variant/gpio.h | 8 + .../brya/variants/telith/memory/Makefile.mk | 12 + .../telith/memory/dram_id.generated.txt | 19 + .../variants/telith/memory/mem_parts_used.txt | 24 + .../brya/variants/telith/overridetree.cb | 537 ++++++++++++++++++ .../google/brya/variants/telith/variant.c | 56 ++ 11 files changed, 814 insertions(+) create mode 100644 src/mainboard/google/brya/variants/telith/Makefile.mk create mode 100644 src/mainboard/google/brya/variants/telith/gpio.c create mode 100644 src/mainboard/google/brya/variants/telith/include/variant/ec.h create mode 100644 src/mainboard/google/brya/variants/telith/include/variant/gpio.h create mode 100644 src/mainboard/google/brya/variants/telith/memory/Makefile.mk create mode 100644 src/mainboard/google/brya/variants/telith/memory/dram_id.generated.txt create mode 100644 src/mainboard/google/brya/variants/telith/memory/mem_parts_used.txt create mode 100644 src/mainboard/google/brya/variants/telith/overridetree.cb create mode 100644 src/mainboard/google/brya/variants/telith/variant.c diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 4f49df25737..d840426c766 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -542,6 +542,16 @@ config BOARD_GOOGLE_TELIKS select HAVE_WWAN_POWER_SEQUENCE select SOC_INTEL_TWINLAKE +config BOARD_GOOGLE_TELITH + select BOARD_GOOGLE_BASEBOARD_NISSA + select BOARD_ROMSIZE_KB_16384 + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_BAYHUB_LV2 + select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_GFX_GENERIC + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_TWINLAKE + config BOARD_GOOGLE_TEREID select BOARD_GOOGLE_BASEBOARD_NISSA select BOARD_ROMSIZE_KB_32768 @@ -734,6 +744,7 @@ config DRIVER_TPM_I2C_BUS default 0x0 if BOARD_GOOGLE_YAVIKS default 0x0 if BOARD_GOOGLE_YAVILLA default 0x1 if BOARD_GOOGLE_ZYDRON + default 0x0 if BOARD_GOOGLE_TELITH config DRIVER_TPM_I2C_ADDR hex @@ -808,6 +819,7 @@ config TPM_TIS_ACPI_INTERRUPT default 13 if BOARD_GOOGLE_YAVIKS default 13 if BOARD_GOOGLE_YAVILLA default 13 if BOARD_GOOGLE_ZYDRON + default 13 if BOARD_GOOGLE_TELITH config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -889,6 +901,7 @@ config MAINBOARD_PART_NUMBER default "Yavista" if BOARD_GOOGLE_YAVISTA default "Zydron" if BOARD_GOOGLE_ZYDRON default "Pujjoga" if BOARD_GOOGLE_PUJJOGA + default "Telith" if BOARD_GOOGLE_TELITH config VARIANT_DIR default "agah" if BOARD_GOOGLE_AGAH @@ -956,6 +969,7 @@ config VARIANT_DIR default "zydron" if BOARD_GOOGLE_ZYDRON default "yavista" if BOARD_GOOGLE_YAVISTA default "pujjoga" if BOARD_GOOGLE_PUJJOGA + default "telith" if BOARD_GOOGLE_TELITH config VBOOT select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 6167976ef60..b263642968d 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -196,3 +196,6 @@ config BOARD_GOOGLE_PUJJOGA config BOARD_GOOGLE_ORISA bool "-> Orisa" + +config BOARD_GOOGLE_TELITH + bool "-> Telith" diff --git a/src/mainboard/google/brya/variants/telith/Makefile.mk b/src/mainboard/google/brya/variants/telith/Makefile.mk new file mode 100644 index 00000000000..f41cdfdb8a6 --- /dev/null +++ b/src/mainboard/google/brya/variants/telith/Makefile.mk @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/telith/gpio.c b/src/mainboard/google/brya/variants/telith/gpio.c new file mode 100644 index 00000000000..7570d51ca38 --- /dev/null +++ b/src/mainboard/google/brya/variants/telith/gpio.c @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A11 : GPP_A11 ==> EN_SPK_PA */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), + /* A18 : NC ==> HDMI_HPD_SRC*/ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG), + /* A21 : GPP_A21 ==> NC */ + PAD_NC_LOCK(GPP_A21, NONE, LOCK_CONFIG), + /* A22 : GPP_A22 ==> NC */ + PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG), + + /* B5 : I2C2_SDA ==> MIPI_WCAM_SDA */ + PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG), + /* B6 : I2C2_SCL ==> MIPI_WCAM_SCL */ + PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG), + + /* B11 : NC ==> EN_PP3300_WLAN_X*/ + PAD_CFG_GPO(GPP_B11, 0, DEEP), + + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), + /* D13 : NC ==> EN_PP1800_WCAM_X */ + PAD_CFG_GPO_LOCK(GPP_D13, 1, LOCK_CONFIG), + + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG), + /* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */ + PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), + + /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */ + PAD_CFG_GPI_SCI_HIGH(GPP_F15, NONE, PLTRST, EDGE_BOTH), + /* F18 : THC1_SPI2_INT# ==> NC */ + PAD_NC(GPP_F18, NONE), + /* F23 : V1P05_CTRL ==> NC*/ + PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG), + + /* H8 : CNV_MFUART2_RXD ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : CNV_MFUART2_TXD ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H12 : UART0_RTS# ==> NC*/ + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), + /* H13 : UART0_CTS# ==> NC */ + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), + /* H15 : DDPB_CTRLCLK ==> HDMI_DDC_SCL */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> HDMI_DDC_SDA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* R6 : DMIC_CLK_A_1A ==> NC */ + PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG), + /* R7 : DMIC_DATA_1A ==> NC */ + PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG), + + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ + /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_C1, 1, DEEP), + + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + + + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/telith/include/variant/ec.h b/src/mainboard/google/brya/variants/telith/include/variant/ec.h new file mode 100644 index 00000000000..7a2a6ff8b77 --- /dev/null +++ b/src/mainboard/google/brya/variants/telith/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/telith/include/variant/gpio.h b/src/mainboard/google/brya/variants/telith/include/variant/gpio.h new file mode 100644 index 00000000000..c4fe342621e --- /dev/null +++ b/src/mainboard/google/brya/variants/telith/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/telith/memory/Makefile.mk b/src/mainboard/google/brya/variants/telith/memory/Makefile.mk new file mode 100644 index 00000000000..3b7dc39124d --- /dev/null +++ b/src/mainboard/google/brya/variants/telith/memory/Makefile.mk @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/teliks/memory src/mainboard/google/brya/variants/teliks/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = H9JCNNNCP3MLYR-N6E, MT62F1G32D4DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-4.hex # ID = 2(0b0010) Parts = H9JCNNNFA5MLYR-N6E, MT62F2G32D8DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 3(0b0011) Parts = K3KL6L60GM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 4(0b0100) Parts = MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT, H58G56BK7BX068 +SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 5(0b0101) Parts = MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT, H58G66BK7BX067 diff --git a/src/mainboard/google/brya/variants/telith/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/telith/memory/dram_id.generated.txt new file mode 100644 index 00000000000..773f11b6768 --- /dev/null +++ b/src/mainboard/google/brya/variants/telith/memory/dram_id.generated.txt @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/teliks/memory src/mainboard/google/brya/variants/teliks/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) +H9JCNNNBK3MLYR-N6E 0 (0000) +H9JCNNNCP3MLYR-N6E 1 (0001) +MT62F1G32D4DR-031 WT:B 1 (0001) +H9JCNNNFA5MLYR-N6E 2 (0010) +MT62F2G32D8DR-031 WT:B 2 (0010) +K3KL6L60GM-MGCT 3 (0011) +MT62F1G32D2DS-026 WT:B 4 (0100) +K3KL8L80CM-MGCT 4 (0100) +H58G56BK7BX068 4 (0100) +MT62F2G32D4DS-026 WT:B 5 (0101) +K3KL9L90CM-MGCT 5 (0101) +H58G66BK7BX067 5 (0101) diff --git a/src/mainboard/google/brya/variants/telith/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/telith/memory/mem_parts_used.txt new file mode 100644 index 00000000000..8aee4de40e5 --- /dev/null +++ b/src/mainboard/google/brya/variants/telith/memory/mem_parts_used.txt @@ -0,0 +1,24 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +MT62F512M32D2DR-031 WT:B +H9JCNNNBK3MLYR-N6E +H9JCNNNCP3MLYR-N6E +MT62F1G32D4DR-031 WT:B +H9JCNNNFA5MLYR-N6E +MT62F2G32D8DR-031 WT:B +K3KL6L60GM-MGCT +MT62F1G32D2DS-026 WT:B +K3KL8L80CM-MGCT +H58G56BK7BX068 +MT62F2G32D4DS-026 WT:B +K3KL9L90CM-MGCT +H58G66BK7BX067 diff --git a/src/mainboard/google/brya/variants/telith/overridetree.cb b/src/mainboard/google/brya/variants/telith/overridetree.cb new file mode 100644 index 00000000000..6ed58f7226c --- /dev/null +++ b/src/mainboard/google/brya/variants/telith/overridetree.cb @@ -0,0 +1,537 @@ +fw_config + field WIFI 8 9 + option UNKNOWN 0 + option WIFI_6_7921 1 + option WIFI_6E 2 + option WIFI_6_8852 3 + end + field CAMERA 10 11 + option UF_720P_WF 0 + option UF_1080P 1 + option UF_720P 2 + option UF_1080P_WF 3 + end +end + +chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004C" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0100b + # Bit0 set to "0" indicates has retimer on USBC Port0, on the DB. + # Bit2 set to "1" indicates no retimer on USBC Port1, on the MB. + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "5" + + register "typec_aux_bias_pads[0]" = "{ + .pad_auxp_dc = GPP_A19, + .pad_auxn_dc = GPP_A20 + }" + + register "typec_aux_bias_pads[1]" = "{ + .pad_auxp_dc = GPP_E22, + .pad_auxn_dc = GPP_E23 + }" + + # FIVR configurations for teliks are disabled since the board doesn't have V1p05 and Vnn + # bypass rails implemented. + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 0, + }" + + # Enable the Cnvi BT Audio Offload + register "cnvi_bt_audio_offload" = "1" + + # Intel Common SoC Config + #+-------------+------------------------------+ + #| Field | Value | + #+-------------+------------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C2 | Sub-board(PSensor)/WCAM | + #| I2C3 | Audio | + #| I2C5 | Trackpad | + #+-------------+------------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 160, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 152, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + # Power limit config + register "power_limits_config[ADL_N_041_6W_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 25, + .tdp_pl4 = 78, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""CPU_VR"" + register "options.tsr[1].desc" = ""CPU"" + register "options.tsr[2].desc" = ""Ambient"" + register "options.tsr[3].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 6000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200 + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "4" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + # Internal panel on the first port of the graphics chip + register "device[0].type" = "panel" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) for port C1 + register "device[3].name" = ""DD03"" + register "device[3].use_pld" = "true" + register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device generic 0 on end + end + end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" + register "cio2_prt[0]" = "1" + device generic 0 on + probe CAMERA UF_720P_WF + probe CAMERA UF_1080P_WF + end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ILTK0001"" + register "generic.desc" = ""ILITEK Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "200" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "200" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 41 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)" + register "key.wake_gpe" = "GPE0_DW2_15" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_ANY" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end + device ref i2c2 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTIDB10"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 13b10 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "4" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "560 * MHz" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1200_WCAM_X + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on + probe CAMERA UF_720P_WF + probe CAMERA UF_1080P_WF + end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "2" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW9714 VCM "" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "vcm_compat" = ""dongwoon,dw9714"" + + register "has_power_resource" = "1" + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_AFVDD + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 0C on + probe CAMERA UF_720P_WF + probe CAMERA UF_1080P_WF + end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""GT24P64E"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "nvm_size" = "0x2000" + register "nvm_pagesize" = "1" + register "nvm_readonly" = "1" + register "nvm_width" = "0x10" + register "nvm_compat" = ""atmel,24c64"" + + device i2c 50 on + probe CAMERA UF_720P_WF + probe CAMERA UF_1080P_WF + end + end + end + device ref i2c3 on + chip drivers/i2c/rt5645 + register "hid" = ""10EC5650"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5650"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + register "cbj_sleeve" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "jd_mode" = "2" + device i2c 1a on end + end + end + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""PRIMAX Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + register "add_acpi_dma_property" = "true" + device generic 0 on + probe WIFI WIFI_6E + end + end + end + device ref pcie_rp4 on + # PCIe 4 WLAN + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on + probe WIFI WIFI_6_7921 + probe WIFI WIFI_6_8852 + end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C MB (7.5 inch) + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C DB (7.1 inch) + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MB (6.4 inch) + register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch) + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch) + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB)) + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 UFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""PCIe Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on + probe WIFI WIFI_6_7921 + probe WIFI WIFI_6_8852 + end + end + chip drivers/usb/acpi + register "desc" = ""CNVi Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on + probe WIFI WIFI_6E + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WLAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port4 on end + end + end + end + end + device ref pcie_rp7 off end # SDCard + device ref hda on + chip drivers/sof + register "spkr_tplg" = "rt5650_sp" + register "jack_tplg" = "rt5650_hp" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/telith/variant.c b/src/mainboard/google/brya/variants/telith/variant.c new file mode 100644 index 00000000000..fbfe76cf755 --- /dev/null +++ b/src/mainboard/google/brya/variants/telith/variant.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +/* Per-pipe DDI Function Control 2 */ +#define TRANS_DDI_FUNC_CTL2_A 0x60404 +#define TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS (3 << 6) + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); +} + +static const struct pad_config wifi_pcie_enable_pad[] = { + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), + /* B11 : NC ==> EN_PP3300_WLAN_X*/ + PAD_CFG_GPO(GPP_B11, 1, DEEP), +}; + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + if (!fw_config_probe(FW_CONFIG(WIFI, WIFI_6E))) { + printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n"); + config->cnvi_bt_core = false; + printk(BIOS_INFO, "CNVi bluetooth audio offload disabled by fw_config\n"); + config->cnvi_bt_audio_offload = false; + } +} + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_6_7921)) + || fw_config_probe(FW_CONFIG(WIFI, WIFI_6_8852))) { + printk(BIOS_INFO, "Enable PCie based Wifi GPIO pins.\n"); + gpio_padbased_override(padbased_table, wifi_pcie_enable_pad, + ARRAY_SIZE(wifi_pcie_enable_pad)); + } +} + +void variant_finalize(void) +{ + /* + * Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login screen, + * it is because it inserts 12 blank frames if it receives the unmute in VB-ID. + * + * Always override the mute in VB-ID to avoid Tcon EC detected the + * audiomute_flag change. + */ + graphics_gtt_rmw(TRANS_DDI_FUNC_CTL2_A, ~TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS, + TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS); +} From dd1ca85dd3e43771b91880c9effab31f48569dff Mon Sep 17 00:00:00 2001 From: Cliff Huang Date: Thu, 10 Oct 2024 00:56:34 -0700 Subject: [PATCH 12/15] mb/google/fatcat: add pre-mem configuration based on fw_config Add the GPIO pad configuration to be performed before memory is set up along with the relevant devices definition. This patch includes: - FW config for pre-mem GPIO PAD configuration - Add overridetree changes used by pre-mem FW config BUG=b:348678529 TEST=Boot on Google Fatcat board. Note this cannot be tested by itself directly. Test with CL:84408, set the proper CBI fw_config bit(s) and check that the corresponding GPIO PADs are configured as expected value accordingly. Signed-off-by: Cliff Huang Change-Id: Iac1f637c21a9818512b224dc4cbe4a75dbc516ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/84718 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Pranava Y N --- src/mainboard/google/fatcat/Kconfig | 1 + src/mainboard/google/fatcat/romstage.c | 15 +- .../baseboard/include/baseboard/variants.h | 1 + .../google/fatcat/variants/fatcat/Makefile.mk | 1 + .../google/fatcat/variants/fatcat/fw_config.c | 108 +++++++ .../fatcat/variants/fatcat/overridetree.cb | 281 +++++++++++++++++- 6 files changed, 405 insertions(+), 2 deletions(-) create mode 100644 src/mainboard/google/fatcat/variants/fatcat/fw_config.c diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 15608212cc6..6d3f4959c7d 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -8,6 +8,7 @@ config BOARD_GOOGLE_FATCAT_COMMON select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_INTEL_PMC select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_WWAN_FM350GL select DRIVERS_SOUNDWIRE_ALC722 select DRIVERS_SPI_ACPI select DUMP_SMBIOS_TYPE17 diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c index 9e41d4660e3..7b56e28e3cc 100644 --- a/src/mainboard/google/fatcat/romstage.c +++ b/src/mainboard/google/fatcat/romstage.c @@ -5,6 +5,17 @@ #include #include +/* + * Placeholder to configure GPIO early from romstage relying on the FW_CONFIG. + * + * If any platform would like to override early GPIOs, they should override from + * the variant directory. + */ +__weak void fw_config_configure_pre_mem_gpio(void) +{ + /* Nothing to do */ +} + void mainboard_memory_init_params(FSPM_UPD *memupd) { const struct pad_config *pads; @@ -14,7 +25,9 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) struct mem_spd spd_info; pads = variant_romstage_gpio_table(&pads_num); - gpio_configure_pads(pads, pads_num); + if (pads_num) + gpio_configure_pads(pads, pads_num); + fw_config_configure_pre_mem_gpio(); memset(&spd_info, 0, sizeof(spd_info)); variant_get_spd_info(&spd_info); diff --git a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h index 27fd8b72e81..581ba5135cf 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h @@ -16,6 +16,7 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_romstage_gpio_table(size_t *num); +void fw_config_configure_pre_mem_gpio(void); void fw_config_gpio_padbased_override(struct pad_config *padbased_table); const struct mb_cfg *variant_memory_params(void); diff --git a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk index 88986e48140..ac6779c1310 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk +++ b/src/mainboard/google/fatcat/variants/fatcat/Makefile.mk @@ -3,5 +3,6 @@ bootblock-y += gpio.c romstage-y += gpio.c romstage-y += memory.c +romstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c ramstage-y += variant.c diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c new file mode 100644 index 00000000000..0e34c132011 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define GPIO_CONFIGURE_PADS(a) gpio_configure_pads(a, ARRAY_SIZE(a)) + +static const struct pad_config pre_mem_x1slot_pads[] = { + /* GPP_A08: X1_PCIE_SLOT_PWR_EN */ + PAD_CFG_GPO(GPP_A08, 0, PLTRST), +}; + +/* + * WWAN: power sequence requires three stages: + * step 1: 3.3V power, FCP# (Full Card Power), RST#, and PERST# off + * step 2: deassert FCP# + * step 3: deassert RST# first, and then PERST#. + * NOTE: Since PERST# is gated by platform reset, PERST# deassertion will happen + * at much later time and time between RST# and PERSET# is guaranteed. + */ +static const struct pad_config pre_mem_wwan_pwr_seq1_pads[] = { + /* GPP_H16: WWAN_PWREN */ + PAD_CFG_GPO(GPP_H16, 1, PLTRST), + /* GPP_A09: M.2_WWAN_FCP_OFF_N */ + PAD_CFG_GPO(GPP_A09, 0, PLTRST), + /* GPP_B20: M.2_WWAN_RST_N */ + PAD_CFG_GPO(GPP_B20, 0, PLTRST), + /* GPP_D03: M.2_WWAN_PERST_GPIO_N */ + PAD_CFG_GPO(GPP_D03, 0, PLTRST), +}; + +static const struct pad_config pre_mem_wwan_pwr_seq2_pads[] = { + /* GPP_A09: M.2_WWAN_FCP_OFF_N */ + PAD_CFG_GPO(GPP_A09, 1, PLTRST), +}; + +/* gen4 NVME: at the top M.2 slot */ +static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = { + /* GPP_B10: GEN4_SSD_PWREN */ + PAD_CFG_GPO(GPP_B10, 0, PLTRST), +}; + +/* gen5 NVME: at the bottom M.2 slot */ +static const struct pad_config pre_mem_gen5_ssd_pwr_pads[] = { + /* GPP_B16: GEN5_SSD_PWREN */ + PAD_CFG_GPO(GPP_B16, 0, PLTRST), +}; + +/* camera1: WFC */ +static const struct pad_config pre_mem_wfc_camera_pwr_pads[] = { + /* GPP_C05: CRD1_PWREN */ + PAD_CFG_GPO(GPP_C05, 0, PLTRST), +}; + +/* camera2: UFC */ +static const struct pad_config pre_mem_ufc_camera_pwr_pads[] = { + /* GPP_C08: CRD2_PWREN */ + PAD_CFG_GPO(GPP_C08, 0, PLTRST), +}; + +void fw_config_configure_pre_mem_gpio(void) +{ + if (fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_PCIE)) || + fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_USB))) { + GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads); + } + + if (fw_config_probe(FW_CONFIG(WFC, WFC_MIPI))) { + GPIO_CONFIGURE_PADS(pre_mem_wfc_camera_pwr_pads); + } + + if (fw_config_probe(FW_CONFIG(UFC, UFC_MIPI))) { + GPIO_CONFIGURE_PADS(pre_mem_ufc_camera_pwr_pads); + } + + if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) { + GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads); + } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) { + GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads); + } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) { + /* TODO */ + } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) { + GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads); + GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads); + /* TODO for UFS */ + } + + if (fw_config_probe(FW_CONFIG(SD, SD_GENSYS)) || + fw_config_probe(FW_CONFIG(SD, SD_BAYHUB))) { + GPIO_CONFIGURE_PADS(pre_mem_x1slot_pads); + } + /* + * NOTE: We place WWAN sequence 2 here. According to the WWAN FIBOCOM + * FM350-GL datasheet, the minimum time requirement (Tpr: time between 3.3V + * and FCP#) is '0'. Therefore, it will be fine even though there is no + * GPIO configured for other PADs via fw_config to have the time delay + * introduced in between sequence 1 and 2. Also, FCP# was not the last PAD + * configured in sequence 1. Although the Tpr is '0' in the datasheet, three + * stages are preserved at this time to guarantee the sequence shown in the + * datasheet timing diagram. + */ + if (fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_PCIE)) || + fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_USB))) { + GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq2_pads); + } +} diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index 623a332c7b3..f89bfd8783d 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -65,5 +65,284 @@ fw_config end chip soc/intel/pantherlake - device domain 0 on end + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C1 | Camera(CRD1) | + #| I2C2 | Camera(CRD2) | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{4,2}" + register "cio2_lane_endpoint[0]" = ""^I2C1.CAM0"" + register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1"" + register "cio2_prt[0]" = "0" + register "cio2_prt[1]" = "2" + device generic 0 on end + end + end + + device ref pcie_rp2 on + probe CELLULAR CELLULAR_PCIE + register "pcie_rp[PCIE_RP(2)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)" + register "reset_off_delay_ms" = "20" + register "srcclk_pin" = "5" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "skip_on_off_support" = "true" + register "use_rp_mutex" = "true" + device generic 0 alias rp2_rtd3 on + probe CELLULAR CELLULAR_PCIE + end + end + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A09)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B20)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E02)" + register "add_acpi_dma_property" = "true" + use rp2_rtd3 as rtd3dev + device generic 0 on + probe CELLULAR CELLULAR_PCIE + end + end + end # WWAN + device ref pcie_rp3 on + probe SD SD_GENSYS + probe SD SD_BAYHUB + # Enable PCH PCIE x1 slot using CLK 3 + register "pcie_rp[PCIE_RP(3)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A08)" + register "enable_delay_ms" = "100" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)" + register "reset_delay_ms" = "20" + register "srcclk_pin" = "2" + device generic 0 on + probe SD SD_GENSYS + probe SD SD_BAYHUB + end + end + end # PCIE x1 slot + device ref pcie_rp5 on + probe STORAGE STORAGE_NVME_GEN4 + probe STORAGE STORAGE_UNKNOWN + register "pcie_rp[PCIE_RP(5)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B10)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)" + register "srcclk_pin" = "6" + device generic 0 on + probe STORAGE STORAGE_NVME_GEN4 + probe STORAGE STORAGE_UNKNOWN + end + end + end # Gen4 M.2 SSD + device ref pcie_rp9 on + probe STORAGE STORAGE_NVME_GEN5 + probe STORAGE STORAGE_UNKNOWN + register "pcie_rp[PCIE_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)" + register "srcclk_pin" = "1" + device generic 0 on + probe STORAGE STORAGE_NVME_GEN5 + probe STORAGE STORAGE_UNKNOWN + end + end + end # Gen5 M.2 SSD + + # NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled. + # TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways. + device ref i2c0 on end + device ref i2c1 on + probe WFC WFC_MIPI + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTIDB10"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 13b10 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM1"" + + register "ssdb.lanes_used" = "4" + register "num_freq_entries" = "1" + register "link_freq[0]" = "560000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "0" + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_E10" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on + probe WFC WFC_MIPI + end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM1"" + register "chip_name" = ""DW AF VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on + probe WFC WFC_MIPI + end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "1" + register "acpi_name" = ""NVM1"" + register "chip_name" = ""BRCA016GWZ"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC"" + register "nvm_compat" = ""atmel,24c16"" + + register "nvm_size" = "0x800" + register "nvm_pagesize" = "0x01" + register "nvm_readonly" = "0x01" + register "nvm_width" = "0x08" + + device i2c 50 on + probe WFC WFC_MIPI + end + end + end + device ref i2c2 on + probe UFC UFC_MIPI + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTIDB10"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 13b10 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM1"" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "560000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_E01" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on + probe UFC UFC_MIPI + end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM1"" + register "chip_name" = ""DW AF VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on + probe UFC UFC_MIPI + end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "1" + register "acpi_name" = ""NVM1"" + register "chip_name" = ""BRCA016GWZ"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC"" + register "nvm_compat" = ""atmel,24c16"" + + register "nvm_size" = "0x800" + register "nvm_pagesize" = "0x01" + register "nvm_readonly" = "0x01" + register "nvm_width" = "0x08" + + device i2c 50 on + probe UFC UFC_MIPI + end + end + end + end end From 2626bcf5f886e47f79e5e9f336492ceab680ff48 Mon Sep 17 00:00:00 2001 From: Amanda Huang Date: Wed, 16 Oct 2024 11:03:18 +0800 Subject: [PATCH 13/15] spd/lp5: Add SPD for MT62F2G32D4DS-020 WT:F Add MT62F2G32D4DS-020 WT:F in the memory_parts.json and re-generate the SPD BUG=b:373394046 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: I592cebf972df1e54555561b243eed42af83342e3 Signed-off-by: Amanda Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/84780 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Dtrain Hsu Reviewed-by: Subrata Banik Reviewed-by: Pranava Y N --- spd/lp5/memory_parts.json | 11 +++++++++++ spd/lp5/set-0/parts_spd_manifest.generated.txt | 1 + spd/lp5/set-1/parts_spd_manifest.generated.txt | 1 + 3 files changed, 13 insertions(+) diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json index 70e05e333c7..62428d2695f 100644 --- a/spd/lp5/memory_parts.json +++ b/spd/lp5/memory_parts.json @@ -262,6 +262,17 @@ "speedMbps": 8533, "lp5x": true } + }, + { + "name": "MT62F2G32D4DS-020 WT:F", + "attribs": { + "densityPerDieGb": 16, + "diesPerPackage": 4, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 8533, + "lp5x": true + } } ] } diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt index 0f0d841e1e0..b44fdcce6fc 100644 --- a/spd/lp5/set-0/parts_spd_manifest.generated.txt +++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt @@ -26,3 +26,4 @@ MT62F1G32D2DS-023 WT:B,spd-11.hex MT62F2G32D4DS-023 WT:B,spd-10.hex MT62F1G32D2DS-023 WT:C,spd-11.hex K3KL8L80DM-MGCU,spd-11.hex +MT62F2G32D4DS-020 WT:F,spd-10.hex diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt index 0f0d841e1e0..b44fdcce6fc 100644 --- a/spd/lp5/set-1/parts_spd_manifest.generated.txt +++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt @@ -26,3 +26,4 @@ MT62F1G32D2DS-023 WT:B,spd-11.hex MT62F2G32D4DS-023 WT:B,spd-10.hex MT62F1G32D2DS-023 WT:C,spd-11.hex K3KL8L80DM-MGCU,spd-11.hex +MT62F2G32D4DS-020 WT:F,spd-10.hex From d15069ece2b4d41739d97f27257002578e8161ec Mon Sep 17 00:00:00 2001 From: Ian Feng Date: Tue, 15 Oct 2024 15:39:02 +0800 Subject: [PATCH 14/15] mb/google/fatcat: Create francka variant Create the francka variant of the fatcat reference board. BUG=b:370666276 TEST=util/abuild/abuild -p none -t google/fatcat -x -a make sure the build includes GOOGLE_FRANCKA Change-Id: I372f445f7007d0d33020545a8febbce27c260e41 Signed-off-by: Ian Feng Reviewed-on: https://review.coreboot.org/c/coreboot/+/84769 Reviewed-by: Dtrain Hsu Reviewed-by: Amanda Hwang Reviewed-by: Pranava Y N Tested-by: build bot (Jenkins) --- src/mainboard/google/fatcat/Kconfig | 4 ++++ src/mainboard/google/fatcat/Kconfig.name | 3 +++ .../fatcat/variants/francka/include/variant/ec.h | 8 ++++++++ .../fatcat/variants/francka/include/variant/gpio.h | 8 ++++++++ .../google/fatcat/variants/francka/memory/Makefile.mk | 6 ++++++ .../variants/francka/memory/dram_id.generated.txt | 6 ++++++ .../fatcat/variants/francka/memory/mem_parts_used.txt | 11 +++++++++++ .../google/fatcat/variants/francka/overridetree.cb | 5 +++++ 8 files changed, 51 insertions(+) create mode 100644 src/mainboard/google/fatcat/variants/francka/include/variant/ec.h create mode 100644 src/mainboard/google/fatcat/variants/francka/include/variant/gpio.h create mode 100644 src/mainboard/google/fatcat/variants/francka/memory/Makefile.mk create mode 100644 src/mainboard/google/fatcat/variants/francka/memory/dram_id.generated.txt create mode 100644 src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt create mode 100644 src/mainboard/google/fatcat/variants/francka/overridetree.cb diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 6d3f4959c7d..f47e5a518d6 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -65,6 +65,9 @@ config BOARD_GOOGLE_FATCATNUVO config BOARD_GOOGLE_FATCATITE select BOARD_GOOGLE_MODEL_FATCAT +config BOARD_GOOGLE_FRANCKA + select BOARD_GOOGLE_MODEL_FATCAT + if BOARD_GOOGLE_FATCAT_COMMON config BASEBOARD_DIR @@ -118,6 +121,7 @@ config MAINBOARD_PART_NUMBER default "Fatcat" if BOARD_GOOGLE_FATCAT default "Fatcatite" if BOARD_GOOGLE_FATCATITE default "Fatcatnuvo" if BOARD_GOOGLE_FATCATNUVO + default "Francka" if BOARD_GOOGLE_FRANCKA config MEMORY_SOLDERDOWN def_bool n diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name index 60384128a09..2782d9bf8c8 100644 --- a/src/mainboard/google/fatcat/Kconfig.name +++ b/src/mainboard/google/fatcat/Kconfig.name @@ -10,3 +10,6 @@ config BOARD_GOOGLE_FATCATITE config BOARD_GOOGLE_FATCATNUVO bool "-> Fatcatnuvo" + +config BOARD_GOOGLE_FRANCKA + bool "-> Francka" diff --git a/src/mainboard/google/fatcat/variants/francka/include/variant/ec.h b/src/mainboard/google/fatcat/variants/francka/include/variant/ec.h new file mode 100644 index 00000000000..4fc0622f15a --- /dev/null +++ b/src/mainboard/google/fatcat/variants/francka/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/fatcat/variants/francka/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/francka/include/variant/gpio.h new file mode 100644 index 00000000000..27c87b3fe71 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/francka/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/fatcat/variants/francka/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/francka/memory/Makefile.mk new file mode 100644 index 00000000000..5e16e25b7aa --- /dev/null +++ b/src/mainboard/google/fatcat/variants/francka/memory/Makefile.mk @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/fatcat/memory src/mainboard/google/fatcat/variants/fatcat/memory/mem_parts_used.txt + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/fatcat/variants/francka/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/francka/memory/dram_id.generated.txt new file mode 100644 index 00000000000..cc0bdf18772 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/francka/memory/dram_id.generated.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/fatcat/memory src/mainboard/google/fatcat/variants/fatcat/memory/mem_parts_used.txt + +DRAM Part Name ID to assign diff --git a/src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt new file mode 100644 index 00000000000..2499005682a --- /dev/null +++ b/src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb new file mode 100644 index 00000000000..bfd637ae508 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb @@ -0,0 +1,5 @@ +chip soc/intel/pantherlake + + device domain 0 on + end +end From ae46d6ddaa0e3ffcfb14fe315c70c86d1591656b Mon Sep 17 00:00:00 2001 From: Daniel Peng Date: Wed, 16 Oct 2024 11:03:05 +0800 Subject: [PATCH 15/15] mb/google/nissa/var/glassway: Add convertible and clamshell WIFI SAR FW_CONFIG ids Based on Gallida360 design, we add two new options for WIFI_SAR_ID: - WIFI_SAR_ID_INTEL_CONVERTIBLE 2 - WIFI_SAR_ID_INTEL_CLAMSHELL 3 BUG=b:372354703 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I1b58c4f572d4dbcb269d38485664ddc51e378e5e Signed-off-by: Daniel Peng Reviewed-on: https://review.coreboot.org/c/coreboot/+/84779 Reviewed-by: Paul Menzel Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Jayvik Desai Reviewed-by: Subrata Banik --- src/mainboard/google/brya/variants/glassway/overridetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/brya/variants/glassway/overridetree.cb b/src/mainboard/google/brya/variants/glassway/overridetree.cb index 9e2738eef5e..6c4d15e93f5 100644 --- a/src/mainboard/google/brya/variants/glassway/overridetree.cb +++ b/src/mainboard/google/brya/variants/glassway/overridetree.cb @@ -20,6 +20,8 @@ fw_config field WIFI_SAR_ID 10 12 option WIFI_SAR_ID_0 0 option WIFI_SAR_ID_1 1 + option WIFI_SAR_ID_INTEL_CONVERTIBLE 2 + option WIFI_SAR_ID_INTEL_CLAMSHELL 3 end field STYLUS 14 option STYLUS_ABSENT 0