From 795994e025365c1db81cadf0b8544425de57516f Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Wed, 24 Apr 2024 22:24:51 +0300 Subject: [PATCH 01/11] mainboard/qemu-aarch64: Set CONFIG_PCI_IOBASE to 0x3eff0000 Define the PCI I/O base address necessary to use port I/O functions on the qemu-aarch64 mainboard, so that we can get the VGA display devices working. The config value is from hw/arm/virt.c [1]: [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, [1] https://gitlab.com/qemu-project/qemu/-/blob/v8.2.3/hw/arm/virt.c#L164 Change-Id: I85439ba68740d64f789983b37d9c95f849ce4f72 Signed-off-by: Alper Nebi Yasak Reviewed-on: https://review.coreboot.org/c/coreboot/+/82059 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/emulation/qemu-aarch64/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig index dcb4f237a8d..af689baac32 100644 --- a/src/mainboard/emulation/qemu-aarch64/Kconfig +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -29,6 +29,9 @@ config ECAM_MMCONF_BASE_ADDRESS config ECAM_MMCONF_BUS_NUMBER default 256 +config PCI_IOBASE + default 0x3eff0000 + config MEMLAYOUT_LD_FILE string default "src/mainboard/emulation/qemu-aarch64/memlayout.ld" From 8ae0eff824ecdf72e21901edeed84b6afecbf741 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Fri, 20 Oct 2023 22:59:26 +0300 Subject: [PATCH 02/11] drivers/qemu: Split Cirrus display support from Bochs display support QEMU's Cirrus display device is supported along with the Bochs driver since commit 7905f9254ebc ("qemu: cirrus native video init"). It is no longer the default since QEMU 2.2. The code supporting it can work independently of the Bochs display driver and depends more heavily on port I/O and VGA support code, so split it from that code to make it easier to support the Bochs driver in other architectures. Change-Id: Ic9492b501ed4fdcbda6886db60b1e5348715e667 Signed-off-by: Alper Nebi Yasak Reviewed-on: https://review.coreboot.org/c/coreboot/+/80375 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/drivers/emulation/qemu/Kconfig | 19 ++++++++++++++----- src/drivers/emulation/qemu/Makefile.mk | 2 +- 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/src/drivers/emulation/qemu/Kconfig b/src/drivers/emulation/qemu/Kconfig index 11231ae52ee..0a1a0788b02 100644 --- a/src/drivers/emulation/qemu/Kconfig +++ b/src/drivers/emulation/qemu/Kconfig @@ -11,18 +11,27 @@ config DRIVERS_EMULATION_QEMU_BOCHS help VGA driver for qemu emulated vga cards supporting the bochs dispi interface. This includes - standard vga, vmware svga and qxl. The default - vga (cirrus) is *not* supported, so you have to - pick another one explicitly via 'qemu -vga $card'. + standard vga, vmware svga, and qxl. + +config DRIVERS_EMULATION_QEMU_CIRRUS + bool "cirrus svga driver" + default y + depends on CPU_QEMU_X86 + depends on MAINBOARD_DO_NATIVE_VGA_INIT + select HAVE_VGA_TEXT_FRAMEBUFFER + select HAVE_LINEAR_FRAMEBUFFER + select VGA + help + VGA driver for qemu emulated cirrus svga card. config DRIVERS_EMULATION_QEMU_BOCHS_XRES int "bochs vga xres" default 800 depends on LINEAR_FRAMEBUFFER - depends on DRIVERS_EMULATION_QEMU_BOCHS + depends on DRIVERS_EMULATION_QEMU_BOCHS || DRIVERS_EMULATION_QEMU_CIRRUS config DRIVERS_EMULATION_QEMU_BOCHS_YRES int "bochs vga yres" default 600 depends on LINEAR_FRAMEBUFFER - depends on DRIVERS_EMULATION_QEMU_BOCHS + depends on DRIVERS_EMULATION_QEMU_BOCHS || DRIVERS_EMULATION_QEMU_CIRRUS diff --git a/src/drivers/emulation/qemu/Makefile.mk b/src/drivers/emulation/qemu/Makefile.mk index c9d94bdca0c..619782fb1ed 100644 --- a/src/drivers/emulation/qemu/Makefile.mk +++ b/src/drivers/emulation/qemu/Makefile.mk @@ -6,4 +6,4 @@ postcar-$(CONFIG_CONSOLE_QEMU_DEBUGCON) += qemu_debugcon.c ramstage-$(CONFIG_CONSOLE_QEMU_DEBUGCON) += qemu_debugcon.c ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_BOCHS) += bochs.c -ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_BOCHS) += cirrus.c +ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_CIRRUS) += cirrus.c From 30610597f240f132b99376ce4cb94c665023a2b4 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Thu, 21 Mar 2024 13:46:43 +0300 Subject: [PATCH 03/11] drivers/qemu: Clarify config option name for QEMU display resolution A previous commit splits out Cirrus display support from Bochs display support, with both using the pre-existing Bochs config options for the requested display resolution. Rename these config names to clarify they are not only specific to the Bochs display driver. Change-Id: Ie0a5e75731231bb768d7728867196c9ab5c53a00 Signed-off-by: Alper Nebi Yasak Reviewed-on: https://review.coreboot.org/c/coreboot/+/82060 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/drivers/emulation/qemu/Kconfig | 8 ++++---- src/drivers/emulation/qemu/bochs.c | 4 ++-- src/drivers/emulation/qemu/cirrus.c | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/drivers/emulation/qemu/Kconfig b/src/drivers/emulation/qemu/Kconfig index 0a1a0788b02..5b01ae785bb 100644 --- a/src/drivers/emulation/qemu/Kconfig +++ b/src/drivers/emulation/qemu/Kconfig @@ -24,14 +24,14 @@ config DRIVERS_EMULATION_QEMU_CIRRUS help VGA driver for qemu emulated cirrus svga card. -config DRIVERS_EMULATION_QEMU_BOCHS_XRES - int "bochs vga xres" +config DRIVERS_EMULATION_QEMU_XRES + int "qemu vga xres" default 800 depends on LINEAR_FRAMEBUFFER depends on DRIVERS_EMULATION_QEMU_BOCHS || DRIVERS_EMULATION_QEMU_CIRRUS -config DRIVERS_EMULATION_QEMU_BOCHS_YRES - int "bochs vga yres" +config DRIVERS_EMULATION_QEMU_YRES + int "qemu vga yres" default 600 depends on LINEAR_FRAMEBUFFER depends on DRIVERS_EMULATION_QEMU_BOCHS || DRIVERS_EMULATION_QEMU_CIRRUS diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index 06504309e07..2e0526fa8f2 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -39,8 +39,8 @@ #define VBE_DISPI_LFB_ENABLED 0x40 #define VBE_DISPI_NOCLEARMEM 0x80 -static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES; -static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES; +static int width = CONFIG_DRIVERS_EMULATION_QEMU_XRES; +static int height = CONFIG_DRIVERS_EMULATION_QEMU_YRES; static void bochs_write(struct resource *res, int index, int val) { diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index 1dc8ac9e3ef..6fa9ac2b4a2 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -9,8 +9,8 @@ #include #include -static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES; -static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES; +static int width = CONFIG_DRIVERS_EMULATION_QEMU_XRES; +static int height = CONFIG_DRIVERS_EMULATION_QEMU_YRES; static u32 addr = 0; enum From 91d2f5d5e00564525d91135bb7684e52528b26b0 Mon Sep 17 00:00:00 2001 From: Ronald Claveau Date: Wed, 29 May 2024 23:21:33 +0200 Subject: [PATCH 04/11] mainboard/dell: Add new mainboard XPS 8300 (Sandy Bridge) Mainboard is identified as 0Y2MRG. The version tested is with Nvidia dGPU (gfx 560ti). The flash is a 4MiB Winbond W25Q32BVSIG. It can be flashed internally with flashrom. Add a strap on the service mode pin of the mainboard for internal flash. Tested working: - SeaBIOS - All USB ports - SATA - dGPU - Ethernet - Environment control - GPIOs - S3 Sleep mode - WakeOnLan Change-Id: I7d394794fec580bc7aed3f6396ceb47d4a6fd059 Signed-off-by: Ronald Claveau Reviewed-on: https://review.coreboot.org/c/coreboot/+/83104 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/mainboard/dell/xps_8300/Kconfig | 35 ++++ src/mainboard/dell/xps_8300/Kconfig.name | 4 + src/mainboard/dell/xps_8300/Makefile.mk | 6 + src/mainboard/dell/xps_8300/acpi/ec.asl | 3 + src/mainboard/dell/xps_8300/acpi/platform.asl | 10 + src/mainboard/dell/xps_8300/acpi/superio.asl | 2 + src/mainboard/dell/xps_8300/board_info.txt | 6 + src/mainboard/dell/xps_8300/devicetree.cb | 48 +++++ src/mainboard/dell/xps_8300/dsdt.asl | 29 +++ src/mainboard/dell/xps_8300/early_init.c | 63 ++++++ src/mainboard/dell/xps_8300/gpio.c | 195 ++++++++++++++++++ src/mainboard/dell/xps_8300/hda_verb.c | 9 + src/mainboard/dell/xps_8300/mainboard.c | 16 ++ src/mainboard/dell/xps_8300/smihandler.c | 31 +++ 14 files changed, 457 insertions(+) create mode 100644 src/mainboard/dell/xps_8300/Kconfig create mode 100644 src/mainboard/dell/xps_8300/Kconfig.name create mode 100644 src/mainboard/dell/xps_8300/Makefile.mk create mode 100644 src/mainboard/dell/xps_8300/acpi/ec.asl create mode 100644 src/mainboard/dell/xps_8300/acpi/platform.asl create mode 100644 src/mainboard/dell/xps_8300/acpi/superio.asl create mode 100644 src/mainboard/dell/xps_8300/board_info.txt create mode 100644 src/mainboard/dell/xps_8300/devicetree.cb create mode 100644 src/mainboard/dell/xps_8300/dsdt.asl create mode 100644 src/mainboard/dell/xps_8300/early_init.c create mode 100644 src/mainboard/dell/xps_8300/gpio.c create mode 100644 src/mainboard/dell/xps_8300/hda_verb.c create mode 100644 src/mainboard/dell/xps_8300/mainboard.c create mode 100644 src/mainboard/dell/xps_8300/smihandler.c diff --git a/src/mainboard/dell/xps_8300/Kconfig b/src/mainboard/dell/xps_8300/Kconfig new file mode 100644 index 00000000000..09bd4c84cca --- /dev/null +++ b/src/mainboard/dell/xps_8300/Kconfig @@ -0,0 +1,35 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_DELL_XPS_8300 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + select SUPERIO_ITE_IT8772F + +config MAINBOARD_DIR + default "dell/xps_8300" + +config MAINBOARD_PART_NUMBER + default "XPS 8300" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + default 60 + +config USBDEBUG_HCD_INDEX + default 2 + +config VGA_BIOS_DGPU_ID + default "10de,1082" + +config CBFS_SIZE + default 0x26F000 + +endif diff --git a/src/mainboard/dell/xps_8300/Kconfig.name b/src/mainboard/dell/xps_8300/Kconfig.name new file mode 100644 index 00000000000..5a1eb0a6635 --- /dev/null +++ b/src/mainboard/dell/xps_8300/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_DELL_XPS_8300 + bool "XPS 8300" diff --git a/src/mainboard/dell/xps_8300/Makefile.mk b/src/mainboard/dell/xps_8300/Makefile.mk new file mode 100644 index 00000000000..52521526f4b --- /dev/null +++ b/src/mainboard/dell/xps_8300/Makefile.mk @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c diff --git a/src/mainboard/dell/xps_8300/acpi/ec.asl b/src/mainboard/dell/xps_8300/acpi/ec.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/dell/xps_8300/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/dell/xps_8300/acpi/platform.asl b/src/mainboard/dell/xps_8300/acpi/platform.asl new file mode 100644 index 00000000000..aff432b6f47 --- /dev/null +++ b/src/mainboard/dell/xps_8300/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/dell/xps_8300/acpi/superio.asl b/src/mainboard/dell/xps_8300/acpi/superio.asl new file mode 100644 index 00000000000..8eb9b64e654 --- /dev/null +++ b/src/mainboard/dell/xps_8300/acpi/superio.asl @@ -0,0 +1,2 @@ +/* SPDX-License-Identifier: CC-PDDC */ +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/dell/xps_8300/board_info.txt b/src/mainboard/dell/xps_8300/board_info.txt new file mode 100644 index 00000000000..c37b6406d1b --- /dev/null +++ b/src/mainboard/dell/xps_8300/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/dell/xps_8300/devicetree.cb b/src/mainboard/dell/xps_8300/devicetree.cb new file mode 100644 index 00000000000..233f946b9a6 --- /dev/null +++ b/src/mainboard/dell/xps_8300/devicetree.cb @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + device domain 0x0 on + subsystemid 0x1028 0x04aa inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "0" + register "pcie_port_coalesce" = "1" + + register "usb_port_config" = "{ + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, // FIXME: Unknown current: RCBA(0x3510)=0x3510 + { 1, 0, 2 }, // FIXME: Unknown current: RCBA(0x3514)=0x3514 + { 1, 6, 3 }, + { 1, 6, 3 }, + { 1, 0, 5 }, // FIXME: Unknown current: RCBA(0x3520)=0x3520 + { 1, 6, 5 }, + { 1, 6, 5 }, + { 1, 0, 5 }, // FIXME: Unknown current: RCBA(0x352c)=0x352c + { 1, 6, 6 }, + { 0, 6, 6 }, + }" + + device ref mei1 on end + device ref ehci2 on end + device ref pcie_rp1 on end + device ref pcie_rp4 on end + device ref pcie_rp5 on end + device ref ehci1 on end + device ref lpc on + register "gen1_dec" = "0x003c0a01" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + end + device ref sata1 on + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1f" + end + device ref smbus on end + end + device ref host_bridge on end + device ref peg10 on end + end +end diff --git a/src/mainboard/dell/xps_8300/dsdt.asl b/src/mainboard/dell/xps_8300/dsdt.asl new file mode 100644 index 00000000000..18ede0a05de --- /dev/null +++ b/src/mainboard/dell/xps_8300/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/dell/xps_8300/early_init.c b/src/mainboard/dell/xps_8300/early_init.c new file mode 100644 index 00000000000..1dc95c37495 --- /dev/null +++ b/src/mainboard/dell/xps_8300/early_init.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) +#define MOUSE_DEV PNP_DEV(0x2e, IT8772F_KBCM) +#define EC_DEV PNP_DEV(0x2e, IT8772F_EC) + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0e); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + + /* Set up GPIOs on Super I/O. */ + ite_ac_resume_southbridge(EC_DEV); + ite_reg_write(MOUSE_DEV, 0x30, 0x00); // PS/2 Mouse disable + + ite_reg_write(EC_DEV, 0x30, 0x01); // Environment controller activate + ite_reg_write(EC_DEV, 0x60, 0x0a); // Environment controller MSB Register Base Address + ite_reg_write(EC_DEV, 0x61, 0x30); // Environment controller LSB Register Base Address + ite_reg_write(EC_DEV, 0x62, 0x0a); // PME Direct Access MSB Register Base Address + ite_reg_write(EC_DEV, 0x63, 0x20); // PME Direct Access LSB Register Base Address + + ite_reg_write(GPIO_DEV, 0x25, 0x00); // GPIO Set 1 + ite_reg_write(GPIO_DEV, 0x26, 0xfc); // GPIO Set 2, Enable pin 7 and 8 to GPIO + ite_reg_write(GPIO_DEV, 0x27, 0x00); // GPIO Set 3 + ite_reg_write(GPIO_DEV, 0x28, 0x00); // GPIO Set 4 + ite_reg_write(GPIO_DEV, 0x29, 0x00); // GPIO Set 5 and 6 + ite_reg_write(GPIO_DEV, 0x2a, 0x00); // Special function 1 + ite_reg_write(GPIO_DEV, 0x2b, 0x00); // Special function 2 + ite_reg_write(GPIO_DEV, 0x2c, 0x03); // Special function 3 + ite_reg_write(GPIO_DEV, 0x60, 0x0a); // SMI MSB Register Base Address + ite_reg_write(GPIO_DEV, 0x62, 0x0a); // Simple I/O MSB Register Base Address + ite_reg_write(GPIO_DEV, 0xb0, 0x00); // Pin set 1 polarity registers + ite_reg_write(GPIO_DEV, 0xb1, 0x00); // Pin set 2 polarity registers + ite_reg_write(GPIO_DEV, 0xb2, 0x00); // Pin set 3 polarity registers + ite_reg_write(GPIO_DEV, 0xb3, 0x00); // Pin set 4 polarity registers + ite_reg_write(GPIO_DEV, 0xb4, 0x00); // Pin set 5 polarity registers + ite_reg_write(GPIO_DEV, 0xb8, 0x00); // Pin set 1 int pull-up disable + ite_reg_write(GPIO_DEV, 0xb9, 0x00); // Pin set 1 int pull-up disable + ite_reg_write(GPIO_DEV, 0xba, 0x00); // Pin set 1 int pull-up disable + ite_reg_write(GPIO_DEV, 0xbb, 0x00); // Pin set 1 int pull-up disable + ite_reg_write(GPIO_DEV, 0xbc, 0x00); // Pin set 1 int pull-up disable + ite_reg_write(GPIO_DEV, 0xbd, 0x00); // Pin set 1 int pull-up disable + ite_reg_write(GPIO_DEV, 0xc0, 0x01); // Set Simple I/O functions on SI/O Set 1 + ite_reg_write(GPIO_DEV, 0xc1, 0x0c); // Set Simple I/O functions on SI/O Set 2 + ite_reg_write(GPIO_DEV, 0xc2, 0x00); // Set Simple I/O functions on SI/O Set 3 + ite_reg_write(GPIO_DEV, 0xc3, 0x40); // Set Simple I/O functions on SI/O Set 4 + ite_reg_write(GPIO_DEV, 0xc4, 0x00); // Set Simple I/O functions on SI/O Set 5 + ite_reg_write(GPIO_DEV, 0xc8, 0x01); // Set Simple I/O Output on SI/O Set 1 + ite_reg_write(GPIO_DEV, 0xc9, 0x0c); // Set Simple I/O Output on SI/O Set 2 + ite_reg_write(GPIO_DEV, 0xca, 0x00); // Set Simple I/O Output on SI/O Set 3 + ite_reg_write(GPIO_DEV, 0xcb, 0x40); // Set Simple I/O Output on SI/O Set 4 + ite_reg_write(GPIO_DEV, 0xcc, 0x00); // Set Simple I/O Output on SI/O Set 5 + ite_reg_write(GPIO_DEV, 0xcd, 0x00); // Set Simple I/O Output on SI/O Set 6 + ite_reg_write(GPIO_DEV, 0xe9, 0x07); // GPIO Bus Select Control Register + ite_reg_write(GPIO_DEV, 0xf6, 0x00); // Hardware Monitor Alert Beep Pin Mapping Register +} diff --git a/src/mainboard/dell/xps_8300/gpio.c b/src/mainboard/dell/xps_8300/gpio.c new file mode 100644 index 00000000000..32bbb2b9f7e --- /dev/null +++ b/src/mainboard/dell/xps_8300/gpio.c @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio72 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/xps_8300/hda_verb.c b/src/mainboard/dell/xps_8300/hda_verb.c new file mode 100644 index 00000000000..faa2a8101f2 --- /dev/null +++ b/src/mainboard/dell/xps_8300/hda_verb.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[0] = {}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/xps_8300/mainboard.c b/src/mainboard/dell/xps_8300/mainboard.c new file mode 100644 index 00000000000..8dbd95ef961 --- /dev/null +++ b/src/mainboard/dell/xps_8300/mainboard.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/dell/xps_8300/smihandler.c b/src/mainboard/dell/xps_8300/smihandler.c new file mode 100644 index 00000000000..f126468fa5a --- /dev/null +++ b/src/mainboard/dell/xps_8300/smihandler.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) + +void mainboard_smi_sleep(u8 slp_typ) +{ + switch (slp_typ) { + case ACPI_S3: + ite_set_3vsbsw(GPIO_DEV, true); + ite_delay_pwrgd3(GPIO_DEV); + it8772f_gpio_led( + GPIO_DEV, + 2 /* set */, + 0x02 /* select */, + 0x01 /* polarity */, + 0x01 /* 1 = pullup */, + 0x01 /* output */, + 0x00 /* 1 = Simple IO function */, + SIO_GPIO_BLINK_GPIO22, + IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + break; + default: + break; + } +} From ea6b6acd01708ad88f4c6fefc4fd074790245f48 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 9 Jul 2024 23:00:50 +0530 Subject: [PATCH 05/11] soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibility This patch refactors the handling of CSE CBMEM IDs to enable platforms to choose whether to perform CSE sync operations within coreboot or defer it to the payload. This separation improves code organization, ensuring `cse_lite.c` focuses on coreboot-specific CSE Lite tasks. Now, platforms can select: * `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot * `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` for deferred payload sync This change ensures mutually exclusive options, avoiding unnecessary SPI flash size increases. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/83393 Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- payloads/libpayload/libc/coreboot.c | 2 ++ src/soc/intel/common/block/cse/Makefile.mk | 2 ++ src/soc/intel/common/block/cse/cse_lite.c | 25 ----------------- .../intel/common/block/cse/cse_sync_payload.c | 28 +++++++++++++++++++ 4 files changed, 32 insertions(+), 25 deletions(-) create mode 100644 src/soc/intel/common/block/cse/cse_sync_payload.c diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 78734264732..1d914c5b764 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -262,12 +262,14 @@ static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info) case CBMEM_ID_MEM_CHIP_INFO: info->mem_chip_base = cbmem_entry->address; break; +#if CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD) case CBMEM_ID_CSE_BP_INFO: info->cse_bp_info = cbmem_entry->address; break; case CBMEM_ID_CSE_INFO: info->cse_info = cbmem_entry->address; break; +#endif default: break; } diff --git a/src/soc/intel/common/block/cse/Makefile.mk b/src/soc/intel/common/block/cse/Makefile.mk index 653d67463c0..d41d7354622 100644 --- a/src/soc/intel/common/block/cse/Makefile.mk +++ b/src/soc/intel/common/block/cse/Makefile.mk @@ -11,6 +11,8 @@ smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += telemetry.c +romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD) += cse_sync_payload.c + ifeq ($(CONFIG_STITCH_ME_BIN),y) CSE_BP1_BIN := $(objcse)/cse_bp1.bin diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 4e3a44661d7..6c4fed7c41a 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1542,31 +1542,6 @@ static void store_ish_version(void) } } -static void preram_create_cbmem_cse_info(int is_recovery) -{ - if (!CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) - return; - - /* - * CBMEM_ID_CSE_INFO will be used by the payload to - - * 1. Avoid reading ISH firmware version on consecutive boots. - * 2. Track state of PSR data during CSE downgrade operation. - */ - void *temp = cbmem_add(CBMEM_ID_CSE_INFO, sizeof(struct cse_specific_info)); - if (!temp) - printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_INFO\n"); - - /* - * CBMEM_ID_CSE_BP_INFO will be used by the payload to avoid reading CSE - * boot partition information on consecutive boots. - */ - temp = cbmem_add(CBMEM_ID_CSE_BP_INFO, sizeof(struct get_bp_info_rsp)); - if (!temp) - printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_BP_INFO\n"); -} - -CBMEM_CREATION_HOOK(preram_create_cbmem_cse_info); - static void ramstage_cse_misc_ops(void *unused) { if (acpi_get_sleep_type() == ACPI_S3) diff --git a/src/soc/intel/common/block/cse/cse_sync_payload.c b/src/soc/intel/common/block/cse/cse_sync_payload.c new file mode 100644 index 00000000000..5c816d13668 --- /dev/null +++ b/src/soc/intel/common/block/cse/cse_sync_payload.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static void preram_create_cbmem_cse_info_for_payload(int is_recovery) +{ + /* + * CBMEM_ID_CSE_INFO will be used by the payload to - + * 1. Keep ISH firmware version on consecutive boots. + * 2. Track state of PSR data during CSE downgrade operation. + */ + void *temp = cbmem_add(CBMEM_ID_CSE_INFO, sizeof(struct cse_specific_info)); + if (!temp) + printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_INFO\n"); + + /* + * CBMEM_ID_CSE_BP_INFO will be used by the payload to keep CSE + * boot partition information on consecutive boots. + */ + temp = cbmem_add(CBMEM_ID_CSE_BP_INFO, sizeof(struct get_bp_info_rsp)); + if (!temp) + printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_BP_INFO\n"); +} + +CBMEM_CREATION_HOOK(preram_create_cbmem_cse_info_for_payload); From 62347c4669937ea47200fd677ad0368f6e289495 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 9 Jul 2024 23:15:39 +0530 Subject: [PATCH 06/11] soc/intel/meteorlake: Conditionally update CSE sync UPDs in FSP-M This patch updates FSP-M UPDs conditionally to ensure CSE firmware updates and VGA initialization control only when `SOC_INTEL_CSE_LITE_SKU` config is enabled. This ensures eSOL rendering is tied to CSE sync performed in coreboot, preventing unnecessary setup when sync is deferred to the payload. Deferring CSE sync to the payload results in the depthcharge screen. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Iffdd4b1be4abba8c57e28542058a575cc6de674c Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/83394 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- src/soc/intel/meteorlake/romstage/fsp_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index ec0bb8dae6f..ec783833ba9 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -454,7 +454,7 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg, sol_type = ELOG_FW_EARLY_SOL_MRC; } - if (is_cse_fw_update_required()) { + if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) { vga_init_control = VGA_INIT_CONTROL_ENABLE; sol_type = ELOG_FW_EARLY_SOL_CSE_SYNC; } From df052ff30ef328b82d25319f1bacb107d3b54225 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 9 Jul 2024 23:18:18 +0530 Subject: [PATCH 07/11] soc/intel: Extend CSE RW Update and ME read access for payload sync Modify the dependencies for `SOC_INTEL_CSE_RW_UPDATE` and `ME_REGION_ALLOW_CPU_READ_ACCESS` config options to include `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD`. This allows these features to be enabled even when CSE sync is performed in the payload, not just within coreboot (when `SOC_INTEL_CSE_LITE_SKU` config is enabled). BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Id6ec19d74237f278e8383c89923523871b2cc2db Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/83395 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- src/soc/intel/common/block/cse/Kconfig | 2 +- src/southbridge/intel/common/firmware/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index d8d2456a1e3..c4aa6b5fa76 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -184,7 +184,7 @@ config SOC_INTEL_CSE_SERVER_SKU config SOC_INTEL_CSE_RW_UPDATE bool "Enable the CSE RW Update Feature" default n - depends on SOC_INTEL_CSE_LITE_SKU + depends on SOC_INTEL_CSE_LITE_SKU || SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD help This config will enable CSE RW firmware update feature and also will be used ensure all the required configs are provided by mainboard. diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 45d8be87c30..95eda31c9d2 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -67,7 +67,7 @@ config CHECK_ME config ME_REGION_ALLOW_CPU_READ_ACCESS bool "Allows HOST/CPU read access to ME region" depends on HAVE_IFD_BIN - default y if SOC_INTEL_CSE_LITE_SKU + default y if SOC_INTEL_CSE_LITE_SKU || SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD default n help The config ensures Host has read access to the ME region if it is locked From 48e6b829139ba185851b97ae4728e46a7da87bc6 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 9 Jul 2024 23:25:54 +0530 Subject: [PATCH 08/11] soc/intel/meteorlake: Conditional selection of CSE Lite PSR This patch makes the selection of `SOC_INTEL_CSE_LITE_PSR` conditional on both `MAINBOARD_HAS_CHROMEOS` and `SOC_INTEL_CSE_LITE_SKU` being enabled. This ensures that CSE Lite PSR is only active when both ChromeOS is the target platform and CSE sync is performed inside coreboot. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I7199c034bbe6e7f077650417da67fa544f0b49d5 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/83396 Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/soc/intel/meteorlake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 622d35f529d..5ec891f65c6 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -91,7 +91,7 @@ config SOC_INTEL_METEORLAKE select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_IOC select SOC_INTEL_CRASHLOG - select SOC_INTEL_CSE_LITE_PSR if MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_CSE_LITE_PSR if MAINBOARD_HAS_CHROMEOS && SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_IOE_DIE_SUPPORT From 24d81018eadbb5488966ee3d794cb8b09f3f15be Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 9 Jul 2024 23:31:12 +0530 Subject: [PATCH 09/11] mb/google/rex: Refactor CSE config options for model-specific settings This patch refactors CSE config options, moving the selection of: * `SOC_INTEL_CSE_LITE_SKU` * `SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2` * `SOC_INTEL_CSE_SEND_EOP_ASYNC` from the generic `BOARD_GOOGLE_REX_COMMON` to individual board models. This enables finer-grained control over CSE features and sync behavior on different Rex and variants platforms. Specifically: * `google/rex0`: Selects `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot. * `google/rex64`: Selects `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` and `SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD` to defer CSE sync to the payload. BUG=b:305898363 TEST=Builds successfully for google/rex variants. Change-Id: Ib5957496b1e1dad8d135b3e10541cb83dd339539 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/83397 Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/mainboard/google/rex/Kconfig | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 9ee0bc06639..2ebcf320504 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -28,9 +28,6 @@ config BOARD_GOOGLE_REX_COMMON select MB_COMPRESS_RAMSTAGE_LZ4 select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT - select SOC_INTEL_CSE_LITE_SKU - select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 - select SOC_INTEL_CSE_SEND_EOP_ASYNC config BOARD_GOOGLE_BASEBOARD_OVIS def_bool n @@ -43,6 +40,9 @@ config BOARD_GOOGLE_BASEBOARD_OVIS select RT8168_GEN_ACPI_POWER_RESOURCE select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE + select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 + select SOC_INTEL_CSE_SEND_EOP_ASYNC select SOC_INTEL_IOE_DIE_SUPPORT select SOC_INTEL_METEORLAKE_U_H select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES @@ -71,6 +71,9 @@ config BOARD_GOOGLE_MODEL_DEKU config BOARD_GOOGLE_MODEL_KARIS def_bool n select BOARD_GOOGLE_BASEBOARD_REX + select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 + select SOC_INTEL_CSE_SEND_EOP_ASYNC config BOARD_GOOGLE_MODEL_OVIS def_bool n @@ -91,6 +94,9 @@ config BOARD_GOOGLE_MODEL_REX config BOARD_GOOGLE_MODEL_REX_EC_ISH def_bool n select BOARD_GOOGLE_MODEL_REX + select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 + select SOC_INTEL_CSE_SEND_EOP_ASYNC select SOC_INTEL_STORE_ISH_FW_VERSION config BOARD_GOOGLE_MODEL_SCREEBO @@ -98,6 +104,9 @@ config BOARD_GOOGLE_MODEL_SCREEBO select BOARD_GOOGLE_BASEBOARD_REX select DRIVERS_GENERIC_ALC1015 select DRIVERS_GENESYSLOGIC_GL9750 + select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 + select SOC_INTEL_CSE_SEND_EOP_ASYNC config BOARD_GOOGLE_DEKU select BOARD_GOOGLE_MODEL_DEKU @@ -121,10 +130,15 @@ config BOARD_GOOGLE_OVIS4ES config BOARD_GOOGLE_REX0 select BOARD_GOOGLE_MODEL_REX + select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 + select SOC_INTEL_CSE_SEND_EOP_ASYNC config BOARD_GOOGLE_REX64 select BOARD_GOOGLE_MODEL_REX select HAVE_X86_64_SUPPORT + select SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD + select SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD select USE_X86_64_SUPPORT config BOARD_GOOGLE_REX_EC_ISH @@ -132,6 +146,9 @@ config BOARD_GOOGLE_REX_EC_ISH config BOARD_GOOGLE_REX4ES select BOARD_GOOGLE_MODEL_REX + select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 + select SOC_INTEL_CSE_SEND_EOP_ASYNC select SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON config BOARD_GOOGLE_REX4ES_EC_ISH From e94d29a02bf50c1cc9bd9340375134832d3ad4a2 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 9 Jul 2024 23:44:53 +0530 Subject: [PATCH 10/11] soc/intel/cmn/cse: Refine boot partition logging This patch ensures CSE boot partition (RO/RW) version information only log when the status is "success". If the status is not successful, log an error message indicating the failure and status code. This change avoids logging potentially incorrect version information when the boot partition is not valid. BUG=b:305898363 TEST=Builds successfully for google/rex variants. Change-Id: I1932302b145326a1131d64b04af1cbfd6d050b7b Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/83398 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- src/soc/intel/common/block/cse/cse_lite.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 6c4fed7c41a..0917897e308 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -271,18 +271,22 @@ static void cse_print_boot_partition_info(void) /* Log version info of RO & RW partitions */ cse_bp = cse_get_bp_entry(RO); - printk(BIOS_DEBUG, "cse_lite: %s version = %d.%d.%d.%d (Status=0x%x, Start=0x%x, End=0x%x)\n", + if (cse_bp->status == BP_STATUS_SUCCESS) + printk(BIOS_DEBUG, "cse_lite: %s version = %d.%d.%d.%d (Start=0x%x, End=0x%x)\n", GET_BP_STR(RO), cse_bp->fw_ver.major, cse_bp->fw_ver.minor, cse_bp->fw_ver.hotfix, cse_bp->fw_ver.build, - cse_bp->status, cse_bp->start_offset, - cse_bp->end_offset); + cse_bp->start_offset, cse_bp->end_offset); + else + printk(BIOS_ERR, "cse_lite: %s status=0x%x\n", GET_BP_STR(RO), cse_bp->status); cse_bp = cse_get_bp_entry(RW); - printk(BIOS_DEBUG, "cse_lite: %s version = %d.%d.%d.%d (Status=0x%x, Start=0x%x, End=0x%x)\n", + if (cse_bp->status == BP_STATUS_SUCCESS) + printk(BIOS_DEBUG, "cse_lite: %s version = %d.%d.%d.%d (Start=0x%x, End=0x%x)\n", GET_BP_STR(RW), cse_bp->fw_ver.major, cse_bp->fw_ver.minor, cse_bp->fw_ver.hotfix, cse_bp->fw_ver.build, - cse_bp->status, cse_bp->start_offset, - cse_bp->end_offset); + cse_bp->start_offset, cse_bp->end_offset); + else + printk(BIOS_ERR, "cse_lite: %s status=0x%x\n", GET_BP_STR(RW), cse_bp->status); } /* From 7f822a3368fcfabc7bb0f316a9eafba5a0604f43 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 10 Jul 2024 17:29:38 +0000 Subject: [PATCH 11/11] libpayload/x86: Add x86-64 support to rdtsc() This patch adds support for x86-64 to the rdtsc() function, allowing it to correctly read the Time Stamp Counter (TSC) on both 32-bit and 64-bit x86 architectures. BUG=b:242829490, b:351851626 TEST=Builds and boots on google/rex0 and google/rex64 systems and manually verified correct TSC readings on x86-32 and x86-64 hardware. Change-Id: I0afac3db2e82a245a37c2e5cf2302bf1dad62c01 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/83414 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- payloads/libpayload/include/x86/arch/rdtsc.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/include/x86/arch/rdtsc.h b/payloads/libpayload/include/x86/arch/rdtsc.h index 41ab24a9c7b..2c92a9f4d42 100644 --- a/payloads/libpayload/include/x86/arch/rdtsc.h +++ b/payloads/libpayload/include/x86/arch/rdtsc.h @@ -33,9 +33,9 @@ static u64 rdtsc(void) { - u64 val; - __asm__ __volatile__ ("rdtsc" : "=A" (val)); - return val; + u32 lo, hi; + __asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi)); + return (u64)hi << 32 | lo; } #endif