diff --git a/3rdparty/fsp b/3rdparty/fsp index cc6399e8c75..800c85770b4 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit cc6399e8c759ad4ed83c2d6ea568fd918fc9bc06 +Subproject commit 800c85770b458ee7f7eeb1276b46e904590d3bd7 diff --git a/3rdparty/vboot b/3rdparty/vboot index 09fcd2184f9..b6f44e62650 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 09fcd2184f9c714829503e84b8a7dfe7f2584e00 +Subproject commit b6f44e62650e563cca651bd4349c418450dd1bd3 diff --git a/Makefile b/Makefile index bc6fabc2e51..cc73900bda5 100644 --- a/Makefile +++ b/Makefile @@ -222,8 +222,7 @@ endif # The primary target needs to be here before we include the # other files - -real-all: real-target +real-all: site-local-target real-target # must come rather early .SECONDARY: diff --git a/Makefile.mk b/Makefile.mk index a16089d6d22..68fc8c988e6 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -90,6 +90,13 @@ show_coreboot: | files_added .PHONY: show_notices show_notices:: | show_coreboot +# This rule allows the site-local makefile to run before starting the actual +# coreboot build. It should not be used in the regular coreboot makefiles. +# Note: This gets run after the immediate makefile code like updating the +# submodules, but before any other targets. +.PHONY: site-local-target +site-local-target:: + ####################################################################### # our phony targets PHONY+= clean-abuild coreboot check-style build_complete @@ -528,7 +535,6 @@ CFLAGS_common += -fno-pie CFLAGS_common += -Wstring-compare ifeq ($(CONFIG_COMPILER_GCC),y) CFLAGS_common += -Wold-style-declaration -CFLAGS_common += -Walloc-size CFLAGS_common += -Wcast-function-type # Don't add these GCC specific flags when running scan-build ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) diff --git a/src/arch/arm64/dma.c b/src/arch/arm64/dma.c index cdeb50fa09d..ec81ab7d5ea 100644 --- a/src/arch/arm64/dma.c +++ b/src/arch/arm64/dma.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include int dma_coherent(const void *ptr) diff --git a/src/arch/arm64/smbios.c b/src/arch/arm64/smbios.c index f0be956cd51..4bf35c4c173 100644 --- a/src/arch/arm64/smbios.c +++ b/src/arch/arm64/smbios.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index 7d332e1fd2c..1ab6a0a3ba2 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -50,6 +50,9 @@ static void intel_ish_enable(struct device *dev) static void intel_ish_get_version(void) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) + return; + struct cse_specific_info *info = cbmem_find(CBMEM_ID_CSE_INFO); if (info == NULL) return; diff --git a/src/include/device/dram/rcd.h b/src/include/device/dram/rcd.h index d0b1f2c031e..d8429b39b4e 100644 --- a/src/include/device/dram/rcd.h +++ b/src/include/device/dram/rcd.h @@ -5,7 +5,6 @@ #include #include -#include enum rcw_idx { VEN_ID_L, diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 2d5a7eb0043..3cf77d6fd84 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -21,10 +21,6 @@ void gfx_set_init_done(int done) int display_init_required(void) { - /* Need display for showing splash screen. */ - if (CONFIG(BMP_LOGO)) - return 1; - /* For vboot, honor VB2_CONTEXT_DISPLAY_INIT. */ if (CONFIG(VBOOT)) { /* Must always select MUST_REQUEST_DISPLAY when using this diff --git a/src/mainboard/asrock/z87m_oc_formula/Kconfig b/src/mainboard/asrock/z87m_oc_formula/Kconfig new file mode 100644 index 00000000000..c05f2fd85ac --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/Kconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_ASROCK_Z87M_OC_FORMULA + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87m_oc_formula" + +config MAINBOARD_PART_NUMBER + default "Z87M OC Formula" + +config USBDEBUG_HCD_INDEX + default 1 # This is the top-most of the two USB-3.0-Ports beneath the RJ45 jack. +endif diff --git a/src/mainboard/asrock/z87m_oc_formula/Kconfig.name b/src/mainboard/asrock/z87m_oc_formula/Kconfig.name new file mode 100644 index 00000000000..0412b1c00cd --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/Kconfig.name @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_ASROCK_Z87M_OC_FORMULA + bool "Z87M OC Formula" diff --git a/src/mainboard/asrock/z87m_oc_formula/Makefile.mk b/src/mainboard/asrock/z87m_oc_formula/Makefile.mk new file mode 100644 index 00000000000..93f729d787c --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/Makefile.mk @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87m_oc_formula/acpi/ec.asl b/src/mainboard/asrock/z87m_oc_formula/acpi/ec.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87m_oc_formula/acpi/platform.asl b/src/mainboard/asrock/z87m_oc_formula/acpi/platform.asl new file mode 100644 index 00000000000..aff432b6f47 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87m_oc_formula/acpi/superio.asl b/src/mainboard/asrock/z87m_oc_formula/acpi/superio.asl new file mode 100644 index 00000000000..16990d45f42 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87m_oc_formula/board_info.txt b/src/mainboard/asrock/z87m_oc_formula/board_info.txt new file mode 100644 index 00000000000..072d2582144 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Z87M%20OC%20Formula/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 (2x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87m_oc_formula/bootblock.c b/src/mainboard/asrock/z87m_oc_formula/bootblock.c new file mode 100644 index 00000000000..1cec5c4fc07 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/bootblock.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* FIXME: remove this if not needed */ +void mainboard_config_superio(void) +{ +} diff --git a/src/mainboard/asrock/z87m_oc_formula/data.vbt b/src/mainboard/asrock/z87m_oc_formula/data.vbt new file mode 100644 index 00000000000..0f70e00fd01 Binary files /dev/null and b/src/mainboard/asrock/z87m_oc_formula/data.vbt differ diff --git a/src/mainboard/asrock/z87m_oc_formula/devicetree.cb b/src/mainboard/asrock/z87m_oc_formula/devicetree.cb new file mode 100644 index 00000000000..cbde4cbb791 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/devicetree.cb @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_dp_c_hotplug" = "4" + + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + device domain 0 on + ops haswell_pci_domain_ops + + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1849 0x0c00 + end + device pci 01.0 on # PEG + end + device pci 02.0 on # iGPU + subsystemid 0x1849 0x0412 + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1849 0x0c0c + end + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "gpe0_en_1" = "0x2246" + register "sata_port0_gen3_dtle" = "0xa" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + device pci 14.0 on # xHCI Controller + subsystemid 0x1849 0x8c31 + end + device pci 16.0 on # MEI #1 + subsystemid 0x1849 0x8c3a + end + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1849 0x153b + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x8c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0x1151 + end + device pci 1c.0 on # RP #1 + subsystemid 0x1849 0x8c10 + end + device pci 1c.1 on # RP #2 mPCIe slot + subsystemid 0x1849 0x8c12 + end + device pci 1c.2 on # RP #3 + end + device pci 1c.3 on # RP #4 PCIe NVMe Controller + end + device pci 1c.4 on # RP #5 + end + device pci 1c.5 on # RP #6 + end + device pci 1c.6 on # RP #7 + end + device pci 1c.7 on # RP #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x8c26 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8c44 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + irq 0xe0 = 0xf9 # + GPIO0 direction + irq 0xe1 = 0xfd # + GPIO0 value + end + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on # GPIO1 + irq 0xf0 = 0xf1 # + GPIO1 direction + irq 0xf1 = 0xf1 # + GPIO1 value + end + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on # GPIO7 + irq 0xe0 = 0xff # + GPIO7 direction + end + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # + Power RAM in S3 + irq 0xf0 = 0x20 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1849 0x8c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8c22 + end + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/z87m_oc_formula/dsdt.asl b/src/mainboard/asrock/z87m_oc_formula/dsdt.asl new file mode 100644 index 00000000000..2eb0805cf24 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asrock/z87m_oc_formula/gma-mainboard.ads b/src/mainboard/asrock/z87m_oc_formula/gma-mainboard.ads new file mode 100644 index 00000000000..61dc90a1518 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, -- DP + HDMI2, -- DP + HDMI3, -- HDMI + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87m_oc_formula/gpio.c b/src/mainboard/asrock/z87m_oc_formula/gpio.c new file mode 100644 index 00000000000..01d39f2f970 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/gpio.c @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio10 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87m_oc_formula/hda_verb.c b/src/mainboard/asrock/z87m_oc_formula/hda_verb.c new file mode 100644 index 00000000000..ab7da869de7 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/hda_verb.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek */ + 0x18491151, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491151), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87m_oc_formula/romstage.c b/src/mainboard/asrock/z87m_oc_formula/romstage.c new file mode 100644 index 00000000000..44932e7229e --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/romstage.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_config_rcba(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[1] = 0x51; + spdi->addresses[2] = 0x52; + spdi->addresses[3] = 0x53; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/gigabyte/ga-h61m-series/Kconfig b/src/mainboard/gigabyte/ga-h61m-series/Kconfig index 77bd800bfe9..09a06edc7fc 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-series/Kconfig @@ -30,29 +30,34 @@ config BOARD_GIGABYTE_GA_H61MA_D3V select BOARD_GIGABYTE_GA_H61M_SERIES select NO_UART_ON_SUPERIO +config BOARD_GIGABYTE_GA_H61M_S2P_R3 + select BOARD_GIGABYTE_GA_H61M_SERIES + if BOARD_GIGABYTE_GA_H61M_SERIES config MAINBOARD_DIR default "gigabyte/ga-h61m-series" config VARIANT_DIR - default "ga-h61m-s2pv" if BOARD_GIGABYTE_GA_H61M_S2PV - default "ga-h61m-ds2v" if BOARD_GIGABYTE_GA_H61M_DS2V - default "ga-h61ma-d3v" if BOARD_GIGABYTE_GA_H61MA_D3V - default "ga-h61m-ds2" if BOARD_GIGABYTE_GA_H61M_DS2 + default "ga-h61m-s2pv" if BOARD_GIGABYTE_GA_H61M_S2PV + default "ga-h61m-ds2v" if BOARD_GIGABYTE_GA_H61M_DS2V + default "ga-h61ma-d3v" if BOARD_GIGABYTE_GA_H61MA_D3V + default "ga-h61m-ds2" if BOARD_GIGABYTE_GA_H61M_DS2 + default "ga-h61m-s2p-r3" if BOARD_GIGABYTE_GA_H61M_S2P_R3 config MAINBOARD_PART_NUMBER - default "GA-H61M-S2PV" if BOARD_GIGABYTE_GA_H61M_S2PV - default "GA-H61M-DS2V" if BOARD_GIGABYTE_GA_H61M_DS2V - default "GA-H61MA-D3V" if BOARD_GIGABYTE_GA_H61MA_D3V - default "GA-H61M-DS2" if BOARD_GIGABYTE_GA_H61M_DS2 + default "GA-H61M-S2PV" if BOARD_GIGABYTE_GA_H61M_S2PV + default "GA-H61M-DS2V" if BOARD_GIGABYTE_GA_H61M_DS2V + default "GA-H61MA-D3V" if BOARD_GIGABYTE_GA_H61MA_D3V + default "GA-H61M-DS2" if BOARD_GIGABYTE_GA_H61M_DS2 + default "GA-H61M-S2P-R3" if BOARD_GIGABYTE_GA_H61M_S2P_R3 config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" # Override the default variant behavior, since the data.vbt is the same config INTEL_GMA_VBT_FILE - default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" + default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" if !BOARD_GIGABYTE_GA_H61M_S2P_R3 config USBDEBUG_HCD_INDEX # Bottom left port seen from rear int diff --git a/src/mainboard/gigabyte/ga-h61m-series/Kconfig.name b/src/mainboard/gigabyte/ga-h61m-series/Kconfig.name index 6cf079eaef3..245e31ce5ca 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/Kconfig.name +++ b/src/mainboard/gigabyte/ga-h61m-series/Kconfig.name @@ -11,3 +11,6 @@ config BOARD_GIGABYTE_GA_H61M_DS2V config BOARD_GIGABYTE_GA_H61MA_D3V bool "GA-H61MA-D3V" + +config BOARD_GIGABYTE_GA_H61M_S2P_R3 + bool "GA-H61M-S2P-R3" diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/data.vbt b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/data.vbt new file mode 100644 index 00000000000..bd50743344a Binary files /dev/null and b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/data.vbt differ diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/gpio.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/gpio.c new file mode 100644 index 00000000000..d6a62515fb8 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/gpio.c @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/hda_verb.c new file mode 100644 index 00000000000..3856bb0ca17 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/hda_verb.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Realtek ALC887 */ + 0x1458a002, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x1458a002), + AZALIA_PIN_CFG(2, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x14, 0x01014410), + AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(2, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(2, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/overridetree.cb b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/overridetree.cb new file mode 100644 index 00000000000..fbebf1c8309 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/overridetree.cb @@ -0,0 +1,78 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x1458 0x5001 inherit + + chip southbridge/intel/bd82x6x + register "usb_port_config" = "{ + {1, 6, 0}, + {1, 6, 0}, + {1, 6, 1}, + {1, 6, 1}, + {1, 6, 2}, + {1, 6, 2}, + {1, 6, 3}, + {1, 6, 3}, + {1, 6, 4}, + {1, 6, 4}, + {1, 6, 6}, + {1, 6, 5}, + {1, 6, 5}, + {1, 6, 6}, + }" + + device ref pcie_rp1 on end # PCIe x1 Port (PCIEX1) + device ref pcie_rp2 on end # VIA Labs VL805 USB 3.0 + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 on # Realtek RTL8111F GbE NIC + device pci 00.0 on + subsystemid 0x1458 0x8892 + end + end + device ref pcie_rp6 on end # ITE IT8892F PCIe to PCI bridge + + device ref lpc on + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x03f8 + irq 0x70 = 0x04 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 on # Parallel port + io 0x60 = 0x0378 + irq 0x70 = 0x05 + drq 0x74 = 0x04 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + irq 0x70 = 0x09 + io 0x62 = 0x0230 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 + irq 0x70 = 0x01 + io 0x62 = 0x0064 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 0x0c + end + device pnp 2e.7 on # GPIO + irq 0x25 = 0x40 + irq 0x27 = 0x10 + irq 0x2c = 0x80 + io 0x60 = 0x0000 + io 0x62 = 0x0a00 + io 0x64 = 0x0000 + irq 0x70 = 0x00 + irq 0xcb = 0x00 + irq 0xf1 = 0x42 + end + device pnp 2e.a off end # CIR + end + end + end + end +end diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb index 274e22c106b..187840f1ce7 100644 --- a/src/mainboard/google/brox/variants/lotso/overridetree.cb +++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb @@ -48,6 +48,22 @@ chip soc/intel/alderlake register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable TCP0 register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable TCP2 + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 350, + .data_hold_time_ns = 400, + }, + .i2c[4] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 110, + .data_hold_time_ns = 100, + }, + }" + register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoPci, [PchSerialIoIndexGSPI1] = PchSerialIoPci, diff --git a/src/mainboard/google/rex/variants/deku/memory/Makefile.mk b/src/mainboard/google/rex/variants/deku/memory/Makefile.mk index e7518edee89..7f40cb3cf57 100644 --- a/src/mainboard/google/rex/variants/deku/memory/Makefile.mk +++ b/src/mainboard/google/rex/variants/deku/memory/Makefile.mk @@ -4,4 +4,4 @@ # ./util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/deku/memory src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 0(0b0000) Parts = MT62F2G32D4DS-026 WT:B, H58G66BK7BX067 +SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 0(0b0000) Parts = MT62F2G32D4DS-026 WT:B, H58G66BK7BX067, K3KL9L90CM-MGCT diff --git a/src/mainboard/google/rex/variants/deku/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/deku/memory/dram_id.generated.txt index 0e3a06a9764..4a7f8e4bf8b 100644 --- a/src/mainboard/google/rex/variants/deku/memory/dram_id.generated.txt +++ b/src/mainboard/google/rex/variants/deku/memory/dram_id.generated.txt @@ -6,3 +6,4 @@ DRAM Part Name ID to assign MT62F2G32D4DS-026 WT:B 0 (0000) H58G66BK7BX067 0 (0000) +K3KL9L90CM-MGCT 0 (0000) diff --git a/src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt index 0871f3cde34..fd3ed99af4b 100644 --- a/src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt +++ b/src/mainboard/google/rex/variants/deku/memory/mem_parts_used.txt @@ -11,3 +11,4 @@ # Part Name MT62F2G32D4DS-026 WT:B H58G66BK7BX067 +K3KL9L90CM-MGCT diff --git a/src/mainboard/ibm/sbp1/romstage.c b/src/mainboard/ibm/sbp1/romstage.c index 489f09f05b7..2c4745e7e8a 100644 --- a/src/mainboard/ibm/sbp1/romstage.c +++ b/src/mainboard/ibm/sbp1/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index d42dc74c514..e30e8ee372f 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -156,6 +156,7 @@ config VBOOT_MUST_REQUEST_DISPLAY config VBOOT_ALWAYS_ENABLE_DISPLAY bool "Force to always enable display" + default y if BMP_LOGO default n help Set this option to indicate to vboot that display should always be enabled. diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index edc7e23d1b3..d8d2456a1e3 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -97,7 +97,7 @@ config SOC_INTEL_STORE_ISH_FW_VERSION config SOC_INTEL_CSE_SEND_EOP_EARLY bool "CSE send EOP early" - depends on SOC_INTEL_COMMON_BLOCK_CSE + depends on SOC_INTEL_COMMON_BLOCK_CSE && !SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD help Use this config to send End Of Post (EOP) earlier through SoC code in order to reduce time required to send EOP and getting CSE response. @@ -106,7 +106,7 @@ config SOC_INTEL_CSE_SEND_EOP_EARLY config SOC_INTEL_CSE_SEND_EOP_LATE bool - depends on SOC_INTEL_COMMON_BLOCK_CSE + depends on SOC_INTEL_COMMON_BLOCK_CSE && !SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD help Use this config to send End Of Post (EOP) late (even after CSE `final` operation) using boot state either `BS_PAYLOAD_BOOT` or `BS_PAYLOAD_LOAD` from common code @@ -119,7 +119,7 @@ config SOC_INTEL_CSE_SEND_EOP_LATE config SOC_INTEL_CSE_SEND_EOP_ASYNC bool - depends on SOC_INTEL_COMMON_BLOCK_CSE + depends on SOC_INTEL_COMMON_BLOCK_CSE && !SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD depends on !SOC_INTEL_CSE_SEND_EOP_LATE depends on !SOC_INTEL_CSE_SEND_EOP_EARLY help @@ -139,10 +139,6 @@ config SOC_INTEL_CSE_SEND_EOP_ASYNC config SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD bool depends on SOC_INTEL_COMMON_BLOCK_CSE - depends on !SOC_INTEL_CSE_SEND_EOP_LATE - depends on !SOC_INTEL_CSE_SEND_EOP_EARLY - depends on !SOC_INTEL_CSE_SEND_EOP_ASYNC - depends on !DISABLE_HECI1_AT_PRE_BOOT help Use this config to specify that the payload will send the End Of Post (EOP) instead of coreboot. @@ -169,7 +165,7 @@ config SOC_INTEL_CSE_LITE_SKU config SOC_INTEL_CSE_LITE_PSR bool default n - depends on SOC_INTEL_CSE_LITE_SKU + depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE help Select this config if Platform Service Record(PSR) is supported by the platform. This @@ -298,7 +294,7 @@ config SOC_INTEL_CSE_LITE_COMPRESS_ME_RW config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY def_bool n - depends on SOC_INTEL_CSE_LITE_SKU + depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD help Mainboard user to select this Kconfig in order to capture pre-cpu reset boot performance telemetry data. @@ -320,13 +316,14 @@ config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE bool default !SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE - depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_COMPRESS_ME_RW + depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_COMPRESS_ME_RW && !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD help Use default flow of CSE FW Update in romstage when uncompressed ME_RW blobs are used. config SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE bool default n + depends on !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD help Use this option if CSE RW update needs to be triggered during RAMSTAGE. diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d78b8a01012..ed07f692839 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -861,23 +861,8 @@ int cse_hmrfpo_get_status(void) return resp.status; } -void print_me_fw_version(void *unused) -{ - struct me_fw_ver_resp resp = {0}; - - /* Ignore if UART debugging is disabled */ - if (!CONFIG(CONSOLE_SERIAL)) - return; - - if (get_me_fw_version(&resp) == CB_SUCCESS) { - printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, - resp.code.minor, resp.code.hotfix, resp.code.build); - return; - } - printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); -} - -enum cb_err get_me_fw_version(struct me_fw_ver_resp *resp) +/* Queries and gets ME firmware version */ +static enum cb_err get_me_fw_version(struct me_fw_ver_resp *resp) { const struct mkhi_hdr fw_ver_msg = { .group_id = MKHI_GROUP_ID_GEN, @@ -894,13 +879,6 @@ enum cb_err get_me_fw_version(struct me_fw_ver_resp *resp) if (!is_cse_enabled()) return CB_ERR; - /* - * Ignore if ME Firmware SKU type is Lite since - * print_boot_partition_info() logs RO(BP1) and RW(BP2) versions. - */ - if (cse_is_hfs3_fw_sku_lite()) - return CB_ERR; - /* * Prerequisites: * 1) HFSTS1 Current Working State is Normal @@ -924,6 +902,29 @@ enum cb_err get_me_fw_version(struct me_fw_ver_resp *resp) return CB_SUCCESS; } +void print_me_fw_version(void *unused) +{ + struct me_fw_ver_resp resp = {0}; + + /* Ignore if UART debugging is disabled */ + if (!CONFIG(CONSOLE_SERIAL)) + return; + + /* + * Skip if ME firmware is Lite SKU, as RO/RW versions are + * already logged by `cse_print_boot_partition_info()` + */ + if (cse_is_hfs3_fw_sku_lite()) + return; + + if (get_me_fw_version(&resp) == CB_SUCCESS) { + printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, + resp.code.minor, resp.code.hotfix, resp.code.build); + return; + } + printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); +} + void cse_trigger_vboot_recovery(enum csme_failure_reason reason) { printk(BIOS_DEBUG, "cse: CSE status registers: HFSTS1: 0x%x, HFSTS2: 0x%x " @@ -1418,6 +1419,9 @@ void cse_late_finalize(void) static void intel_cse_get_rw_version(void) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) + return; + struct cse_specific_info *info = cbmem_find(CBMEM_ID_CSE_INFO); if (info == NULL) return; diff --git a/src/soc/intel/common/block/cse/cse_spec.c b/src/soc/intel/common/block/cse/cse_spec.c index 74155cd1501..af64255514d 100644 --- a/src/soc/intel/common/block/cse/cse_spec.c +++ b/src/soc/intel/common/block/cse/cse_spec.c @@ -28,6 +28,9 @@ static bool is_manufacturing_mode(union me_hfsts1 hfsts1, union me_hfsts6 hfsts6 static void dump_me_status(void *unused) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) + return; + union me_hfsts1 hfsts1; union me_hfsts2 hfsts2; union me_hfsts3 hfsts3; diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 3db13248d2c..552eb7b2d42 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -443,11 +443,6 @@ int cse_hmrfpo_get_status(void); */ void print_me_fw_version(void *unused); -/* - * Queries and gets ME firmware version - */ -enum cb_err get_me_fw_version(struct me_fw_ver_resp *resp); - /* * Checks current working operation state is normal or not. * Returns true if CSE's current working state is normal, otherwise false. diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 9bee9becae2..58c4556abaa 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -192,7 +192,7 @@ config FSP_HEADER_PATH config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/ElkhartLakeFspBinPkg/FspBin/FSP.fd" + default "3rdparty/fsp/ElkhartLakeFspBinPkg/FspBin/FSPRel.bin" config PSE_ENABLE bool "Enable PSE ARM controller" diff --git a/src/soc/intel/xeon_sp/chip_gen6.c b/src/soc/intel/xeon_sp/chip_gen6.c index c4462d56c98..8bbfbe871b5 100644 --- a/src/soc/intel/xeon_sp/chip_gen6.c +++ b/src/soc/intel/xeon_sp/chip_gen6.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/intel/xeon_sp/config.c b/src/soc/intel/xeon_sp/config.c index c2a908c984e..a61f724ae14 100644 --- a/src/soc/intel/xeon_sp/config.c +++ b/src/soc/intel/xeon_sp/config.c @@ -6,3 +6,8 @@ __weak enum xeonsp_cxl_mode get_cxl_mode(void) { return XEONSP_CXL_DISABLED; } + +__weak enum xeonsp_fast_boot_mode get_fast_boot_mode(void) +{ + return XEONSP_FAST_BOOT_COLD | XEONSP_FAST_BOOT_WARM; +} diff --git a/src/soc/intel/xeon_sp/gnr/romstage.c b/src/soc/intel/xeon_sp/gnr/romstage.c index 95b2e15a5d0..0c3aed04191 100644 --- a/src/soc/intel/xeon_sp/gnr/romstage.c +++ b/src/soc/intel/xeon_sp/gnr/romstage.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include static uint8_t get_mmcfg_base_upd_index(const uint64_t base_addr) @@ -48,6 +50,19 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) m_cfg->mmCfgBase = get_mmcfg_base_upd_index(CONFIG_ECAM_MMCONF_BASE_ADDRESS); m_cfg->mmCfgSize = get_mmcfg_size_upd_index(CONFIG_ECAM_MMCONF_LENGTH); + /* fast boot setting */ + int fast_boot_mode = get_fast_boot_mode(); + m_cfg->AttemptFastBoot = !!(fast_boot_mode & XEONSP_FAST_BOOT_WARM); + m_cfg->AttemptFastBootCold = !!(fast_boot_mode & XEONSP_FAST_BOOT_COLD); + + FSPM_ARCH2_UPD *arch_upd = &mupd->FspmArchUpd; + if (fast_boot_mode == XEONSP_FAST_BOOT_DISABLED) { + arch_upd->BootMode = + FSP_BOOT_WITH_FULL_CONFIGURATION; + printk(BIOS_NOTICE, "Reset BootMode as " + "FSP_BOOT_WITH_FULL_CONFIGURATION.\n"); + } + /* Board level settings */ mainboard_memory_init_params(mupd); } diff --git a/src/soc/intel/xeon_sp/include/soc/config.h b/src/soc/intel/xeon_sp/include/soc/config.h index 6d5f3d587d4..66538f5a284 100644 --- a/src/soc/intel/xeon_sp/include/soc/config.h +++ b/src/soc/intel/xeon_sp/include/soc/config.h @@ -11,4 +11,12 @@ enum xeonsp_cxl_mode { enum xeonsp_cxl_mode get_cxl_mode(void); +enum xeonsp_fast_boot_mode { + XEONSP_FAST_BOOT_DISABLED = 0x0, + XEONSP_FAST_BOOT_COLD = 0x1, + XEONSP_FAST_BOOT_WARM = 0x2, +}; + +enum xeonsp_fast_boot_mode get_fast_boot_mode(void); + #endif diff --git a/src/soc/qualcomm/common/include/soc/qup_se_handlers_common.h b/src/soc/qualcomm/common/include/soc/qup_se_handlers_common.h index a004c7944c5..b9dfb25f022 100644 --- a/src/soc/qualcomm/common/include/soc/qup_se_handlers_common.h +++ b/src/soc/qualcomm/common/include/soc/qup_se_handlers_common.h @@ -3,7 +3,6 @@ #ifndef __SOC_COMMON_QCOM_QUP_SE_H__ #define __SOC_COMMON_QCOM_QUP_SE_H__ -#include #include #include #include diff --git a/src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h b/src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h index fc1721afa93..ad93865da8c 100644 --- a/src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h +++ b/src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include /* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */ #define USB3_PCS_PHYSTATUS BIT(6) diff --git a/src/soc/qualcomm/common/include/soc/usb/qusb_phy.h b/src/soc/qualcomm/common/include/soc/usb/qusb_phy.h index dd4a736bd04..90c6ff3c35a 100644 --- a/src/soc/qualcomm/common/include/soc/usb/qusb_phy.h +++ b/src/soc/qualcomm/common/include/soc/usb/qusb_phy.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #define PORT_TUNE1_MASK 0xf0 diff --git a/src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h b/src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h index de0b385c0b3..353aba52a4a 100644 --- a/src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h +++ b/src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include struct usb_board_data { /*Register values going to override from the boardfile*/ diff --git a/src/soc/qualcomm/common/qupv3_spi.c b/src/soc/qualcomm/common/qupv3_spi.c index 1bb5c75e5e9..5e05d573ff2 100644 --- a/src/soc/qualcomm/common/qupv3_spi.c +++ b/src/soc/qualcomm/common/qupv3_spi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/src/soc/qualcomm/common/usb/qmpv3_usb_phy.c b/src/soc/qualcomm/common/usb/qmpv3_usb_phy.c index c1782be7901..8c4c339b500 100644 --- a/src/soc/qualcomm/common/usb/qmpv3_usb_phy.c +++ b/src/soc/qualcomm/common/usb/qmpv3_usb_phy.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include diff --git a/src/soc/qualcomm/common/usb/qmpv4_usb_phy.c b/src/soc/qualcomm/common/usb/qmpv4_usb_phy.c index 23ab75ad2a7..6a5d7abcb0d 100644 --- a/src/soc/qualcomm/common/usb/qmpv4_usb_phy.c +++ b/src/soc/qualcomm/common/usb/qmpv4_usb_phy.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include diff --git a/src/soc/qualcomm/common/usb/qusb_phy.c b/src/soc/qualcomm/common/usb/qusb_phy.c index ddb087f0aa1..0defd2f3b33 100644 --- a/src/soc/qualcomm/common/usb/qusb_phy.c +++ b/src/soc/qualcomm/common/usb/qusb_phy.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include diff --git a/src/soc/qualcomm/common/usb/snps_usb_phy.c b/src/soc/qualcomm/common/usb/snps_usb_phy.c index d04694b0c7e..a7ad7ba8197 100644 --- a/src/soc/qualcomm/common/usb/snps_usb_phy.c +++ b/src/soc/qualcomm/common/usb/snps_usb_phy.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 268df0a5174..662b8a2ca98 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 1c3e810d198..033ccf4834f 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -51,20 +51,20 @@ union gprd { * protected region start address, where bit 0-11 of * the start address are assumed to be zero. */ - uint32_t start:15; + uint32_t start : 15; /* Specifies read protection is enabled */ - uint32_t read_protect_en:1; + uint32_t read_protect_en : 1; /* * End Address: bit 16-30 of the GPRD represents the * protected region end address, where bit 0-11 of * the end address are assumed to be 0xfff. */ - uint32_t end:15; + uint32_t end : 15; /* Specifies write protection is enabled */ - uint32_t write_protect_en:1; + uint32_t write_protect_en : 1; } __packed data; uint32_t value; @@ -133,9 +133,9 @@ static struct fdbar *find_fd(char *image, int size) /* Scan for FD signature */ for (i = 0; i < (size - 4); i += 4) { - if (*(uint32_t *) (image + i) == 0x0FF0A55A) { + if (*(uint32_t *)(image + i) == 0x0FF0A55A) { found = 1; - break; // signature found. + break; // signature found. } } @@ -144,7 +144,7 @@ static struct fdbar *find_fd(char *image, int size) return NULL; } - struct fdbar *fdb = (struct fdbar *) (image + i); + struct fdbar *fdb = (struct fdbar *)(image + i); return PTR_IN_RANGE(fdb, image, size) ? fdb : NULL; } @@ -168,9 +168,8 @@ static struct fcba *find_fcba(char *image, int size) struct fdbar *fdb = find_fd(image, size); if (!fdb) return NULL; - struct fcba *fcba = (struct fcba *) (image + ((fdb->flmap0 & 0xff) << 4)); + struct fcba *fcba = (struct fcba *)(image + ((fdb->flmap0 & 0xff) << 4)); return PTR_IN_RANGE(fcba, image, size) ? fcba : NULL; - } static struct fmba *find_fmba(char *image, int size) @@ -178,7 +177,7 @@ static struct fmba *find_fmba(char *image, int size) struct fdbar *fdb = find_fd(image, size); if (!fdb) return NULL; - struct fmba *fmba = (struct fmba *) (image + ((fdb->flmap1 & 0xff) << 4)); + struct fmba *fmba = (struct fmba *)(image + ((fdb->flmap1 & 0xff) << 4)); return PTR_IN_RANGE(fmba, image, size) ? fmba : NULL; } @@ -211,7 +210,7 @@ static struct fmsba *find_fmsba(char *image, int size) struct fdbar *fdb = find_fd(image, size); if (!fdb) return NULL; - struct fmsba *fmsba = (struct fmsba *) (image + ((fdb->flmap2 & 0xff) << 4)); + struct fmsba *fmsba = (struct fmsba *)(image + ((fdb->flmap2 & 0xff) << 4)); return PTR_IN_RANGE(fmsba, image, size) ? fmsba : NULL; } @@ -355,7 +354,7 @@ static struct region get_region(const struct frba *frba, unsigned int region_typ if (region_type >= max_regions) { fprintf(stderr, "Invalid region type %d.\n", region_type); - exit (EXIT_FAILURE); + exit(EXIT_FAILURE); } flreg = frba->flreg[region_type]; @@ -387,7 +386,7 @@ static const char *region_name(unsigned int region_type) { if (region_type >= max_regions) { fprintf(stderr, "Invalid region type.\n"); - exit (EXIT_FAILURE); + exit(EXIT_FAILURE); } return region_names[region_type].pretty; @@ -452,7 +451,7 @@ static int max_regions_from_fdbar(const struct fdbar *fdb) * 4 bytes of space. */ if (sorted[i] == frba) - return MIN((sorted[i+1] - sorted[i])/4, MAX_REGIONS); + return MIN((sorted[i + 1] - sorted[i]) / 4, MAX_REGIONS); } /* Never reaches this point */ return 0; @@ -717,7 +716,7 @@ static void dump_fcba(const struct fcba *fcba, const struct fpsba *fpsba) printf("\nFound Component Section\n"); printf("FLCOMP 0x%08x\n", fcba->flcomp); printf(" Dual Output Fast Read Support: %ssupported\n", - (fcba->flcomp & (1 << 30))?"":"not "); + (fcba->flcomp & (1 << 30)) ? "" : "not "); printf(" Read ID/Read Status Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 27) & 7); printf("\n Write/Erase Clock Frequency: "); @@ -725,7 +724,7 @@ static void dump_fcba(const struct fcba *fcba, const struct fpsba *fpsba) printf("\n Fast Read Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 21) & 7); printf("\n Fast Read Support: %ssupported", - (fcba->flcomp & (1 << 20))?"":"not "); + (fcba->flcomp & (1 << 20)) ? "" : "not "); if (is_platform_with_100x_series_pch() && chipset != CHIPSET_100_200_SERIES_SUNRISE_POINT) { printf("\n Read eSPI/EC Bus Frequency: "); @@ -977,7 +976,7 @@ static void dump_vscc(uint32_t vscc) static void dump_vtba(const struct vtba *vtba, int vtl) { int i; - int max_len = sizeof(struct vtba)/sizeof(struct vscc); + int max_len = sizeof(struct vtba) / sizeof(struct vscc); int num = (vtl >> 1) < max_len ? (vtl >> 1) : max_len; printf("ME VSCC table:\n"); @@ -997,10 +996,10 @@ static void dump_oem(const uint8_t *oem) for (i = 0; i < 4; i++) { printf("%02x:", i << 4); for (j = 0; j < 16; j++) - printf(" %02x", oem[(i<<4)+j]); - printf ("\n"); + printf(" %02x", oem[(i << 4) + j]); + printf("\n"); } - printf ("\n"); + printf("\n"); } static void dump_fd(char *image, int size) @@ -1124,11 +1123,11 @@ static void create_fmap_template(char *image, int size, const char *layout_fname sorted_regions[count_regions] = region; // basically insertion sort - for (int i = count_regions-1; i >= 0 ; i--) { - if (sorted_regions[i].base > sorted_regions[i+1].base) { + for (int i = count_regions - 1; i >= 0; i--) { + if (sorted_regions[i].base > sorted_regions[i + 1].base) { struct region tmp = sorted_regions[i]; - sorted_regions[i] = sorted_regions[i+1]; - sorted_regions[i+1] = tmp; + sorted_regions[i] = sorted_regions[i + 1]; + sorted_regions[i + 1] = tmp; } } count_regions++; @@ -1858,8 +1857,8 @@ static void fpsba_set_altmedisable(struct fpsba *fpsba, struct fmsba *fmsba, boo { if (ifd_version >= IFD_VERSION_2) { printf("%sting the HAP bit to %s Intel ME...\n", - altmedisable?"Set":"Unset", - altmedisable?"disable":"enable"); + altmedisable ? "Set" : "Unset", + altmedisable ? "disable" : "enable"); if (altmedisable) fpsba->pchstrp[0] |= (1 << 16); else @@ -1868,8 +1867,8 @@ static void fpsba_set_altmedisable(struct fpsba *fpsba, struct fmsba *fmsba, boo if (chipset >= CHIPSET_ICH8 && chipset <= CHIPSET_ICH10) { printf("%sting the ICH_MeDisable, MCH_MeDisable, " "and MCH_AltMeDisable to %s Intel ME...\n", - altmedisable?"Set":"Unset", - altmedisable?"disable":"enable"); + altmedisable ? "Set" : "Unset", + altmedisable ? "disable" : "enable"); if (altmedisable) { /* MCH_MeDisable */ fmsba->data[0] |= 1; @@ -1884,8 +1883,8 @@ static void fpsba_set_altmedisable(struct fpsba *fpsba, struct fmsba *fmsba, boo } } else { printf("%sting the AltMeDisable to %s Intel ME...\n", - altmedisable?"Set":"Unset", - altmedisable?"disable":"enable"); + altmedisable ? "Set" : "Unset", + altmedisable ? "disable" : "enable"); if (altmedisable) fpsba->pchstrp[10] |= (1 << 7); else @@ -2570,7 +2569,7 @@ int main(int argc, char *argv[]) // generate new filename if (new_filename == NULL) { - new_filename = (char *) malloc((strlen(filename) + 5) * sizeof(char)); + new_filename = (char *)malloc((strlen(filename) + 5) * sizeof(char)); if (!new_filename) { printf("Out of memory.\n"); exit(EXIT_FAILURE);