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emit_utils.c
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emit_utils.c
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/* **********************************************************
* Copyright (c) 2010-2022 Google, Inc. All rights reserved.
* Copyright (c) 2000-2010 VMware, Inc. All rights reserved.
* **********************************************************/
/*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of VMware, Inc. nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL VMWARE, INC. OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*/
/* Copyright (c) 2003-2007 Determina Corp. */
/* Copyright (c) 2001-2003 Massachusetts Institute of Technology */
/* Copyright (c) 2000-2001 Hewlett-Packard Company */
/* file "emit_utils.c"
* The Pentium processors maintain cache consistency in hardware, so we don't
* worry about getting stale cache entries.
*/
#include "../globals.h"
#include "../fragment.h"
#include "../fcache.h"
#include "arch.h"
#include "instr.h"
#include "instr_create_shared.h"
#include "instrlist.h"
#include "instrument.h" /* for dr_insert_call() */
#include "decode_private.h"
#define PRE instrlist_meta_preinsert
#define APP instrlist_meta_append
/***************************************************************************/
/* EXIT STUB */
/***************************************************************************/
/*
direct branch exit_stub:
5x8 mov %xax, xax_offs(&dcontext) or tls
<we used to support PROFILE_LINKCOUNT with a counter inc here but no more>
5x10 mov &linkstub, %xax
5 jmp target addr
indirect branch exit_stub (only used if -indirect_stubs):
6x9 mov %xbx, xbx_offs(&dcontext) or tls
5x11 mov &linkstub, %xbx
5 jmp indirect_branch_lookup
indirect branches use xbx so that the flags can be saved into xax using
the lahf instruction!
xref PR 249775 on lahf support on x64.
also see emit_inline_ibl_stub() below
*/
/* macro to make it easier to get offsets of fields that are in
* a different memory space with self-protection
*/
#define UNPROT_OFFS(dcontext, offs) \
(TEST(SELFPROT_DCONTEXT, dynamo_options.protect_mask) \
? (((ptr_uint_t)((dcontext)->upcontext.separate_upcontext)) + (offs)) \
: (((ptr_uint_t)(dcontext)) + (offs)))
/* The write that inserts the relative target is done atomically so this
* function is safe with respect to a thread executing the code containing
* this target, presuming that the code in both the before and after states
* is valid, and that [pc, pc+4) does not cross a cache line.
* For x64 this routine only works for 32-bit reachability. If further
* reach is needed the caller must use indirection. Xref PR 215395.
*/
byte *
insert_relative_target(byte *pc, cache_pc target, bool hot_patch)
{
/* insert 4-byte pc-relative offset from the beginning of the next instruction
*/
int value = (int)(ptr_int_t)(target - pc - 4);
IF_X64(ASSERT(CHECK_TRUNCATE_TYPE_int(target - pc - 4)));
ATOMIC_4BYTE_WRITE(vmcode_get_writable_addr(pc), value, hot_patch);
pc += 4;
return pc;
}
byte *
insert_relative_jump(byte *pc, cache_pc target, bool hot_patch)
{
int value;
ASSERT(pc != NULL);
*(vmcode_get_writable_addr(pc)) = JMP_OPCODE;
pc++;
/* test that we aren't crossing a cache line boundary */
CHECK_JMP_TARGET_ALIGNMENT(pc, 4, hot_patch);
/* We don't need to be atomic, so don't use insert_relative_target. */
value = (int)(ptr_int_t)(target - pc - 4);
IF_X64(ASSERT(CHECK_TRUNCATE_TYPE_int(target - pc - 4)));
*(int *)(vmcode_get_writable_addr(pc)) = value;
pc += 4;
return pc;
}
bool
exit_cti_reaches_target(dcontext_t *dcontext, fragment_t *f, linkstub_t *l,
cache_pc target_pc)
{
/* Our reachability model assumes cache is all self-reachable */
return true;
}
void
patch_stub(fragment_t *f, cache_pc stub_pc, cache_pc target_pc, cache_pc target_prefix_pc,
bool hot_patch)
{
/* x86 doesn't use this approach to linking */
ASSERT_NOT_REACHED();
}
bool
stub_is_patched(dcontext_t *dcontext, fragment_t *f, cache_pc stub_pc)
{
/* x86 doesn't use this approach to linking */
return false;
}
void
unpatch_stub(dcontext_t *dcontext, fragment_t *f, cache_pc stub_pc, bool hot_patch)
{
/* x86 doesn't use this approach to linking: nothing to do */
}
/* Patch the (direct) branch at branch_pc so it branches to target_pc
* The write that actually patches the branch is done atomically so this
* function is safe with respect to a thread executing this branch presuming
* that both the before and after targets are valid and that [pc, pc+4) does
* not cross a cache line.
*/
void
patch_branch(dr_isa_mode_t isa_mode, cache_pc branch_pc, cache_pc target_pc,
bool hot_patch)
{
cache_pc byte_ptr = exit_cti_disp_pc(branch_pc);
insert_relative_target(byte_ptr, target_pc, hot_patch);
}
/* Checks patchable exit cti for proper alignment for patching. If it's
* properly aligned returns 0, else returns the number of bytes it would
* need to be forward shifted to be properly aligned */
uint
patchable_exit_cti_align_offs(dcontext_t *dcontext, instr_t *inst, cache_pc pc)
{
/* all our exit cti's currently use 4 byte offsets */
/* FIXME : would be better to use a instr_is_cti_long or some such
* also should check for addr16 flag (we shouldn't have any prefixes) */
ASSERT((instr_is_cti(inst) && !instr_is_cti_short(inst) &&
!TESTANY(~(PREFIX_JCC_TAKEN | PREFIX_JCC_NOT_TAKEN | PREFIX_PRED_MASK),
instr_get_prefixes(inst))) ||
instr_is_cti_short_rewrite(inst, NULL));
IF_X64(ASSERT(CHECK_TRUNCATE_TYPE_uint(
ALIGN_SHIFT_SIZE(pc + instr_length(dcontext, inst) - CTI_PATCH_SIZE,
CTI_PATCH_SIZE, PAD_JMPS_ALIGNMENT))));
return (uint)ALIGN_SHIFT_SIZE(pc + instr_length(dcontext, inst) - CTI_PATCH_SIZE,
CTI_PATCH_SIZE, PAD_JMPS_ALIGNMENT);
}
/* make sure to keep in sync w/ instr_raw_is_tls_spill() */
static cache_pc
insert_spill_or_restore(dcontext_t *dcontext, cache_pc pc, uint flags, bool spill,
bool shared, reg_id_t reg, ushort tls_offs, uint dc_offs,
bool require_addr16)
{
DEBUG_DECLARE(cache_pc start_pc;)
pc = vmcode_get_writable_addr(pc);
IF_DEBUG(start_pc = pc);
byte opcode = ((reg == REG_XAX) ? (spill ? MOV_XAX2MEM_OPCODE : MOV_MEM2XAX_OPCODE)
: (spill ? MOV_REG2MEM_OPCODE : MOV_MEM2REG_OPCODE));
#ifdef X64
/* for x64, shared and private fragments all use tls, even for 32-bit code */
shared = true;
if (!FRAG_IS_32(flags)) {
/* mov %rbx, gs:os_tls_offset(tls_offs) */
if (reg == REG_XAX) {
/* shorter to use 0xa3 w/ addr32 prefix than 0x89/0x8b w/ sib byte */
/* FIXME: PR 209709: test perf and remove if outweighs space */
*pc = ADDR_PREFIX_OPCODE;
pc++;
}
*pc = TLS_SEG_OPCODE;
pc++;
*pc = REX_PREFIX_BASE_OPCODE | REX_PREFIX_W_OPFLAG;
pc++;
*pc = opcode;
pc++;
if (reg != REG_XAX) {
/* 0x1c for rbx, 0x0c for rcx, 0x04 for rax */
*pc = MODRM_BYTE(0 /*mod*/, reg_get_bits(reg), 4 /*rm*/);
pc++;
*pc = SIB_DISP32;
pc++; /* sib byte: abs addr */
}
*((uint *)pc) = (uint)os_tls_offset(tls_offs);
pc += 4;
} else
#endif /* X64 */
if (shared) {
/* mov %ebx, fs:os_tls_offset(tls_offs) */
/* trying hard to keep the size of the stub 5 for eax, 6 else */
/* FIXME: case 5231 when staying on trace space is better,
* when going through this to the IBL routine speed asks for
* not adding the prefix.
*/
bool addr16 = (require_addr16 || use_addr_prefix_on_short_disp());
if (addr16) {
*pc = ADDR_PREFIX_OPCODE;
pc++;
}
*pc = TLS_SEG_OPCODE;
pc++;
*pc = opcode;
pc++;
if (reg != REG_XAX) {
/* 0x1e for ebx, 0x0e for ecx, 0x06 for eax
* w/o addr16 those are 0x1d, 0x0d, 0x05
*/
*pc = MODRM_BYTE(0 /*mod*/, reg_get_bits(reg), addr16 ? 6 : 5 /*rm*/);
pc++;
}
if (addr16) {
*((ushort *)pc) = os_tls_offset(tls_offs);
pc += 2;
} else {
*((uint *)pc) = os_tls_offset(tls_offs);
pc += 4;
}
} else {
/* mov %ebx,((int)&dcontext)+dc_offs */
*pc = opcode;
pc++;
if (reg != REG_XAX) {
/* 0x1d for ebx, 0x0d for ecx, 0x05 for eax */
*pc = MODRM_BYTE(0 /*mod*/, reg_get_bits(reg), 5 /*rm*/);
pc++;
}
IF_X64(ASSERT_NOT_IMPLEMENTED(false));
*((uint *)pc) = (uint)(ptr_uint_t)UNPROT_OFFS(dcontext, dc_offs);
pc += 4;
}
ASSERT(IF_X64_ELSE(false, !shared) ||
(pc - start_pc) ==
(reg == REG_XAX ? SIZE_MOV_XAX_TO_TLS(flags, require_addr16)
: SIZE_MOV_XBX_TO_TLS(flags, require_addr16)));
ASSERT(IF_X64_ELSE(false, !shared) || !spill || reg == REG_XAX ||
instr_raw_is_tls_spill(start_pc, reg, tls_offs));
return vmcode_get_executable_addr(pc);
}
/* instr_raw_is_tls_spill() matches the exact sequence of bytes inserted here */
static byte *
insert_jmp_to_ibl(byte *pc, fragment_t *f, linkstub_t *l, cache_pc exit_target,
dcontext_t *dcontext)
{
#ifdef WINDOWS
bool spill_xbx_to_fs = FRAG_DB_SHARED(f->flags) ||
(is_shared_syscall_routine(dcontext, exit_target) &&
DYNAMO_OPTION(shared_fragment_shared_syscalls));
#else
bool spill_xbx_to_fs = FRAG_DB_SHARED(f->flags);
#endif
ASSERT(linkstub_owned_by_fragment(dcontext, f, l));
/* we use XBX to hold the linkstub pointer for IBL routines,
note that direct stubs use XAX for linkstub pointer */
#ifdef WINDOWS
if (INTERNAL_OPTION(shared_syscalls_fastpath) &&
is_shared_syscall_routine(dcontext, exit_target)) {
/* jmp <exit_target> */
pc = insert_relative_jump(pc, exit_target, NOT_HOT_PATCHABLE);
return pc;
} else
#endif
pc = insert_spill_or_restore(dcontext, pc, f->flags, true /*spill*/,
spill_xbx_to_fs, REG_XBX, INDIRECT_STUB_SPILL_SLOT,
XBX_OFFSET, true);
/* Switch to the writable view for the raw stores below. */
pc = vmcode_get_writable_addr(pc);
/* mov $linkstub_ptr,%xbx */
#ifdef X64
if (!FRAG_IS_32(f->flags)) {
*pc = REX_PREFIX_BASE_OPCODE | REX_PREFIX_W_OPFLAG;
pc++;
}
#endif
*pc = MOV_IMM2XBX_OPCODE;
pc++;
#ifdef WINDOWS
if (DYNAMO_OPTION(shared_syscalls) &&
is_shared_syscall_routine(dcontext, exit_target)) {
/* FIXME We could reduce mem usage by not allocating a linkstub for
* this exit since it's never referenced.
*/
LOG(THREAD, LOG_LINKS, 4, "\tF%d using %s shared syscalls link stub\n", f->id,
TEST(FRAG_IS_TRACE, f->flags) ? "trace" : "bb");
l = (linkstub_t *)(TEST(FRAG_IS_TRACE, f->flags)
? get_shared_syscalls_trace_linkstub()
: get_shared_syscalls_bb_linkstub());
}
#endif
if (TEST(FRAG_COARSE_GRAIN, f->flags)) {
/* FIXME: once we separate these we should switch to 15-byte w/
* store-to-mem instead of in a spilled xbx, to use same
* slots as coarse direct stubs
*/
/* There is no linkstub_t so we store source tag instead */
*((ptr_uint_t *)pc) = (ptr_uint_t)f->tag;
pc += sizeof(f->tag);
/* FIXME: once we separate the indirect stubs out we will need
* a 15-byte stub . For that we should simply store the
* source cti directly into a tls slot. For now though we inline
* the stubs and spill xbx.
*/
} else {
*((ptr_uint_t *)pc) = (ptr_uint_t)l;
pc += sizeof(l);
}
pc = vmcode_get_executable_addr(pc);
/* jmp <exit_target> */
pc = insert_relative_jump(pc, exit_target, NOT_HOT_PATCHABLE);
return pc;
}
/* inserts any nop padding needed to ensure patchable branch offsets don't
* cross cache line boundaries. If emitting sets the offset field of all
* instructions, else sets the translation for the added nops (for
* recreating). If emitting and -pad_jmps_shift_{bb,trace} returns the number
* of bytes to shift the start_pc by (this avoids putting a nop before the
* first exit cti) else returns 0.
*/
uint
nop_pad_ilist(dcontext_t *dcontext, fragment_t *f, instrlist_t *ilist, bool emitting)
{
instr_t *inst;
uint offset = 0;
int first_patch_offset = -1;
uint start_shift = 0;
/* if emitting prefix_size isn't set up yet */
cache_pc starting_pc = f->start_pc + fragment_prefix_size(f->flags);
ASSERT(emitting || f->prefix_size == fragment_prefix_size(f->flags));
ASSERT(PAD_FRAGMENT_JMPS(f->flags)); /* shouldn't call this otherwise */
for (inst = instrlist_first(ilist); inst != NULL; inst = instr_get_next(inst)) {
/* don't support non exit cti patchable instructions yet */
ASSERT_NOT_IMPLEMENTED(!TEST(INSTR_HOT_PATCHABLE, inst->flags));
if (instr_is_exit_cti(inst)) {
/* see if we need to be able to patch this instruction */
if (is_exit_cti_patchable(dcontext, inst, f->flags)) {
/* See if we are crossing a cache line. Offset is the start of
* the current instr.
*/
uint nop_length =
patchable_exit_cti_align_offs(dcontext, inst, starting_pc + offset);
LOG(THREAD, LOG_INTERP, 4, "%s: F%d @" PFX " cti shift needed: %d\n",
__FUNCTION__, f->id, starting_pc + offset, nop_length);
if (first_patch_offset < 0)
first_patch_offset = offset;
if (nop_length > 0) {
/* crosses cache line, nop pad */
/* instead of inserting a nop, shift the starting pc if
* we are within 1 cache line of the first patchable offset
* (this covers the case of a conditional branch which
* mangles to two patchable exits and is still safe since
* they are less then a cache line apart) */
if (PAD_JMPS_SHIFT_START(f->flags) &&
offset + instr_length(dcontext, inst) - first_patch_offset <
PAD_JMPS_ALIGNMENT) {
ASSERT(start_shift == 0); /* should only shift once */
start_shift = nop_length;
/* adjust the starting_pc, all previously checked
* instructions should be fine since we are still
* within the same cache line as the first patchable
* offset */
starting_pc += nop_length;
} else {
instr_t *nop_inst = INSTR_CREATE_nopNbyte(dcontext, nop_length);
#ifdef X64
if (FRAG_IS_32(f->flags)) {
instr_set_x86_mode(nop_inst, true /*x86*/);
instr_shrink_to_32_bits(nop_inst);
}
#endif
LOG(THREAD, LOG_INTERP, 4,
"Marking exit branch as having nop padding\n");
instr_branch_set_padded(inst, true);
instrlist_preinsert(ilist, inst, nop_inst);
/* sanity check */
ASSERT((int)nop_length == instr_length(dcontext, nop_inst));
if (emitting) {
/* fixup offsets */
nop_inst->offset = offset;
/* only inc stats for emitting, not for recreating */
STATS_PAD_JMPS_ADD(f->flags, num_nops, 1);
STATS_PAD_JMPS_ADD(f->flags, nop_bytes, nop_length);
}
/* set translation whether emitting or not */
instr_set_translation(nop_inst, instr_get_translation(inst));
instr_set_our_mangling(nop_inst, true);
offset += nop_length;
}
/* sanity check that we fixed the alignment */
ASSERT(patchable_exit_cti_align_offs(dcontext, inst,
starting_pc + offset) == 0);
} else {
DOSTATS({
/* only inc stats for emitting, not for recreating */
if (emitting)
STATS_PAD_JMPS_ADD(f->flags, num_no_pad_exits, 1);
});
}
}
}
if (emitting)
inst->offset = offset; /* used by instr_encode */
offset += instr_length(dcontext, inst);
}
return start_shift;
}
static cache_pc
insert_save_xax(dcontext_t *dcontext, cache_pc pc, uint flags, bool shared,
ushort tls_offs, bool require_addr16)
{
return insert_spill_or_restore(dcontext, pc, flags, true /*spill*/, shared, REG_XAX,
tls_offs, XAX_OFFSET, require_addr16);
}
/* restore xax in a stub or a fragment prefix */
static cache_pc
insert_restore_xax(dcontext_t *dcontext, cache_pc pc, uint flags, bool shared,
ushort tls_offs, bool require_addr16)
{
return insert_spill_or_restore(dcontext, pc, flags, false /*restore*/, shared,
REG_XAX, tls_offs, XAX_OFFSET, require_addr16);
}
/* for the hashtable lookup inlined into exit stubs, the
* lookup routine is encoded earlier into a template,
* (in the routine emit_inline_ibl_stub(), below)
* which we copy here and fix up the linkstub ptr for.
* when the hashtable changes, the mask and table are
* updated in update_indirect_exit_stub(), below.
*/
static byte *
insert_inlined_ibl(dcontext_t *dcontext, fragment_t *f, linkstub_t *l, byte *pc,
cache_pc unlinked_exit_target, uint flags)
{
ibl_code_t *ibl_code =
get_ibl_routine_code(dcontext, extract_branchtype(l->flags), f->flags);
byte *start_pc = pc;
cache_pc linked_exit_target = get_linked_entry(dcontext, unlinked_exit_target);
/* PR 248207: haven't updated the inlining to be x64-compliant yet */
IF_X64(ASSERT_NOT_IMPLEMENTED(false));
ASSERT(linkstub_owned_by_fragment(dcontext, f, l));
ASSERT(ibl_code->ibl_head_is_inlined);
ASSERT(EXIT_HAS_STUB(l->flags, f->flags));
memcpy(start_pc, ibl_code->inline_ibl_stub_template, ibl_code->inline_stub_length);
/* exit should be unlinked initially */
patch_branch(FRAG_ISA_MODE(f->flags), EXIT_CTI_PC(f, l),
start_pc + ibl_code->inline_unlink_offs, NOT_HOT_PATCHABLE);
if (DYNAMO_OPTION(indirect_stubs)) {
/* fixup linked/unlinked targets */
if (DYNAMO_OPTION(atomic_inlined_linking)) {
insert_relative_target(start_pc + ibl_code->inline_linkedjmp_offs,
linked_exit_target, NOT_HOT_PATCHABLE);
insert_relative_target(start_pc + ibl_code->inline_unlinkedjmp_offs,
unlinked_exit_target, NOT_HOT_PATCHABLE);
} else {
insert_relative_target(start_pc + ibl_code->inline_linkedjmp_offs,
unlinked_exit_target, NOT_HOT_PATCHABLE);
}
/* set the linkstub ptr */
pc = start_pc + ibl_code->inline_linkstub_first_offs;
IF_X64(ASSERT_NOT_IMPLEMENTED(false));
*((uint *)vmcode_get_writable_addr(pc)) = (uint)(ptr_uint_t)l;
if (DYNAMO_OPTION(atomic_inlined_linking)) {
pc = start_pc + ibl_code->inline_linkstub_second_offs;
IF_X64(ASSERT_NOT_IMPLEMENTED(false));
*((uint *)vmcode_get_writable_addr(pc)) = (uint)(ptr_uint_t)l;
}
} else {
insert_relative_target(start_pc + ibl_code->inline_linkedjmp_offs,
linked_exit_target, NOT_HOT_PATCHABLE);
insert_relative_target(
start_pc + ibl_code->inline_unlink_offs +
1 /* skip jmp opcode: see emit_inline_ibl_stub FIXME */,
unlinked_exit_target, NOT_HOT_PATCHABLE);
}
return start_pc + ibl_code->inline_stub_length;
}
/* Emit code for the exit stub at stub_pc. Return the size of the
* emitted code in bytes. This routine assumes that the caller will
* take care of any cache synchronization necessary (though none is
* necessary on the Pentium).
* The stub is unlinked initially, except coarse grain indirect exits,
* which are always linked.
*/
int
insert_exit_stub_other_flags(dcontext_t *dcontext, fragment_t *f, linkstub_t *l,
cache_pc stub_pc, ushort l_flags)
{
byte *pc = (byte *)stub_pc;
cache_pc exit_target;
bool indirect = false;
bool can_inline = true;
ASSERT(linkstub_owned_by_fragment(dcontext, f, l));
/* select the correct exit target */
if (LINKSTUB_DIRECT(l_flags)) {
if (TEST(FRAG_COARSE_GRAIN, f->flags)) {
/* need to target the fcache return prefix */
exit_target = fcache_return_coarse_prefix(stub_pc, NULL);
ASSERT(exit_target != NULL);
} else
exit_target = get_direct_exit_target(dcontext, f->flags);
} else {
ASSERT(LINKSTUB_INDIRECT(l_flags));
/* caller shouldn't call us if no stub */
ASSERT(EXIT_HAS_STUB(l_flags, f->flags));
if (TEST(FRAG_COARSE_GRAIN, f->flags)) {
/* need to target the ibl prefix */
exit_target =
get_coarse_ibl_prefix(dcontext, stub_pc, extract_branchtype(l_flags));
ASSERT(exit_target != NULL);
} else {
/* initially, stub should be unlinked */
exit_target = get_unlinked_entry(dcontext, EXIT_TARGET_TAG(dcontext, f, l));
}
indirect = true;
#ifdef WINDOWS
can_inline = (exit_target != unlinked_shared_syscall_routine(dcontext));
#endif
if (can_inline) {
ibl_code_t *ibl_code =
get_ibl_routine_code(dcontext, extract_branchtype(l_flags), f->flags);
if (!ibl_code->ibl_head_is_inlined)
can_inline = false;
}
}
if (indirect && can_inline) {
pc = insert_inlined_ibl(dcontext, f, l, pc, exit_target, f->flags);
IF_X64(ASSERT(CHECK_TRUNCATE_TYPE_int(pc - stub_pc)));
return (int)(pc - stub_pc);
}
if (indirect) {
pc = insert_jmp_to_ibl(pc, f, l, exit_target, dcontext);
} else if (TEST(FRAG_COARSE_GRAIN, f->flags)) {
/* This is an entrance stub. It may be executed even when linked,
* so we store target info to memory instead of a register.
* The exact bytes used here are assumed by entrance_stub_target_tag().
*/
#ifdef X64
if (!FRAG_IS_32(f->flags)) {
app_pc tgt = EXIT_TARGET_TAG(dcontext, f, l);
/* Both entrance_stub_target_tag() and coarse_indirect_stub_jmp_target()
* assume that the addr prefix is present for 32-bit but not 64-bit.
*/
pc = vmcode_get_writable_addr(pc);
/* since we have no 8-byte-immed-to-memory, we split into two pieces */
*pc = TLS_SEG_OPCODE;
pc++;
*pc = MOV_IMM2MEM_OPCODE;
pc++;
*pc = MODRM_BYTE(0 /*mod*/, 0 /*reg*/, 4 /*rm*/);
pc++; /* => no base, w/ sib */
*pc = SIB_DISP32;
pc++; /* just disp32 */
/* low 32 bits */
*((uint *)pc) = (uint)os_tls_offset(DIRECT_STUB_SPILL_SLOT);
pc += 4;
*((uint *)pc) = (uint)(ptr_uint_t)tgt;
pc += 4;
*pc = TLS_SEG_OPCODE;
pc++;
*pc = MOV_IMM2MEM_OPCODE;
pc++;
*pc = MODRM_BYTE(0 /*mod*/, 0 /*reg*/, 4 /*rm*/);
pc++; /* => no base, w/ sib */
*pc = SIB_DISP32;
pc++; /* just disp32 */
/* high 32 bits */
*((uint *)pc) = 4 + (uint)os_tls_offset(DIRECT_STUB_SPILL_SLOT);
pc += 4;
*((uint *)pc) = (uint)(((ptr_uint_t)tgt) >> 32);
pc += 4;
pc = vmcode_get_executable_addr(pc);
} else {
#endif /* X64 */
/* We must be at or below 15 bytes so we require addr16.
* Both entrance_stub_target_tag() and coarse_indirect_stub_jmp_target()
* assume that the addr prefix is present for 32-bit but not 64-bit.
*/
pc = vmcode_get_writable_addr(pc);
/* addr16 mov <target>, fs:<dir-stub-spill> */
/* FIXME: PR 209709: test perf and remove if outweighs space */
*pc = ADDR_PREFIX_OPCODE;
pc++;
*pc = TLS_SEG_OPCODE;
pc++;
*pc = MOV_IMM2MEM_OPCODE;
pc++;
*pc = MODRM16_DISP16;
pc++;
*((ushort *)pc) = os_tls_offset(DIRECT_STUB_SPILL_SLOT);
pc += 2;
*((uint *)pc) = (uint)(ptr_uint_t)EXIT_TARGET_TAG(dcontext, f, l);
pc += 4;
pc = vmcode_get_executable_addr(pc);
#ifdef X64
}
#endif /* X64 */
/* jmp to exit target */
pc = insert_relative_jump(pc, exit_target, NOT_HOT_PATCHABLE);
} else {
/* direct branch */
/* we use XAX to hold the linkstub pointer before we get to fcache_return,
note that indirect stubs use XBX for linkstub pointer */
pc = insert_save_xax(dcontext, pc, f->flags, FRAG_DB_SHARED(f->flags),
DIRECT_STUB_SPILL_SLOT, true);
/* mov $linkstub_ptr,%xax */
#ifdef X64
if (FRAG_IS_32(f->flags)) {
/* XXX i#829: we only support stubs in the low 4GB which is ok for
* WOW64 mixed-mode but long-term for 64-bit flexibility (i#774) we
* may need to store the other half of the pointer somewhere
*/
uint l_uint;
ASSERT_TRUNCATE(l_uint, uint, (ptr_uint_t)l);
l_uint = (uint)(ptr_uint_t)l;
*(vmcode_get_writable_addr(pc)) = MOV_IMM2XAX_OPCODE;
pc++;
*((uint *)vmcode_get_writable_addr(pc)) = l_uint;
pc += sizeof(l_uint);
} else {
*(vmcode_get_writable_addr(pc)) =
REX_PREFIX_BASE_OPCODE | REX_PREFIX_W_OPFLAG;
pc++;
#endif
/* shared w/ 32-bit and 64-bit !FRAG_IS_32 */
*(vmcode_get_writable_addr(pc)) = MOV_IMM2XAX_OPCODE;
pc++;
*((ptr_uint_t *)vmcode_get_writable_addr(pc)) = (ptr_uint_t)l;
pc += sizeof(l);
#ifdef X64
}
#endif
/* jmp to exit target */
pc = insert_relative_jump(pc, exit_target, NOT_HOT_PATCHABLE);
}
IF_X64(ASSERT(CHECK_TRUNCATE_TYPE_int(pc - stub_pc)));
return (int)(pc - stub_pc);
}
cache_pc
exit_cti_disp_pc(cache_pc branch_pc)
{
cache_pc byte_ptr = branch_pc;
byte opcode = *byte_ptr;
uint length = 0;
if (opcode == RAW_PREFIX_jcc_taken || opcode == RAW_PREFIX_jcc_not_taken) {
length++;
byte_ptr++;
opcode = *byte_ptr;
/* branch hints are only valid with jcc instrs, and if present on
* other ctis we strip them out during mangling (i#435)
*/
ASSERT(opcode == RAW_OPCODE_jcc_byte1);
}
if (opcode == ADDR_PREFIX_OPCODE) { /* used w/ jecxz/loop* */
length++;
byte_ptr++;
opcode = *byte_ptr;
}
if (opcode >= RAW_OPCODE_loop_start && opcode <= RAW_OPCODE_loop_end) {
/* assume that this is a mangled jcxz/loop*
* target pc is in last 4 bytes of "9-byte instruction"
*/
length += CTI_SHORT_REWRITE_LENGTH;
} else if (opcode == RAW_OPCODE_jcc_byte1) {
/* 2-byte opcode, 6-byte instruction, except for branch hint */
ASSERT(*(byte_ptr + 1) >= RAW_OPCODE_jcc_byte2_start &&
*(byte_ptr + 1) <= RAW_OPCODE_jcc_byte2_end);
length += CBR_LONG_LENGTH;
} else {
/* 1-byte opcode, 5-byte instruction */
#ifdef HOT_PATCHING_INTERFACE
ASSERT(opcode == RAW_OPCODE_jmp || opcode == RAW_OPCODE_call);
#else
ASSERT(opcode == RAW_OPCODE_jmp);
#endif
length += JMP_LONG_LENGTH;
}
return branch_pc + length - 4; /* disp is 4 even on x64 */
}
/* NOTE : for inlined indirect branches linking is !NOT! atomic with respect
* to a thread executing in the cache unless using the atomic_inlined_linking
* option (unlike unlinking)
*/
void
link_indirect_exit_arch(dcontext_t *dcontext, fragment_t *f, linkstub_t *l,
bool hot_patch, app_pc target_tag)
{
uint stub_size;
app_pc exit_target, cur_target, pc;
/* w/ indirect exits now having their stub pcs computed based
* on the cti targets, we must calculate them at a consistent
* state (we do have multi-stage modifications for inlined stubs)
*/
byte *stub_pc = (byte *)EXIT_STUB_PC(dcontext, f, l);
if (DYNAMO_OPTION(indirect_stubs)) {
/* go to start of 5-byte jump instruction at end of exit stub */
stub_size = exit_stub_size(dcontext, target_tag, f->flags);
pc = stub_pc + stub_size - 5;
} else {
/* cti goes straight to ibl, and must be a jmp, not jcc,
* except for -unsafe_ignore_eflags_trace stay-on-trace cmp,jne
*/
pc = EXIT_CTI_PC(f, l);
/* for x64, or -unsafe_ignore_eflags_trace, a trace may have a jne to the stub */
if (*pc == JNE_OPCODE_1) {
ASSERT(TEST(FRAG_IS_TRACE, f->flags));
#ifndef X64
ASSERT(INTERNAL_OPTION(unsafe_ignore_eflags_trace));
#endif
/* FIXME: share this code w/ common path below: 1 opcode byte vs 2 */
/* get absolute address of target */
cur_target = (app_pc)PC_RELATIVE_TARGET(pc + 2);
exit_target = get_linked_entry(dcontext, cur_target);
pc += 2; /* skip jne opcode */
pc = insert_relative_target(pc, exit_target, hot_patch);
return;
} else {
ASSERT(*pc == JMP_OPCODE);
}
}
/* get absolute address of target */
cur_target = (app_pc)PC_RELATIVE_TARGET(pc + 1);
exit_target = get_linked_entry(dcontext, cur_target);
pc++; /* skip jmp opcode */
pc = insert_relative_target(pc, exit_target, hot_patch);
}
cache_pc
indirect_linkstub_stub_pc(dcontext_t *dcontext, fragment_t *f, linkstub_t *l)
{
cache_pc cti = EXIT_CTI_PC(f, l);
/* decode the cti: it should be a relative jmp to the stub */
cache_pc stub;
if (!EXIT_HAS_STUB(l->flags, f->flags))
return NULL;
/* for x64, or -unsafe_ignore_eflags_trace, a trace may have a jne to the stub */
if (*cti == JNE_OPCODE_1) {
ASSERT(TEST(FRAG_IS_TRACE, f->flags));
#ifndef X64
ASSERT(INTERNAL_OPTION(unsafe_ignore_eflags_trace));
#endif
stub = (cache_pc)PC_RELATIVE_TARGET(cti + 2 /*opcode bytes*/);
} else {
if (*cti == JMP_OPCODE) {
stub = (cache_pc)PC_RELATIVE_TARGET(cti + 1 /*opcode byte*/);
} else {
/* case 6532/10987: frozen coarse has no jmp to stub */
ASSERT(TEST(FRAG_COARSE_GRAIN, f->flags));
ASSERT(coarse_is_indirect_stub(cti));
stub = cti;
}
}
ASSERT(stub >= cti && (stub - cti) <= MAX_FRAGMENT_SIZE);
if (!TEST(LINK_LINKED, l->flags)) {
/* the unlink target is not always the start of the stub */
stub -= linkstub_unlink_entry_offset(dcontext, f, l);
/* FIXME: for -no_indirect_stubs we could point exit cti directly
* at unlink ibl routine if we could find the stub target for
* linking here...should consider storing stub pc for ind exits
* for that case to save 5 bytes in the inlined stub
*/
}
return stub;
}
/* since we now support branch hints on long cbrs, we need to do a little
* decoding to find their length
*/
cache_pc
cbr_fallthrough_exit_cti(cache_pc prev_cti_pc)
{
if (*prev_cti_pc == RAW_PREFIX_jcc_taken || *prev_cti_pc == RAW_PREFIX_jcc_not_taken)
prev_cti_pc++;
return (prev_cti_pc + CBR_LONG_LENGTH);
}
/* This is an atomic operation with respect to a thread executing in the
* cache (barring ifdef NATIVE_RETURN, which is now removed), for
* inlined indirect exits the
* unlinked path of the ibl routine detects the race condition between the
* two patching writes and handles it appropriately unless using the
* atomic_inlined_linking option in which case there is only one patching
* write (since tail is duplicated) */
void
unlink_indirect_exit(dcontext_t *dcontext, fragment_t *f, linkstub_t *l)
{
uint stub_size;
cache_pc exit_target, cur_target;
app_pc target_tag = EXIT_TARGET_TAG(dcontext, f, l);
byte *pc;
ibl_code_t *ibl_code = NULL;
/* w/ indirect exits now having their stub pcs computed based
* on the cti targets, we must calculate them at a consistent
* state (we do have multi-stage modifications for inlined stubs)
*/
byte *stub_pc = (byte *)EXIT_STUB_PC(dcontext, f, l);
ASSERT(!TEST(FRAG_COARSE_GRAIN, f->flags));
ASSERT(linkstub_owned_by_fragment(dcontext, f, l));
ASSERT(LINKSTUB_INDIRECT(l->flags));
/* target is always the same, so if it's already unlinked, this is a nop */
if (!TEST(LINK_LINKED, l->flags))
return;
#ifdef WINDOWS
if (!is_shared_syscall_routine(dcontext, target_tag)) {
#endif
ibl_code = get_ibl_routine_code(dcontext, extract_branchtype(l->flags), f->flags);
#ifdef WINDOWS
}
#endif
if ((!DYNAMO_OPTION(atomic_inlined_linking) && DYNAMO_OPTION(indirect_stubs)) ||
#ifdef WINDOWS
target_tag ==
shared_syscall_routine_ex(
dcontext _IF_X64(FRAGMENT_GENCODE_MODE(f->flags))) ||
#endif
/* FIXME: for -no_indirect_stubs and inlined ibl, we'd like to directly
* target the unlinked ibl entry but we don't yet -- see FIXME in
* emit_inline_ibl_stub()
*/
!ibl_code->ibl_head_is_inlined) {
if (DYNAMO_OPTION(indirect_stubs)) {
/* go to start of 5-byte jump instruction at end of exit stub */
stub_size = exit_stub_size(dcontext, target_tag, f->flags);
pc = stub_pc + stub_size - 5;
} else {
/* cti goes straight to ibl, and must be a jmp, not jcc */
pc = EXIT_CTI_PC(f, l);
/* for x64, or -unsafe_ignore_eflags_trace, a trace may have a jne */
if (*pc == JNE_OPCODE_1) {
ASSERT(TEST(FRAG_IS_TRACE, f->flags));
#ifndef X64
ASSERT(INTERNAL_OPTION(unsafe_ignore_eflags_trace));
#endif
pc++; /* 2-byte opcode, skip 1st here */
} else
ASSERT(*pc == JMP_OPCODE);
}
cur_target = (cache_pc)PC_RELATIVE_TARGET(pc + 1);
exit_target = get_unlinked_entry(dcontext, cur_target);
pc++; /* skip jmp opcode */
pc = insert_relative_target(pc, exit_target, HOT_PATCHABLE);
}
/* To maintain atomicity with respect to executing thread, must unlink
* the ending jmp (above) first so that the unlinked path can detect the
* race condition case */
#ifdef WINDOWS
/* faster than is_shared_syscall_routine() since only linked target can get here
* yet inconsistent
*/
if (target_tag !=
shared_syscall_routine_ex(dcontext _IF_X64(FRAGMENT_GENCODE_MODE(f->flags)))) {
#endif
/* need to make branch target the unlink entry point inside exit stub */
if (ibl_code->ibl_head_is_inlined) {
cache_pc target = stub_pc;
/* now add offset of unlinked entry */
target += ibl_code->inline_unlink_offs;
patch_branch(FRAG_ISA_MODE(f->flags), EXIT_CTI_PC(f, l), target,
HOT_PATCHABLE);
}
#ifdef WINDOWS
}
#endif
}
/*******************************************************************************
* COARSE-GRAIN FRAGMENT SUPPORT
*/
cache_pc
entrance_stub_jmp(cache_pc stub)
{
#ifdef X64
if (*stub == 0x65)
return (stub + STUB_COARSE_DIRECT_SIZE64 - JMP_LONG_LENGTH);
/* else, 32-bit stub */
#endif
return (stub + STUB_COARSE_DIRECT_SIZE32 - JMP_LONG_LENGTH);
}
/* Returns whether stub is an entrance stub as opposed to a fragment
* or a coarse indirect stub. FIXME: if we separate coarse indirect
* stubs from bodies we'll need to put them somewhere else, or fix up
* decode_fragment() to be able to distinguish them in some other way
* like first instruction tls slot.
*/
bool
coarse_is_entrance_stub(cache_pc stub)
{
bool res = false;
/* FIXME: case 10334: pass in info and if non-NULL avoid lookup here? */
coarse_info_t *info = get_stub_coarse_info(stub);
if (info != NULL) {
res = ALIGNED(stub, coarse_stub_alignment(info)) &&
*entrance_stub_jmp(stub) == JMP_OPCODE;
DOCHECK(1, {
if (res) {
cache_pc tgt = entrance_stub_jmp_target(stub);
ASSERT(!in_fcache(stub));
ASSERT(tgt == trace_head_return_coarse_prefix(stub, info) ||
tgt == fcache_return_coarse_prefix(stub, info) ||
/* another fragment */
in_fcache(tgt));
}
});
}
return res;
}
/*###########################################################################
*
* fragment_t Prefixes
*
* Two types: indirect branch target, which restores eflags and xcx, and
* normal prefix, which just restores xcx
*/
#define IBL_EFLAGS_IN_TLS() (IF_X64_ELSE(true, SHARED_IB_TARGETS()))
/* Indirect Branch Target Prefix
* We have 3 different prefixes: one if we don't need to restore eflags, one
* if we need to restore just using sahf, and one if we also need to restore
* the overflow flag OF.
*
* FIXME: currently we cache-align the prefix, not the normal
* entry point...if prefix gets much longer, might want to add
* nops to get normal entry cache-aligned?
*/
/* for now all ibl targets must use same scratch locations: tls or not, no mixture */
#ifdef X86
# define RESTORE_XAX_PREFIX(flags) \