From 657773fe7887d0df82d97e07e08e72307969ddd9 Mon Sep 17 00:00:00 2001 From: Joshua Warburton Date: Wed, 20 Dec 2023 11:49:52 +0000 Subject: [PATCH 1/3] i#6499: AArch64 codec: mark instructions with governing predicate as predicated This patch adds the DR_PRED_GOVERNING flag to instructions containing any governing predicate registers as well as tagging the governing register with DR_OPND_IS_GOVERNING. To do this, it extends the codec functionalty such that operands may have "flags" which allow us to add some special code generation when they are encountered. In this case we ammend the instr decode/encode functions to both tag the governing predicate and the instr itself. issue: #i6499 Change-Id: If93aedb4036e7ec18b20bb6f56f4297b433737b9 --- core/ir/aarch64/codec.c | 3 +- core/ir/aarch64/codec.py | 67 +- core/ir/aarch64/codec_sve.txt | 1182 ++++++++++++++-------------- core/ir/aarch64/codec_sve2.txt | 150 ++-- core/ir/aarch64/codec_v80.txt | 8 + core/ir/aarch64/disassemble.c | 4 +- core/ir/aarch64/instr_create_api.h | 915 +++++++++++---------- core/ir/instr.h | 14 + core/ir/instr_api.h | 3 + core/ir/instr_inline_api.h | 7 + core/ir/instr_shared.c | 14 + core/ir/opnd_api.h | 43 +- 12 files changed, 1291 insertions(+), 1119 deletions(-) diff --git a/core/ir/aarch64/codec.c b/core/ir/aarch64/codec.c index bb3554062ab..4e078c1145d 100644 --- a/core/ir/aarch64/codec.c +++ b/core/ir/aarch64/codec.c @@ -2406,7 +2406,8 @@ static inline bool encode_float_const_pair(uint pos, float first, float second, opnd_t opnd, OUT uint *enc_out) { - IF_RETURN_FALSE(!opnd_is_immed_float(opnd)) + if (!opnd_is_immed_float(opnd)) + return false; const float value = opnd_get_immed_float(opnd); IF_RETURN_FALSE((value != first) && (value != second)) diff --git a/core/ir/aarch64/codec.py b/core/ir/aarch64/codec.py index a645044f7d0..7098294d1d6 100755 --- a/core/ir/aarch64/codec.py +++ b/core/ir/aarch64/codec.py @@ -68,6 +68,14 @@ def __init__(self, gen, used, must_be_set): self.used = used self.non_zero = must_be_set +def opnd_stem(opnd_name): + """Strip off all flags from the opnd""" + return opnd_name.split(".")[0] + +def opnd_flags(opnd_name): + """Return the opnd's flags""" + return opnd_name.split(".")[1:] + class Opndset: def __init__(self, fixed, dsts, srcs, enc_order): for (ds, i, ot) in enc_order: @@ -138,11 +146,11 @@ def generate_opndset_decoders(opndsettab, opndtab): vars = (['dst%d' % i for i in range(len(dsts))] + ['src%d' % i for i in range(len(srcs))]) tests = (['!decode_opnd_%s(enc & 0x%08x, opcode, pc, &dst%d)' % - (dsts[i], opndtab[dsts[i]].gen | opndtab[dsts[i]].used, i) + (opnd_stem(dsts[i]), opndtab[dsts[i]].gen | opndtab[dsts[i]].used, i) for i in range(len(dsts))] + ['!decode_opnd_%s(enc & 0x%08x, opcode, pc, &src%d)' % - (srcs[i], opndtab[srcs[i]].gen | opndtab[srcs[i]].used, i) + (opnd_stem(srcs[i]), opndtab[srcs[i]].gen | opndtab[srcs[i]].used, i) for i in range(len(srcs))]) c += [' opnd_t ' + ', '.join(vars) + ';'] c += [' if (' + ' ||\n '.join(tests) + ')'] @@ -150,6 +158,11 @@ def generate_opndset_decoders(opndsettab, opndtab): c.append(' instr_set_opcode(instr, opcode);') c.append(' instr_set_num_opnds(dcontext, instr, %d, %d);' % (len(dsts), len(srcs))) + if any("gov" in opnd_flags(op) for op in srcs): + c += [' instr_set_has_register_predication(instr);'] + for i, op in enumerate(srcs): + if "gov" in opnd_flags(op): + c += [' src{0} = opnd_add_flags(src{0}, DR_OPND_IS_GOVERNING);'.format(i)] for i in range(len(dsts)): c.append(' instr_set_dst(instr, %d, dst%d);' % (i, i)) for i in range(len(srcs)): @@ -293,7 +306,7 @@ def make_enc(n, reordered, f, opndtab): 'instr_get_%s(instr, %d), ' + instr_arg_if_required + '&%s%d)') ret_str = (encode_method_format_str % - (ot, ('0' if opndtab[ot].used == 0 else + (opnd_stem(ot), ('0' if opndtab[ot].used == 0 else 'enc & 0x%08x' % opndtab[ot].used if opndtab[ot].used & ~f == 0 else '%s & 0x%08x' % (find_required(f, reordered, n, opndtab), @@ -319,22 +332,26 @@ def generate_opndset_encoders(opndsettab, opndtab): c += [' int opcode = instr->opcode;'] # The initial values are only required to silence a bad compiler warning: c += [' uint ' + ' = 0, '.join(vars) + ' = 0;'] - tests = (['instr_num_dsts(instr) == %d && instr_num_srcs(instr) == %d' % - (len(dsts), len(srcs))] + - [make_enc(i, enc_order, fixed, opndtab) - for i in range(len(enc_order))]) - - tests2 = (['dst%d == (enc & 0x%08x)' % (i, opndtab[dsts[i]].gen) - for i in range(len(dsts))] + - ['src%d == (enc & 0x%08x)' % (i, opndtab[srcs[i]].gen) - for i in range(len(srcs))]) + tests = ['instr_num_dsts(instr) == %d && instr_num_srcs(instr) == %d' % (len(dsts), len(srcs))] + + has_governing = any("gov" in opnd_flags(op) for op in srcs) + if has_governing: + tests += ['instr_has_register_predication(instr)'] + + tests += [make_enc(i, enc_order, fixed, opndtab) for i in range(len(enc_order))] + + opnd_tests = (['dst%d == (enc & 0x%08x)' % (i, opndtab[dst].gen) + for i, dst in enumerate(dsts)] + + ['src%d == (enc & 0x%08x)' % (i, opndtab[src].gen) + for i, src in enumerate(srcs)]) c += [' if (' + ' &&\n '.join(tests) + ') {'] c += [' ASSERT((dst%d & 0x%08x) == 0);' % - (i, ONES & ~opndtab[dsts[i]].gen) for i in range(len(dsts))] + (i, ONES & ~opndtab[dst].gen) for i, dst in enumerate(dsts)] c += [' ASSERT((src%d & 0x%08x) == 0);' % - (i, ONES & ~opndtab[srcs[i]].gen) for i in range(len(srcs))] + (i, ONES & ~opndtab[src].gen) for i, src in enumerate(srcs)] c += [' enc |= ' + ' | '.join(vars) + ';'] - c += [' if (' + ' &&\n '.join(tests2) + ')'] + c += [' if (' + ' &&\n '.join(opnd_tests) + ')'] + c += [' return enc;'] c += [' }'] c += [' return ENCFAIL;'] @@ -373,7 +390,7 @@ def reorder_key(t): last_pattern = patterns.pop() for pattern in patterns: c.append(' enc = encode_opnds%s(pc, instr, 0x%08x, di);' % ( - pattern.opndset, pattern.set_bits())) + opnd_stem(pattern.opndset), pattern.set_bits())) c.append(' if (enc != ENCFAIL)') c.append(' return enc;') # Fallthrough to call the next version of the encoder if defined. @@ -514,7 +531,19 @@ def write_if_changed(file, data): open(file, 'w').write(data) def read_opnd_defs_file(path): - opndtab = dict() + class OpndtabDict(dict): + """ + We want additional hints to be present when parsing opnds so that + the generator can make differing choices about them but we always + want to pass down to the same decode function. This object + functions just like a dictionary but ignores everything after + the first . when using a key to access the value. + """ + def __getitem__(self, key): + return super().__getitem__(key.split(".")[0]) + + opndtab = OpndtabDict() + file_msg = 'operand definitions file' try: @@ -545,7 +574,7 @@ def read_codec_file(path): for line in (l.split('#')[0].strip() for l in file): if not line: continue - if re.match('^[01x\^]{32} +[n|r|w|rw|wr|er|ew]+ +[0-9]+ +[a-zA-Z0-9]* +[a-zA-Z_0-9][a-zA-Z_0-9 ]*:[a-zA-Z_0-9 ]*$', line): + if re.match('^[01x\^]{32} +[n|r|w|rw|wr|er|ew]+ +[0-9]+ +[a-zA-Z0-9]* +[a-zA-Z_0-9][a-zA-Z_0-9 \.]*:[a-zA-Z_0-9 \.]*$', line): # Syntax: pattern opcode opndtype* : opndtype* pattern, nzcv_rw_flag, enum, feat, opcode, args = line.split(None, 5) dsts, srcs = [a.split() for a in args.split(':')] @@ -591,7 +620,7 @@ def consistency_check(patterns, opndtab): unhandled_bits &= ~opndtab[ot].gen except KeyError: raise Exception('Undefined opndtype %s in:\n%s' % - (ot, pattern_to_str(*p))) + (opnd_stem(ot), pattern_to_str(*p))) if unhandled_bits: raise Exception('Unhandled bits:\n%32s in:\n%s' % (re.sub('1', 'x', re.sub('0', ' ', bin(unhandled_bits)[2:])), diff --git a/core/ir/aarch64/codec_sve.txt b/core/ir/aarch64/codec_sve.txt index 20a2d54155b..42d807d0a58 100644 --- a/core/ir/aarch64/codec_sve.txt +++ b/core/ir/aarch64/codec_sve.txt @@ -40,34 +40,34 @@ # Instruction definitions: -00000100xx010110101xxxxxxxxxxxxx n 6 SVE abs z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_5 +00000100xx010110101xxxxxxxxxxxxx n 6 SVE abs z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_5 00000100xx1xxxxx000000xxxxxxxxxx n 9 SVE add z_size_bhsd_0 : z_size_bhsd_5 z_size_bhsd_16 -00000100xx000000000xxxxxxxxxxxxx n 9 SVE add z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +00000100xx000000000xxxxxxxxxxxxx n 9 SVE add z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 00100101xx10000011xxxxxxxxxxxxxx n 9 SVE add z_size_bhsd_0 : z_size_bhsd_0 imm8_5 lsl shift1 00000100011xxxxx01010xxxxxxxxxxx n 934 SVE addpl x0sp : x16sp simm6_5 00000100001xxxxx01010xxxxxxxxxxx n 935 SVE addvl x0sp : x16sp simm6_5 00000100001xxxxx1010xxxxxxxxxxxx n 15 SVE adr z_d_0 : svemem_vec_vec_idx 00000100011xxxxx1010xxxxxxxxxxxx n 15 SVE adr z_d_0 : svemem_vec_vec_idx 000001001x1xxxxx1010xxxxxxxxxxxx n 15 SVE adr z_sz_sd : svemem_vec_vec_idx -00000100xx011010000xxxxxxxxxxxxx n 21 SVE and z0 : p10_lo z0 z5 bhsd_sz +00000100xx011010000xxxxxxxxxxxxx n 21 SVE and z0 : p10_lo.gov z0 z5 bhsd_sz 00000101100000xxxxxxxxxxxxxxxxxx n 21 SVE and z_imm13_bhsd_0 : z_imm13_bhsd_0 imm13_const -001001010000xxxx01xxxx0xxxx0xxxx n 21 SVE and p_b_0 : p10_zer p_b_5 p_b_16 +001001010000xxxx01xxxx0xxxx0xxxx n 21 SVE and p_b_0 : p10_zer.gov p_b_5 p_b_16 00000100001xxxxx001100xxxxxxxxxx n 21 SVE and z_d_0 : z_d_5 z_d_16 -00000100xx011010000xxxxxxxxxxxxx n 21 SVE and z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -001001010100xxxx01xxxx0xxxx0xxxx w 22 SVE ands p_b_0 : p10_zer p_b_5 p_b_16 -0000010000011010001xxxxxxxxxxxxx n 915 SVE andv b0 : p10_lo z_size_bhsd_5 -0000010001011010001xxxxxxxxxxxxx n 915 SVE andv h0 : p10_lo z_size_bhsd_5 -0000010010011010001xxxxxxxxxxxxx n 915 SVE andv s0 : p10_lo z_size_bhsd_5 -0000010011011010001xxxxxxxxxxxxx n 915 SVE andv d0 : p10_lo z_size_bhsd_5 -00000100xx000000100xxxxxxxxxxxxx n 899 SVE asr z_tszl8_bhsd_0 : p10_mrg_lo z_tszl8_bhsd_0 tszl8_imm3_5p1 -00000100xx011000100xxxxxxxxxxxxx n 899 SVE asr z_size_bhs_0 : p10_mrg_lo z_size_bhs_0 z_d_5 -00000100xx010000100xxxxxxxxxxxxx n 899 SVE asr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +00000100xx011010000xxxxxxxxxxxxx n 21 SVE and z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +001001010100xxxx01xxxx0xxxx0xxxx w 22 SVE ands p_b_0 : p10_zer.gov p_b_5 p_b_16 +0000010000011010001xxxxxxxxxxxxx n 915 SVE andv b0 : p10_lo.gov z_size_bhsd_5 +0000010001011010001xxxxxxxxxxxxx n 915 SVE andv h0 : p10_lo.gov z_size_bhsd_5 +0000010010011010001xxxxxxxxxxxxx n 915 SVE andv s0 : p10_lo.gov z_size_bhsd_5 +0000010011011010001xxxxxxxxxxxxx n 915 SVE andv d0 : p10_lo.gov z_size_bhsd_5 +00000100xx000000100xxxxxxxxxxxxx n 899 SVE asr z_tszl8_bhsd_0 : p10_mrg_lo.gov z_tszl8_bhsd_0 tszl8_imm3_5p1 +00000100xx011000100xxxxxxxxxxxxx n 899 SVE asr z_size_bhs_0 : p10_mrg_lo.gov z_size_bhs_0 z_d_5 +00000100xx010000100xxxxxxxxxxxxx n 899 SVE asr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 00000100xx1xxxxx100100xxxxxxxxxx n 899 SVE asr z_tszl19_bhsd_0 : z_tszl19_bhsd_5 tszl19_imm3_16p1 00000100xx1xxxxx100000xxxxxxxxxx n 899 SVE asr z_size_bhs_0 : z_size_bhs_5 z_d_16 -00000100xx000100100xxxxxxxxxxxxx n 900 SVE asrd z_tszl8_bhsd_0 : p10_mrg_lo z_tszl8_bhsd_0 tszl8_imm3_5p1 -00000100xx010100100xxxxxxxxxxxxx n 901 SVE asrr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -0110010110001010101xxxxxxxxxxxxx n 953 BF16 bfcvt z_h_0 : p10_mrg_lo z_s_5 -0110010010001010101xxxxxxxxxxxxx n 1064 BF16 bfcvtnt z_msz_bhsd_0 : z_msz_bhsd_0 p10_mrg_lo z_s_5 +00000100xx000100100xxxxxxxxxxxxx n 900 SVE asrd z_tszl8_bhsd_0 : p10_mrg_lo.gov z_tszl8_bhsd_0 tszl8_imm3_5p1 +00000100xx010100100xxxxxxxxxxxxx n 901 SVE asrr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +0110010110001010101xxxxxxxxxxxxx n 953 BF16 bfcvt z_h_0 : p10_mrg_lo.gov z_s_5 +0110010010001010101xxxxxxxxxxxxx n 1064 BF16 bfcvtnt z_msz_bhsd_0 : z_msz_bhsd_0 p10_mrg_lo.gov z_s_5 01100100011xxxxx100000xxxxxxxxxx n 954 BF16 bfdot z_s_0 : z_s_0 z_h_5 z_h_16 01100100011xxxxx010000xxxxxxxxxx n 954 BF16 bfdot z_s_0 : z_s_0 z_h_5 z3_h_16 i2_index_19 01100100111xxxxx100000xxxxxxxxxx n 955 BF16 bfmlalb z_s_0 : z_s_0 z_h_5 z_h_16 @@ -75,69 +75,69 @@ 01100100111xxxxx100001xxxxxxxxxx n 956 BF16 bfmlalt z_s_0 : z_s_0 z_h_5 z_h_16 01100100111xxxxx0100x1xxxxxxxxxx n 956 BF16 bfmlalt z_s_0 : z_s_0 z_h_5 z3_h_16 i3_index_11 01100100011xxxxx111001xxxxxxxxxx n 957 BF16 bfmmla z_s_0 : z_s_0 z_h_5 z_h_16 -00000100xx011011000xxxxxxxxxxxxx n 29 SVE bic z0 : p10_lo z0 z5 bhsd_sz -001001010000xxxx01xxxx0xxxx1xxxx n 29 SVE bic p_b_0 : p10_zer p_b_5 p_b_16 +00000100xx011011000xxxxxxxxxxxxx n 29 SVE bic z0 : p10_lo.gov z0 z5 bhsd_sz +001001010000xxxx01xxxx0xxxx1xxxx n 29 SVE bic p_b_0 : p10_zer.gov p_b_5 p_b_16 00000100111xxxxx001100xxxxxxxxxx n 29 SVE bic z_d_0 : z_d_5 z_d_16 -00000100xx011011000xxxxxxxxxxxxx n 29 SVE bic z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -001001010100xxxx01xxxx0xxxx1xxxx w 30 SVE bics p_b_0 : p10_zer p_b_5 p_b_16 -001001010001000001xxxx0xxxx0xxxx n 867 SVE brka p_b_0 : p10_zer p_b_5 -001001010001000001xxxx0xxxx1xxxx n 867 SVE brka p_b_0 : p10_mrg p_b_5 -001001010101000001xxxx0xxxx0xxxx w 868 SVE brkas p_b_0 : p10_zer p_b_5 -001001011001000001xxxx0xxxx0xxxx n 869 SVE brkb p_b_0 : p10_zer p_b_5 -001001011001000001xxxx0xxxx1xxxx n 869 SVE brkb p_b_0 : p10_mrg p_b_5 -001001011101000001xxxx0xxxx0xxxx w 870 SVE brkbs p_b_0 : p10_zer p_b_5 -001001010001100001xxxx0xxxx0xxxx n 871 SVE brkn p_b_0 : p10_zer p_b_5 p_b_0 -001001010101100001xxxx0xxxx0xxxx w 872 SVE brkns p_b_0 : p10_zer p_b_5 p_b_0 -001001010000xxxx11xxxx0xxxx0xxxx n 873 SVE brkpa p_b_0 : p10_zer p_b_5 p_b_16 -001001010100xxxx11xxxx0xxxx0xxxx w 874 SVE brkpas p_b_0 : p10_zer p_b_5 p_b_16 -001001010000xxxx11xxxx0xxxx1xxxx n 875 SVE brkpb p_b_0 : p10_zer p_b_5 p_b_16 -001001010100xxxx11xxxx0xxxx1xxxx w 876 SVE brkpbs p_b_0 : p10_zer p_b_5 p_b_16 -00000101xx110000101xxxxxxxxxxxxx n 835 SVE clasta wx_size_0_zr : p10_lo wx_size_0_zr z_size_bhsd_5 -00000101xx101010100xxxxxxxxxxxxx n 835 SVE clasta bhsd_size_reg0 : p10_lo bhsd_size_reg0 z_size_bhsd_5 -00000101xx101000100xxxxxxxxxxxxx n 835 SVE clasta z_size_bhsd_0 : p10_lo z_size_bhsd_0 z_size_bhsd_5 -00000101xx110001101xxxxxxxxxxxxx n 836 SVE clastb wx_size_0_zr : p10_lo wx_size_0_zr z_size_bhsd_5 -00000101xx101011100xxxxxxxxxxxxx n 836 SVE clastb bhsd_size_reg0 : p10_lo bhsd_size_reg0 z_size_bhsd_5 -00000101xx101001100xxxxxxxxxxxxx n 836 SVE clastb z_size_bhsd_0 : p10_lo z_size_bhsd_0 z_size_bhsd_5 -00000100xx011000101xxxxxxxxxxxxx n 59 SVE cls z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_5 -00000100xx011001101xxxxxxxxxxxxx n 60 SVE clz z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_5 -00100101xx0xxxxx100xxxxxxxx0xxxx w 807 SVE cmpeq p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 simm5 -00100100xx0xxxxx001xxxxxxxx0xxxx w 807 SVE cmpeq p_size_bhs_0 : p10_zer_lo z_size_bhs_5 z_d_16 -00100100xx0xxxxx101xxxxxxxx0xxxx w 807 SVE cmpeq p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 z_size_bhsd_16 -00100101xx0xxxxx000xxxxxxxx0xxxx w 808 SVE cmpge p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 simm5 -00100100xx0xxxxx010xxxxxxxx0xxxx w 808 SVE cmpge p_size_bhs_0 : p10_zer_lo z_size_bhs_5 z_d_16 -00100100xx0xxxxx100xxxxxxxx0xxxx w 808 SVE cmpge p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 z_size_bhsd_16 -00100101xx0xxxxx000xxxxxxxx1xxxx w 809 SVE cmpgt p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 simm5 -00100100xx0xxxxx010xxxxxxxx1xxxx w 809 SVE cmpgt p_size_bhs_0 : p10_zer_lo z_size_bhs_5 z_d_16 -00100100xx0xxxxx100xxxxxxxx1xxxx w 809 SVE cmpgt p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 z_size_bhsd_16 -00100100xx1xxxxxxx0xxxxxxxx1xxxx w 810 SVE cmphi p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 imm7 -00100100xx0xxxxx110xxxxxxxx1xxxx w 810 SVE cmphi p_size_bhs_0 : p10_zer_lo z_size_bhs_5 z_d_16 -00100100xx0xxxxx000xxxxxxxx1xxxx w 810 SVE cmphi p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 z_size_bhsd_16 -00100100xx1xxxxxxx0xxxxxxxx0xxxx w 811 SVE cmphs p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 imm7 -00100100xx0xxxxx110xxxxxxxx0xxxx w 811 SVE cmphs p_size_bhs_0 : p10_zer_lo z_size_bhs_5 z_d_16 -00100100xx0xxxxx000xxxxxxxx0xxxx w 811 SVE cmphs p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 z_size_bhsd_16 -00100101xx0xxxxx001xxxxxxxx1xxxx w 812 SVE cmple p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 simm5 -00100100xx0xxxxx011xxxxxxxx1xxxx w 812 SVE cmple p_size_bhs_0 : p10_zer_lo z_size_bhs_5 z_d_16 -00100100xx1xxxxxxx1xxxxxxxx0xxxx w 813 SVE cmplo p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 imm7 -00100100xx0xxxxx111xxxxxxxx0xxxx w 813 SVE cmplo p_size_bhs_0 : p10_zer_lo z_size_bhs_5 z_d_16 -00100100xx1xxxxxxx1xxxxxxxx1xxxx w 814 SVE cmpls p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 imm7 -00100100xx0xxxxx111xxxxxxxx1xxxx w 814 SVE cmpls p_size_bhs_0 : p10_zer_lo z_size_bhs_5 z_d_16 -00100101xx0xxxxx001xxxxxxxx0xxxx w 815 SVE cmplt p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 simm5 -00100100xx0xxxxx011xxxxxxxx0xxxx w 815 SVE cmplt p_size_bhs_0 : p10_zer_lo z_size_bhs_5 z_d_16 -00100101xx0xxxxx100xxxxxxxx1xxxx w 816 SVE cmpne p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 simm5 -00100100xx0xxxxx001xxxxxxxx1xxxx w 816 SVE cmpne p_size_bhs_0 : p10_zer_lo z_size_bhs_5 z_d_16 -00100100xx0xxxxx101xxxxxxxx1xxxx w 816 SVE cmpne p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 z_size_bhsd_16 -00000100xx011011101xxxxxxxxxxxxx n 793 SVE cnot z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_5 -00000100xx011010101xxxxxxxxxxxxx n 69 SVE cnt z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_5 +00000100xx011011000xxxxxxxxxxxxx n 29 SVE bic z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +001001010100xxxx01xxxx0xxxx1xxxx w 30 SVE bics p_b_0 : p10_zer.gov p_b_5 p_b_16 +001001010001000001xxxx0xxxx0xxxx n 867 SVE brka p_b_0 : p10_zer.gov p_b_5 +001001010001000001xxxx0xxxx1xxxx n 867 SVE brka p_b_0 : p10_mrg.gov p_b_5 +001001010101000001xxxx0xxxx0xxxx w 868 SVE brkas p_b_0 : p10_zer.gov p_b_5 +001001011001000001xxxx0xxxx0xxxx n 869 SVE brkb p_b_0 : p10_zer.gov p_b_5 +001001011001000001xxxx0xxxx1xxxx n 869 SVE brkb p_b_0 : p10_mrg.gov p_b_5 +001001011101000001xxxx0xxxx0xxxx w 870 SVE brkbs p_b_0 : p10_zer.gov p_b_5 +001001010001100001xxxx0xxxx0xxxx n 871 SVE brkn p_b_0 : p10_zer.gov p_b_5 p_b_0 +001001010101100001xxxx0xxxx0xxxx w 872 SVE brkns p_b_0 : p10_zer.gov p_b_5 p_b_0 +001001010000xxxx11xxxx0xxxx0xxxx n 873 SVE brkpa p_b_0 : p10_zer.gov p_b_5 p_b_16 +001001010100xxxx11xxxx0xxxx0xxxx w 874 SVE brkpas p_b_0 : p10_zer.gov p_b_5 p_b_16 +001001010000xxxx11xxxx0xxxx1xxxx n 875 SVE brkpb p_b_0 : p10_zer.gov p_b_5 p_b_16 +001001010100xxxx11xxxx0xxxx1xxxx w 876 SVE brkpbs p_b_0 : p10_zer.gov p_b_5 p_b_16 +00000101xx110000101xxxxxxxxxxxxx n 835 SVE clasta wx_size_0_zr : p10_lo.gov wx_size_0_zr z_size_bhsd_5 +00000101xx101010100xxxxxxxxxxxxx n 835 SVE clasta bhsd_size_reg0 : p10_lo.gov bhsd_size_reg0 z_size_bhsd_5 +00000101xx101000100xxxxxxxxxxxxx n 835 SVE clasta z_size_bhsd_0 : p10_lo.gov z_size_bhsd_0 z_size_bhsd_5 +00000101xx110001101xxxxxxxxxxxxx n 836 SVE clastb wx_size_0_zr : p10_lo.gov wx_size_0_zr z_size_bhsd_5 +00000101xx101011100xxxxxxxxxxxxx n 836 SVE clastb bhsd_size_reg0 : p10_lo.gov bhsd_size_reg0 z_size_bhsd_5 +00000101xx101001100xxxxxxxxxxxxx n 836 SVE clastb z_size_bhsd_0 : p10_lo.gov z_size_bhsd_0 z_size_bhsd_5 +00000100xx011000101xxxxxxxxxxxxx n 59 SVE cls z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_5 +00000100xx011001101xxxxxxxxxxxxx n 60 SVE clz z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_5 +00100101xx0xxxxx100xxxxxxxx0xxxx w 807 SVE cmpeq p_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 simm5 +00100100xx0xxxxx001xxxxxxxx0xxxx w 807 SVE cmpeq p_size_bhs_0 : p10_zer_lo.gov z_size_bhs_5 z_d_16 +00100100xx0xxxxx101xxxxxxxx0xxxx w 807 SVE cmpeq p_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 z_size_bhsd_16 +00100101xx0xxxxx000xxxxxxxx0xxxx w 808 SVE cmpge p_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 simm5 +00100100xx0xxxxx010xxxxxxxx0xxxx w 808 SVE cmpge p_size_bhs_0 : p10_zer_lo.gov z_size_bhs_5 z_d_16 +00100100xx0xxxxx100xxxxxxxx0xxxx w 808 SVE cmpge p_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 z_size_bhsd_16 +00100101xx0xxxxx000xxxxxxxx1xxxx w 809 SVE cmpgt p_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 simm5 +00100100xx0xxxxx010xxxxxxxx1xxxx w 809 SVE cmpgt p_size_bhs_0 : p10_zer_lo.gov z_size_bhs_5 z_d_16 +00100100xx0xxxxx100xxxxxxxx1xxxx w 809 SVE cmpgt p_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 z_size_bhsd_16 +00100100xx1xxxxxxx0xxxxxxxx1xxxx w 810 SVE cmphi p_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 imm7 +00100100xx0xxxxx110xxxxxxxx1xxxx w 810 SVE cmphi p_size_bhs_0 : p10_zer_lo.gov z_size_bhs_5 z_d_16 +00100100xx0xxxxx000xxxxxxxx1xxxx w 810 SVE cmphi p_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 z_size_bhsd_16 +00100100xx1xxxxxxx0xxxxxxxx0xxxx w 811 SVE cmphs p_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 imm7 +00100100xx0xxxxx110xxxxxxxx0xxxx w 811 SVE cmphs p_size_bhs_0 : p10_zer_lo.gov z_size_bhs_5 z_d_16 +00100100xx0xxxxx000xxxxxxxx0xxxx w 811 SVE cmphs p_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 z_size_bhsd_16 +00100101xx0xxxxx001xxxxxxxx1xxxx w 812 SVE cmple p_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 simm5 +00100100xx0xxxxx011xxxxxxxx1xxxx w 812 SVE cmple p_size_bhs_0 : p10_zer_lo.gov z_size_bhs_5 z_d_16 +00100100xx1xxxxxxx1xxxxxxxx0xxxx w 813 SVE cmplo p_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 imm7 +00100100xx0xxxxx111xxxxxxxx0xxxx w 813 SVE cmplo p_size_bhs_0 : p10_zer_lo.gov z_size_bhs_5 z_d_16 +00100100xx1xxxxxxx1xxxxxxxx1xxxx w 814 SVE cmpls p_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 imm7 +00100100xx0xxxxx111xxxxxxxx1xxxx w 814 SVE cmpls p_size_bhs_0 : p10_zer_lo.gov z_size_bhs_5 z_d_16 +00100101xx0xxxxx001xxxxxxxx0xxxx w 815 SVE cmplt p_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 simm5 +00100100xx0xxxxx011xxxxxxxx0xxxx w 815 SVE cmplt p_size_bhs_0 : p10_zer_lo.gov z_size_bhs_5 z_d_16 +00100101xx0xxxxx100xxxxxxxx1xxxx w 816 SVE cmpne p_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 simm5 +00100100xx0xxxxx001xxxxxxxx1xxxx w 816 SVE cmpne p_size_bhs_0 : p10_zer_lo.gov z_size_bhs_5 z_d_16 +00100100xx0xxxxx101xxxxxxxx1xxxx w 816 SVE cmpne p_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 z_size_bhsd_16 +00000100xx011011101xxxxxxxxxxxxx n 793 SVE cnot z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_5 +00000100xx011010101xxxxxxxxxxxxx n 69 SVE cnt z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_5 000001000010xxxx111000xxxxxxxxxx n 839 SVE cntb x0 : pred_constr mul imm4_16p1 000001001110xxxx111000xxxxxxxxxx n 844 SVE cntd x0 : pred_constr mul imm4_16p1 000001000110xxxx111000xxxxxxxxxx n 845 SVE cnth x0 : pred_constr mul imm4_16p1 -00100101xx10000010xxxx0xxxxxxxxx n 821 SVE cntp x0 : p10 p_size_bhsd_5 +00100101xx10000010xxxx0xxxxxxxxx n 821 SVE cntp x0 : p10.gov p_size_bhsd_5 000001001010xxxx111000xxxxxxxxxx n 846 SVE cntw x0 : pred_constr mul imm4_16p1 -00000101xx100001100xxxxxxxxxxxxx n 886 SVE compact z_size_sd_0 : p10_lo z_size_sd_5 -00000101xx01xxxx00xxxxxxxxxxxxxx n 785 SVE cpy z_size_bhsd_0 : p16_zer simm8_5 lsl shift1 -00000101xx01xxxx01xxxxxxxxxxxxxx n 785 SVE cpy z_size_bhsd_0 : p16_mrg simm8_5 lsl shift1 -00000101xx101000101xxxxxxxxxxxxx n 785 SVE cpy z_size_bhsd_0 : p10_mrg_lo wx_size_5_sp -00000101xx100000100xxxxxxxxxxxxx n 785 SVE cpy z_size_bhsd_0 : p10_mrg_lo bhsd_size_reg5 +00000101xx100001100xxxxxxxxxxxxx n 886 SVE compact z_size_sd_0 : p10_lo.gov z_size_sd_5 +00000101xx01xxxx00xxxxxxxxxxxxxx n 785 SVE cpy z_size_bhsd_0 : p16_zer.gov simm8_5 lsl shift1 +00000101xx01xxxx01xxxxxxxxxxxxxx n 785 SVE cpy z_size_bhsd_0 : p16_mrg.gov simm8_5 lsl shift1 +00000101xx101000101xxxxxxxxxxxxx n 785 SVE cpy z_size_bhsd_0 : p10_mrg_lo.gov wx_size_5_sp +00000101xx100000100xxxxxxxxxxxxx n 785 SVE cpy z_size_bhsd_0 : p10_mrg_lo.gov bhsd_size_reg5 001001011x1xxxxx001000xxxxx00000 rw 923 SVE ctermeq : wx_sz_5 wx_sz_16 001001011x1xxxxx001000xxxxx10000 rw 924 SVE ctermne : wx_sz_5 wx_sz_16 000001000011xxxx111001xxxxxxxxxx n 840 SVE decb x0 : x0 pred_constr mul imm4_16p1 @@ -153,131 +153,131 @@ 00000101xx1xxxxx001000xxxxxxxxxx n 88 SVE dup z_tsz_bhsdq_0 : z_tsz_bhsdq_5 imm2_tsz_index 00000101xx100000001110xxxxxxxxxx n 88 SVE dup z_size_bhsd_0 : wx_size_5_sp 00000101110000xxxxxxxxxxxxxxxxxx n 893 SVE dupm z_imm13_bhsd_0 : imm13_const -00000100xx011001000xxxxxxxxxxxxx n 90 SVE eor z0 : p10_lo z0 z5 bhsd_sz +00000100xx011001000xxxxxxxxxxxxx n 90 SVE eor z0 : p10_lo.gov z0 z5 bhsd_sz 00000101010000xxxxxxxxxxxxxxxxxx n 90 SVE eor z_imm13_bhsd_0 : z_imm13_bhsd_0 imm13_const -001001010000xxxx01xxxx1xxxx0xxxx n 90 SVE eor p_b_0 : p10_zer p_b_5 p_b_16 +001001010000xxxx01xxxx1xxxx0xxxx n 90 SVE eor p_b_0 : p10_zer.gov p_b_5 p_b_16 00000100101xxxxx001100xxxxxxxxxx n 90 SVE eor z_d_0 : z_d_5 z_d_16 -00000100xx011001000xxxxxxxxxxxxx n 90 SVE eor z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -001001010100xxxx01xxxx1xxxx0xxxx w 828 SVE eors p_b_0 : p10_zer p_b_5 p_b_16 -0000010000011001001xxxxxxxxxxxxx n 916 SVE eorv b0 : p10_lo z_size_bhsd_5 -0000010001011001001xxxxxxxxxxxxx n 916 SVE eorv h0 : p10_lo z_size_bhsd_5 -0000010010011001001xxxxxxxxxxxxx n 916 SVE eorv s0 : p10_lo z_size_bhsd_5 -0000010011011001001xxxxxxxxxxxxx n 916 SVE eorv d0 : p10_lo z_size_bhsd_5 +00000100xx011001000xxxxxxxxxxxxx n 90 SVE eor z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +001001010100xxxx01xxxx1xxxx0xxxx w 828 SVE eors p_b_0 : p10_zer.gov p_b_5 p_b_16 +0000010000011001001xxxxxxxxxxxxx n 916 SVE eorv b0 : p10_lo.gov z_size_bhsd_5 +0000010001011001001xxxxxxxxxxxxx n 916 SVE eorv h0 : p10_lo.gov z_size_bhsd_5 +0000010010011001001xxxxxxxxxxxxx n 916 SVE eorv s0 : p10_lo.gov z_size_bhsd_5 +0000010011011001001xxxxxxxxxxxxx n 916 SVE eorv d0 : p10_lo.gov z_size_bhsd_5 00000101001xxxxx000xxxxxxxxxxxxx n 92 SVE ext z_b_0 : z_b_0 z_b_5 imm8_10 -01100101xx001000100xxxxxxxxxxxxx n 94 SVE fabd z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 -00000100xx011100101xxxxxxxxxxxxx n 95 SVE fabs z_size_hsd_0 : p10_mrg_lo z_size_hsd_5 -01100101xx0xxxxx110xxxxxxxx1xxxx n 96 SVE facge p_size_hsd_0 : p10_zer_lo z_size_hsd_5 z_size_hsd_16 -01100101xx0xxxxx111xxxxxxxx1xxxx n 97 SVE facgt p_size_hsd_0 : p10_zer_lo z_size_hsd_5 z_size_hsd_16 -01100101xx011000100xxx0000xxxxxx n 98 SVE fadd z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 fpimm1_half_one_5 -01100101xx000000100xxxxxxxxxxxxx n 98 SVE fadd z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 +01100101xx001000100xxxxxxxxxxxxx n 94 SVE fabd z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 +00000100xx011100101xxxxxxxxxxxxx n 95 SVE fabs z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_5 +01100101xx0xxxxx110xxxxxxxx1xxxx n 96 SVE facge p_size_hsd_0 : p10_zer_lo.gov z_size_hsd_5 z_size_hsd_16 +01100101xx0xxxxx111xxxxxxxx1xxxx n 97 SVE facgt p_size_hsd_0 : p10_zer_lo.gov z_size_hsd_5 z_size_hsd_16 +01100101xx011000100xxx0000xxxxxx n 98 SVE fadd z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 fpimm1_half_one_5 +01100101xx000000100xxxxxxxxxxxxx n 98 SVE fadd z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 01100101xx0xxxxx000000xxxxxxxxxx n 98 SVE fadd z_size_hsd_0 : z_size_hsd_5 z_size_hsd_16 -0110010101011000001xxxxxxxxxxxxx n 917 SVE fadda h0 : p10_lo h0 z_size_hsd_5 -0110010110011000001xxxxxxxxxxxxx n 917 SVE fadda s0 : p10_lo s0 z_size_hsd_5 -0110010111011000001xxxxxxxxxxxxx n 917 SVE fadda d0 : p10_lo d0 z_size_hsd_5 -0110010101000000001xxxxxxxxxxxxx n 918 SVE faddv h0 : p10_lo z_size_hsd_5 -0110010110000000001xxxxxxxxxxxxx n 918 SVE faddv s0 : p10_lo z_size_hsd_5 -0110010111000000001xxxxxxxxxxxxx n 918 SVE faddv d0 : p10_lo z_size_hsd_5 -01100100xx00000x100xxxxxxxxxxxxx n 944 SVE fcadd z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 imm1_ew_16 -01100101xx010010001xxxxxxxx0xxxx n 102 SVE fcmeq p_size_hsd_0 : p10_zer_lo z_size_hsd_5 zero_fp_const -01100101xx0xxxxx011xxxxxxxx0xxxx n 102 SVE fcmeq p_size_hsd_0 : p10_zer_lo z_size_hsd_5 z_size_hsd_16 -01100101xx010000001xxxxxxxx0xxxx n 103 SVE fcmge p_size_hsd_0 : p10_zer_lo z_size_hsd_5 zero_fp_const -01100101xx0xxxxx010xxxxxxxx0xxxx n 103 SVE fcmge p_size_hsd_0 : p10_zer_lo z_size_hsd_5 z_size_hsd_16 -01100101xx010000001xxxxxxxx1xxxx n 104 SVE fcmgt p_size_hsd_0 : p10_zer_lo z_size_hsd_5 zero_fp_const -01100101xx0xxxxx010xxxxxxxx1xxxx n 104 SVE fcmgt p_size_hsd_0 : p10_zer_lo z_size_hsd_5 z_size_hsd_16 -01100100xx0xxxxx0xxxxxxxxxxxxxxx n 945 SVE fcmla z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo z_size_hsd_5 z_size_hsd_16 imm2_nesw_13 +0110010101011000001xxxxxxxxxxxxx n 917 SVE fadda h0 : p10_lo.gov h0 z_size_hsd_5 +0110010110011000001xxxxxxxxxxxxx n 917 SVE fadda s0 : p10_lo.gov s0 z_size_hsd_5 +0110010111011000001xxxxxxxxxxxxx n 917 SVE fadda d0 : p10_lo.gov d0 z_size_hsd_5 +0110010101000000001xxxxxxxxxxxxx n 918 SVE faddv h0 : p10_lo.gov z_size_hsd_5 +0110010110000000001xxxxxxxxxxxxx n 918 SVE faddv s0 : p10_lo.gov z_size_hsd_5 +0110010111000000001xxxxxxxxxxxxx n 918 SVE faddv d0 : p10_lo.gov z_size_hsd_5 +01100100xx00000x100xxxxxxxxxxxxx n 944 SVE fcadd z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 imm1_ew_16 +01100101xx010010001xxxxxxxx0xxxx n 102 SVE fcmeq p_size_hsd_0 : p10_zer_lo.gov z_size_hsd_5 zero_fp_const +01100101xx0xxxxx011xxxxxxxx0xxxx n 102 SVE fcmeq p_size_hsd_0 : p10_zer_lo.gov z_size_hsd_5 z_size_hsd_16 +01100101xx010000001xxxxxxxx0xxxx n 103 SVE fcmge p_size_hsd_0 : p10_zer_lo.gov z_size_hsd_5 zero_fp_const +01100101xx0xxxxx010xxxxxxxx0xxxx n 103 SVE fcmge p_size_hsd_0 : p10_zer_lo.gov z_size_hsd_5 z_size_hsd_16 +01100101xx010000001xxxxxxxx1xxxx n 104 SVE fcmgt p_size_hsd_0 : p10_zer_lo.gov z_size_hsd_5 zero_fp_const +01100101xx0xxxxx010xxxxxxxx1xxxx n 104 SVE fcmgt p_size_hsd_0 : p10_zer_lo.gov z_size_hsd_5 z_size_hsd_16 +01100100xx0xxxxx0xxxxxxxxxxxxxxx n 945 SVE fcmla z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo.gov z_size_hsd_5 z_size_hsd_16 imm2_nesw_13 01100100101xxxxx0001xxxxxxxxxxxx n 945 SVE fcmla z_h_0 : z_h_0 z_h_5 z3_h_16 i2_index_19 imm2_nesw_10 01100100111xxxxx0001xxxxxxxxxxxx n 945 SVE fcmla z_s_0 : z_s_0 z_s_5 z4_s_16 i1_index_20 imm2_nesw_10 -01100101xx010001001xxxxxxxx1xxxx n 105 SVE fcmle p_size_hsd_0 : p10_zer_lo z_size_hsd_5 zero_fp_const -01100101xx010001001xxxxxxxx0xxxx n 106 SVE fcmlt p_size_hsd_0 : p10_zer_lo z_size_hsd_5 zero_fp_const -01100101xx010011001xxxxxxxx0xxxx n 805 SVE fcmne p_size_hsd_0 : p10_zer_lo z_size_hsd_5 zero_fp_const -01100101xx0xxxxx011xxxxxxxx1xxxx n 805 SVE fcmne p_size_hsd_0 : p10_zer_lo z_size_hsd_5 z_size_hsd_16 -01100101xx0xxxxx110xxxxxxxx0xxxx n 806 SVE fcmuo p_size_hsd_0 : p10_zer_lo z_size_hsd_5 z_size_hsd_16 -00000101xx01xxxx110xxxxxxxxxxxxx n 906 SVE fcpy z_size_hsd_0 : p16_mrg fpimm8_5 -0110010111001000101xxxxxxxxxxxxx n 110 SVE fcvt z_h_0 : p10_mrg_lo z_d_5 -0110010111001010101xxxxxxxxxxxxx n 110 SVE fcvt z_s_0 : p10_mrg_lo z_d_5 -0110010111001001101xxxxxxxxxxxxx n 110 SVE fcvt z_d_0 : p10_mrg_lo z_h_5 -0110010110001001101xxxxxxxxxxxxx n 110 SVE fcvt z_s_0 : p10_mrg_lo z_h_5 -0110010111001011101xxxxxxxxxxxxx n 110 SVE fcvt z_d_0 : p10_mrg_lo z_s_5 -0110010110001000101xxxxxxxxxxxxx n 110 SVE fcvt z_h_0 : p10_mrg_lo z_s_5 -0110010111011000101xxxxxxxxxxxxx n 125 SVE fcvtzs z_s_0 : p10_mrg_lo z_d_5 -0110010111011110101xxxxxxxxxxxxx n 125 SVE fcvtzs z_d_0 : p10_mrg_lo z_d_5 -0110010101011010101xxxxxxxxxxxxx n 125 SVE fcvtzs z_h_0 : p10_mrg_lo z_h_5 -0110010101011100101xxxxxxxxxxxxx n 125 SVE fcvtzs z_s_0 : p10_mrg_lo z_h_5 -0110010101011110101xxxxxxxxxxxxx n 125 SVE fcvtzs z_d_0 : p10_mrg_lo z_h_5 -0110010110011100101xxxxxxxxxxxxx n 125 SVE fcvtzs z_s_0 : p10_mrg_lo z_s_5 -0110010111011100101xxxxxxxxxxxxx n 125 SVE fcvtzs z_d_0 : p10_mrg_lo z_s_5 -0110010111011001101xxxxxxxxxxxxx n 126 SVE fcvtzu z_s_0 : p10_mrg_lo z_d_5 -0110010111011111101xxxxxxxxxxxxx n 126 SVE fcvtzu z_d_0 : p10_mrg_lo z_d_5 -0110010101011011101xxxxxxxxxxxxx n 126 SVE fcvtzu z_h_0 : p10_mrg_lo z_h_5 -0110010101011101101xxxxxxxxxxxxx n 126 SVE fcvtzu z_s_0 : p10_mrg_lo z_h_5 -0110010101011111101xxxxxxxxxxxxx n 126 SVE fcvtzu z_d_0 : p10_mrg_lo z_h_5 -0110010110011101101xxxxxxxxxxxxx n 126 SVE fcvtzu z_s_0 : p10_mrg_lo z_s_5 -0110010111011101101xxxxxxxxxxxxx n 126 SVE fcvtzu z_d_0 : p10_mrg_lo z_s_5 -01100101xx001101100xxxxxxxxxxxxx n 127 SVE fdiv z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 -01100101xx001100100xxxxxxxxxxxxx n 926 SVE fdivr z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 +01100101xx010001001xxxxxxxx1xxxx n 105 SVE fcmle p_size_hsd_0 : p10_zer_lo.gov z_size_hsd_5 zero_fp_const +01100101xx010001001xxxxxxxx0xxxx n 106 SVE fcmlt p_size_hsd_0 : p10_zer_lo.gov z_size_hsd_5 zero_fp_const +01100101xx010011001xxxxxxxx0xxxx n 805 SVE fcmne p_size_hsd_0 : p10_zer_lo.gov z_size_hsd_5 zero_fp_const +01100101xx0xxxxx011xxxxxxxx1xxxx n 805 SVE fcmne p_size_hsd_0 : p10_zer_lo.gov z_size_hsd_5 z_size_hsd_16 +01100101xx0xxxxx110xxxxxxxx0xxxx n 806 SVE fcmuo p_size_hsd_0 : p10_zer_lo.gov z_size_hsd_5 z_size_hsd_16 +00000101xx01xxxx110xxxxxxxxxxxxx n 906 SVE fcpy z_size_hsd_0 : p16_mrg.gov fpimm8_5 +0110010111001000101xxxxxxxxxxxxx n 110 SVE fcvt z_h_0 : p10_mrg_lo.gov z_d_5 +0110010111001010101xxxxxxxxxxxxx n 110 SVE fcvt z_s_0 : p10_mrg_lo.gov z_d_5 +0110010111001001101xxxxxxxxxxxxx n 110 SVE fcvt z_d_0 : p10_mrg_lo.gov z_h_5 +0110010110001001101xxxxxxxxxxxxx n 110 SVE fcvt z_s_0 : p10_mrg_lo.gov z_h_5 +0110010111001011101xxxxxxxxxxxxx n 110 SVE fcvt z_d_0 : p10_mrg_lo.gov z_s_5 +0110010110001000101xxxxxxxxxxxxx n 110 SVE fcvt z_h_0 : p10_mrg_lo.gov z_s_5 +0110010111011000101xxxxxxxxxxxxx n 125 SVE fcvtzs z_s_0 : p10_mrg_lo.gov z_d_5 +0110010111011110101xxxxxxxxxxxxx n 125 SVE fcvtzs z_d_0 : p10_mrg_lo.gov z_d_5 +0110010101011010101xxxxxxxxxxxxx n 125 SVE fcvtzs z_h_0 : p10_mrg_lo.gov z_h_5 +0110010101011100101xxxxxxxxxxxxx n 125 SVE fcvtzs z_s_0 : p10_mrg_lo.gov z_h_5 +0110010101011110101xxxxxxxxxxxxx n 125 SVE fcvtzs z_d_0 : p10_mrg_lo.gov z_h_5 +0110010110011100101xxxxxxxxxxxxx n 125 SVE fcvtzs z_s_0 : p10_mrg_lo.gov z_s_5 +0110010111011100101xxxxxxxxxxxxx n 125 SVE fcvtzs z_d_0 : p10_mrg_lo.gov z_s_5 +0110010111011001101xxxxxxxxxxxxx n 126 SVE fcvtzu z_s_0 : p10_mrg_lo.gov z_d_5 +0110010111011111101xxxxxxxxxxxxx n 126 SVE fcvtzu z_d_0 : p10_mrg_lo.gov z_d_5 +0110010101011011101xxxxxxxxxxxxx n 126 SVE fcvtzu z_h_0 : p10_mrg_lo.gov z_h_5 +0110010101011101101xxxxxxxxxxxxx n 126 SVE fcvtzu z_s_0 : p10_mrg_lo.gov z_h_5 +0110010101011111101xxxxxxxxxxxxx n 126 SVE fcvtzu z_d_0 : p10_mrg_lo.gov z_h_5 +0110010110011101101xxxxxxxxxxxxx n 126 SVE fcvtzu z_s_0 : p10_mrg_lo.gov z_s_5 +0110010111011101101xxxxxxxxxxxxx n 126 SVE fcvtzu z_d_0 : p10_mrg_lo.gov z_s_5 +01100101xx001101100xxxxxxxxxxxxx n 127 SVE fdiv z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 +01100101xx001100100xxxxxxxxxxxxx n 926 SVE fdivr z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 00100101xx111001110xxxxxxxxxxxxx n 907 SVE fdup z_size_hsd_0 : fpimm8_5 00000100xx100000101110xxxxxxxxxx n 789 SVE fexpa z_size_hsd_0 : z_size_hsd_5 -01100101xx1xxxxx100xxxxxxxxxxxxx n 927 SVE fmad z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo z_size_hsd_5 z_size_hsd_16 -01100101xx011110100xxx0000xxxxxx n 129 SVE fmax z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 fpimm1_zero_one_5 -01100101xx000110100xxxxxxxxxxxxx n 129 SVE fmax z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 -01100101xx011100100xxx0000xxxxxx n 130 SVE fmaxnm z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 fpimm1_zero_one_5 -01100101xx000100100xxxxxxxxxxxxx n 130 SVE fmaxnm z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 -0110010101000100001xxxxxxxxxxxxx n 132 SVE fmaxnmv h0 : p10_lo z_size_hsd_5 -0110010110000100001xxxxxxxxxxxxx n 132 SVE fmaxnmv s0 : p10_lo z_size_hsd_5 -0110010111000100001xxxxxxxxxxxxx n 132 SVE fmaxnmv d0 : p10_lo z_size_hsd_5 -0110010101000110001xxxxxxxxxxxxx n 134 SVE fmaxv h0 : p10_lo z_size_hsd_5 -0110010110000110001xxxxxxxxxxxxx n 134 SVE fmaxv s0 : p10_lo z_size_hsd_5 -0110010111000110001xxxxxxxxxxxxx n 134 SVE fmaxv d0 : p10_lo z_size_hsd_5 -01100101xx011111100xxx0000xxxxxx n 135 SVE fmin z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 fpimm1_zero_one_5 -01100101xx000111100xxxxxxxxxxxxx n 135 SVE fmin z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 -01100101xx011101100xxx0000xxxxxx n 136 SVE fminnm z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 fpimm1_zero_one_5 -01100101xx000101100xxxxxxxxxxxxx n 136 SVE fminnm z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 -0110010101000101001xxxxxxxxxxxxx n 138 SVE fminnmv h0 : p10_lo z_size_hsd_5 -0110010110000101001xxxxxxxxxxxxx n 138 SVE fminnmv s0 : p10_lo z_size_hsd_5 -0110010111000101001xxxxxxxxxxxxx n 138 SVE fminnmv d0 : p10_lo z_size_hsd_5 -0110010101000111001xxxxxxxxxxxxx n 140 SVE fminv h0 : p10_lo z_size_hsd_5 -0110010110000111001xxxxxxxxxxxxx n 140 SVE fminv s0 : p10_lo z_size_hsd_5 -0110010111000111001xxxxxxxxxxxxx n 140 SVE fminv d0 : p10_lo z_size_hsd_5 -01100101xx1xxxxx000xxxxxxxxxxxxx n 141 SVE fmla z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo z_size_hsd_5 z_size_hsd_16 +01100101xx1xxxxx100xxxxxxxxxxxxx n 927 SVE fmad z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo.gov z_size_hsd_5 z_size_hsd_16 +01100101xx011110100xxx0000xxxxxx n 129 SVE fmax z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 fpimm1_zero_one_5 +01100101xx000110100xxxxxxxxxxxxx n 129 SVE fmax z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 +01100101xx011100100xxx0000xxxxxx n 130 SVE fmaxnm z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 fpimm1_zero_one_5 +01100101xx000100100xxxxxxxxxxxxx n 130 SVE fmaxnm z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 +0110010101000100001xxxxxxxxxxxxx n 132 SVE fmaxnmv h0 : p10_lo.gov z_size_hsd_5 +0110010110000100001xxxxxxxxxxxxx n 132 SVE fmaxnmv s0 : p10_lo.gov z_size_hsd_5 +0110010111000100001xxxxxxxxxxxxx n 132 SVE fmaxnmv d0 : p10_lo.gov z_size_hsd_5 +0110010101000110001xxxxxxxxxxxxx n 134 SVE fmaxv h0 : p10_lo.gov z_size_hsd_5 +0110010110000110001xxxxxxxxxxxxx n 134 SVE fmaxv s0 : p10_lo.gov z_size_hsd_5 +0110010111000110001xxxxxxxxxxxxx n 134 SVE fmaxv d0 : p10_lo.gov z_size_hsd_5 +01100101xx011111100xxx0000xxxxxx n 135 SVE fmin z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 fpimm1_zero_one_5 +01100101xx000111100xxxxxxxxxxxxx n 135 SVE fmin z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 +01100101xx011101100xxx0000xxxxxx n 136 SVE fminnm z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 fpimm1_zero_one_5 +01100101xx000101100xxxxxxxxxxxxx n 136 SVE fminnm z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 +0110010101000101001xxxxxxxxxxxxx n 138 SVE fminnmv h0 : p10_lo.gov z_size_hsd_5 +0110010110000101001xxxxxxxxxxxxx n 138 SVE fminnmv s0 : p10_lo.gov z_size_hsd_5 +0110010111000101001xxxxxxxxxxxxx n 138 SVE fminnmv d0 : p10_lo.gov z_size_hsd_5 +0110010101000111001xxxxxxxxxxxxx n 140 SVE fminv h0 : p10_lo.gov z_size_hsd_5 +0110010110000111001xxxxxxxxxxxxx n 140 SVE fminv s0 : p10_lo.gov z_size_hsd_5 +0110010111000111001xxxxxxxxxxxxx n 140 SVE fminv d0 : p10_lo.gov z_size_hsd_5 +01100101xx1xxxxx000xxxxxxxxxxxxx n 141 SVE fmla z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo.gov z_size_hsd_5 z_size_hsd_16 011001000x1xxxxx000000xxxxxxxxxx n 141 SVE fmla z_h_0 : z_h_0 z_h_5 z3_h_16 i3_index_19 01100100101xxxxx000000xxxxxxxxxx n 141 SVE fmla z_s_0 : z_s_0 z_s_5 z3_s_16 i2_index_19 01100100111xxxxx000000xxxxxxxxxx n 141 SVE fmla z_d_0 : z_d_0 z_d_5 z4_d_16 i1_index_20 -01100101xx1xxxxx001xxxxxxxxxxxxx n 144 SVE fmls z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo z_size_hsd_5 z_size_hsd_16 +01100101xx1xxxxx001xxxxxxxxxxxxx n 144 SVE fmls z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo.gov z_size_hsd_5 z_size_hsd_16 011001000x1xxxxx000001xxxxxxxxxx n 144 SVE fmls z_h_0 : z_h_0 z_h_5 z3_h_16 i3_index_19 01100100101xxxxx000001xxxxxxxxxx n 144 SVE fmls z_s_0 : z_s_0 z_s_5 z3_s_16 i2_index_19 01100100111xxxxx000001xxxxxxxxxx n 144 SVE fmls z_d_0 : z_d_0 z_d_5 z4_d_16 i1_index_20 -01100101xx1xxxxx101xxxxxxxxxxxxx n 933 SVE fmsb z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo z_size_hsd_5 z_size_hsd_16 -01100101xx011010100xxx0000xxxxxx n 149 SVE fmul z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 fpimm1_half_two_5 -01100101xx000010100xxxxxxxxxxxxx n 149 SVE fmul z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 +01100101xx1xxxxx101xxxxxxxxxxxxx n 933 SVE fmsb z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo.gov z_size_hsd_5 z_size_hsd_16 +01100101xx011010100xxx0000xxxxxx n 149 SVE fmul z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 fpimm1_half_two_5 +01100101xx000010100xxxxxxxxxxxxx n 149 SVE fmul z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 01100101xx0xxxxx000010xxxxxxxxxx n 149 SVE fmul z_size_hsd_0 : z_size_hsd_5 z_size_hsd_16 011001000x1xxxxx001000xxxxxxxxxx n 149 SVE fmul z_h_0 : z_h_5 z3_h_16 i3_index_19 01100100101xxxxx001000xxxxxxxxxx n 149 SVE fmul z_s_0 : z_s_5 z3_s_16 i2_index_19 01100100111xxxxx001000xxxxxxxxxx n 149 SVE fmul z_d_0 : z_d_5 z4_d_16 i1_index_20 -01100101xx001010100xxxxxxxxxxxxx n 150 SVE fmulx z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 -00000100xx011101101xxxxxxxxxxxxx n 151 SVE fneg z_size_hsd_0 : p10_mrg_lo z_size_hsd_5 -01100101xx1xxxxx110xxxxxxxxxxxxx n 928 SVE fnmad z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo z_size_hsd_5 z_size_hsd_16 -01100101xx1xxxxx010xxxxxxxxxxxxx n 929 SVE fnmla z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo z_size_hsd_5 z_size_hsd_16 -01100101xx1xxxxx011xxxxxxxxxxxxx n 930 SVE fnmls z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo z_size_hsd_5 z_size_hsd_16 -01100101xx1xxxxx111xxxxxxxxxxxxx n 1063 SVE fnmsb z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo z_size_hsd_5 z_size_hsd_16 +01100101xx001010100xxxxxxxxxxxxx n 150 SVE fmulx z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 +00000100xx011101101xxxxxxxxxxxxx n 151 SVE fneg z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_5 +01100101xx1xxxxx110xxxxxxxxxxxxx n 928 SVE fnmad z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo.gov z_size_hsd_5 z_size_hsd_16 +01100101xx1xxxxx010xxxxxxxxxxxxx n 929 SVE fnmla z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo.gov z_size_hsd_5 z_size_hsd_16 +01100101xx1xxxxx011xxxxxxxxxxxxx n 930 SVE fnmls z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo.gov z_size_hsd_5 z_size_hsd_16 +01100101xx1xxxxx111xxxxxxxxxxxxx n 1063 SVE fnmsb z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo.gov z_size_hsd_5 z_size_hsd_16 01100101xx001110001100xxxxxxxxxx n 155 SVE frecpe z_size_hsd_0 : z_size_hsd_5 01100101xx0xxxxx000110xxxxxxxxxx n 156 SVE frecps z_size_hsd_0 : z_size_hsd_5 z_size_hsd_16 -01100101xx001100101xxxxxxxxxxxxx n 157 SVE frecpx z_size_hsd_0 : p10_mrg_lo z_size_hsd_5 -01100101xx000100101xxxxxxxxxxxxx n 158 SVE frinta z_size_hsd_0 : p10_mrg_lo z_size_hsd_5 -01100101xx000111101xxxxxxxxxxxxx n 159 SVE frinti z_size_hsd_0 : p10_mrg_lo z_size_hsd_5 -01100101xx000010101xxxxxxxxxxxxx n 160 SVE frintm z_size_hsd_0 : p10_mrg_lo z_size_hsd_5 -01100101xx000000101xxxxxxxxxxxxx n 161 SVE frintn z_size_hsd_0 : p10_mrg_lo z_size_hsd_5 -01100101xx000001101xxxxxxxxxxxxx n 162 SVE frintp z_size_hsd_0 : p10_mrg_lo z_size_hsd_5 -01100101xx000110101xxxxxxxxxxxxx n 163 SVE frintx z_size_hsd_0 : p10_mrg_lo z_size_hsd_5 -01100101xx000011101xxxxxxxxxxxxx n 164 SVE frintz z_size_hsd_0 : p10_mrg_lo z_size_hsd_5 +01100101xx001100101xxxxxxxxxxxxx n 157 SVE frecpx z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_5 +01100101xx000100101xxxxxxxxxxxxx n 158 SVE frinta z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_5 +01100101xx000111101xxxxxxxxxxxxx n 159 SVE frinti z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_5 +01100101xx000010101xxxxxxxxxxxxx n 160 SVE frintm z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_5 +01100101xx000000101xxxxxxxxxxxxx n 161 SVE frintn z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_5 +01100101xx000001101xxxxxxxxxxxxx n 162 SVE frintp z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_5 +01100101xx000110101xxxxxxxxxxxxx n 163 SVE frintx z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_5 +01100101xx000011101xxxxxxxxxxxxx n 164 SVE frintz z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_5 01100101xx001111001100xxxxxxxxxx n 165 SVE frsqrte z_size_hsd_0 : z_size_hsd_5 01100101xx0xxxxx000111xxxxxxxxxx n 166 SVE frsqrts z_size_hsd_0 : z_size_hsd_5 z_size_hsd_16 -01100101xx001001100xxxxxxxxxxxxx n 931 SVE fscale z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 -01100101xx001101101xxxxxxxxxxxxx n 167 SVE fsqrt z_size_hsd_0 : p10_mrg_lo z_size_hsd_5 -01100101xx011001100xxx0000xxxxxx n 168 SVE fsub z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 fpimm1_half_one_5 -01100101xx000001100xxxxxxxxxxxxx n 168 SVE fsub z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 +01100101xx001001100xxxxxxxxxxxxx n 931 SVE fscale z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 +01100101xx001101101xxxxxxxxxxxxx n 167 SVE fsqrt z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_5 +01100101xx011001100xxx0000xxxxxx n 168 SVE fsub z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 fpimm1_half_one_5 +01100101xx000001100xxxxxxxxxxxxx n 168 SVE fsub z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 01100101xx0xxxxx000001xxxxxxxxxx n 168 SVE fsub z_size_hsd_0 : z_size_hsd_5 z_size_hsd_16 -01100101xx011011100xxx0000xxxxxx n 932 SVE fsubr z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 fpimm1_half_one_5 -01100101xx000011100xxxxxxxxxxxxx n 932 SVE fsubr z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 +01100101xx011011100xxx0000xxxxxx n 932 SVE fsubr z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 fpimm1_half_one_5 +01100101xx000011100xxxxxxxxxxxxx n 932 SVE fsubr z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 01100101xx010xxx100000xxxxxxxxxx n 790 SVE ftmad z_size_hsd_0 : z_size_hsd_0 z_size_hsd_5 imm3 01100101xx0xxxxx000011xxxxxxxxxx n 791 SVE ftsmul z_size_hsd_0 : z_size_hsd_5 z_size_hsd_16 00000100xx1xxxxx101100xxxxxxxxxx n 792 SVE ftssel z_size_hsd_0 : z_size_hsd_5 z_size_hsd_16 @@ -296,344 +296,344 @@ 00000100xx1xxxxx010011xxxxxxxxxx n 922 SVE index z_size_bhsd_0 : wx_size_5_zr wx_size_16_zr 00000101xx100100001110xxxxxxxxxx n 881 SVE insr z_size_bhsd_0 : z_size_bhsd_0 wx_size_5_zr 00000101xx110100001110xxxxxxxxxx n 881 SVE insr z_size_bhsd_0 : z_size_bhsd_0 bhsd_size_reg5 -00000101xx100000101xxxxxxxxxxxxx n 837 SVE lasta wx_size_0_zr : p10_lo z_size_bhsd_5 -00000101xx100010100xxxxxxxxxxxxx n 837 SVE lasta bhsd_size_reg0 : p10_lo z_size_bhsd_5 -00000101xx100001101xxxxxxxxxxxxx n 838 SVE lastb wx_size_0_zr : p10_lo z_size_bhsd_5 -00000101xx100011100xxxxxxxxxxxxx n 838 SVE lastb bhsd_size_reg0 : p10_lo z_size_bhsd_5 -10100100001xxxxx010xxxxxxxxxxxxx n 946 SVE ld1b z_h_0 : svemem_gpr_shf p10_zer_lo -10100100010xxxxx010xxxxxxxxxxxxx n 946 SVE ld1b z_s_0 : svemem_gpr_shf p10_zer_lo -10100100011xxxxx010xxxxxxxxxxxxx n 946 SVE ld1b z_d_0 : svemem_gpr_shf p10_zer_lo -10100100000xxxxx010xxxxxxxxxxxxx n 946 SVE ld1b z_b_0 : svemem_gpr_shf p10_zer_lo -11000100001xxxxx110xxxxxxxxxxxxx n 946 SVE ld1b z_d_0 : svemem_vec_d_imm5 p10_zer_lo -10000100001xxxxx110xxxxxxxxxxxxx n 946 SVE ld1b z_s_0 : svemem_vec_s_imm5 p10_zer_lo -11000100001xxxxx110xxxxxxxxxxxxx n 946 SVE ld1b z_d_0 : svemem_vec_d_imm5 p10_zer_lo -10000100001xxxxx110xxxxxxxxxxxxx n 946 SVE ld1b z_s_0 : svemem_vec_s_imm5 p10_zer_lo -11000100010xxxxx110xxxxxxxxxxxxx n 946 SVE ld1b z_d_0 : svemem_gpr_vec64 p10_zer_lo -110001000x0xxxxx010xxxxxxxxxxxxx n 946 SVE ld1b z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -100001000x0xxxxx010xxxxxxxxxxxxx n 946 SVE ld1b z_s_0 : svemem_gpr_vec32_ld p10_zer_lo -101001000010xxxx101xxxxxxxxxxxxx n 946 SVE ld1b z_h_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001000100xxxx101xxxxxxxxxxxxx n 946 SVE ld1b z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001000110xxxx101xxxxxxxxxxxxx n 946 SVE ld1b z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001000000xxxx101xxxxxxxxxxxxx n 946 SVE ld1b z_b_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -11000101101xxxxx110xxxxxxxxxxxxx n 975 SVE ld1d z_d_0 : svemem_vec_d_imm5 p10_zer_lo -11000101111xxxxx110xxxxxxxxxxxxx n 975 SVE ld1d z_d_0 : svemem_gpr_vec64 p10_zer_lo -11000101110xxxxx110xxxxxxxxxxxxx n 975 SVE ld1d z_d_0 : svemem_gpr_vec64 p10_zer_lo -110001011x1xxxxx010xxxxxxxxxxxxx n 975 SVE ld1d z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -110001011x0xxxxx010xxxxxxxxxxxxx n 975 SVE ld1d z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -10100101111xxxxx010xxxxxxxxxxxxx n 975 SVE ld1d z_msz_bhsd_0 : svemem_gpr_shf p10_zer_lo -101001011110xxxx101xxxxxxxxxxxxx n 975 SVE ld1d z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -10000100101xxxxx110xxxxxxxxxxxxx n 976 SVE ld1h z_s_0 : svemem_vec_s_imm5 p10_zer_lo -11000100101xxxxx110xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_vec_d_imm5 p10_zer_lo -11000100111xxxxx110xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_gpr_vec64 p10_zer_lo -11000100110xxxxx110xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_gpr_vec64 p10_zer_lo -110001001x1xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -110001001x0xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -100001001x1xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_s_0 : svemem_gpr_vec32_ld p10_zer_lo -100001001x0xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_s_0 : svemem_gpr_vec32_ld p10_zer_lo -10100100101xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_msz_bhsd_0 : svemem_gpr_shf p10_zer_lo -10100100110xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_s_0 : svemem_gpr_shf p10_zer_lo -10100100111xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_gpr_shf p10_zer_lo -101001001010xxxx101xxxxxxxxxxxxx n 976 SVE ld1h z_h_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001001100xxxx101xxxxxxxxxxxxx n 976 SVE ld1h z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001001110xxxx101xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -1000010001xxxxxx101xxxxxxxxxxxxx n 908 SVE ld1rb z_h_0 : svememx6_b_5 p10_zer_lo -1000010001xxxxxx110xxxxxxxxxxxxx n 908 SVE ld1rb z_s_0 : svememx6_b_5 p10_zer_lo -1000010001xxxxxx111xxxxxxxxxxxxx n 908 SVE ld1rb z_d_0 : svememx6_b_5 p10_zer_lo -1000010001xxxxxx100xxxxxxxxxxxxx n 908 SVE ld1rb z_b_0 : svememx6_b_5 p10_zer_lo -1000010111xxxxxx111xxxxxxxxxxxxx n 909 SVE ld1rd z_d_0 : svememx6_d_5 p10_zer_lo -1000010011xxxxxx101xxxxxxxxxxxxx n 910 SVE ld1rh z_h_0 : svememx6_h_5 p10_zer_lo -1000010011xxxxxx110xxxxxxxxxxxxx n 910 SVE ld1rh z_s_0 : svememx6_h_5 p10_zer_lo -1000010011xxxxxx111xxxxxxxxxxxxx n 910 SVE ld1rh z_d_0 : svememx6_h_5 p10_zer_lo -10100100001xxxxx000xxxxxxxxxxxxx n 947 SVE ld1rob z_b_0 : svemem_ssz_gpr_shf p10_zer_lo -101001000000xxxx001xxxxxxxxxxxxx n 948 SVE ld1rqb z_b_0 : svemem_ssz_gpr_simm4 p10_zer_lo -10100100000xxxxx000xxxxxxxxxxxxx n 948 SVE ld1rqb z_b_0 : svemem_ssz_gpr_shf p10_zer_lo -101001011000xxxx001xxxxxxxxxxxxx n 1060 SVE ld1rqd z_d_0 : svemem_ssz_gpr_simm4 p10_zer_lo -10100101100xxxxx000xxxxxxxxxxxxx n 1060 SVE ld1rqd z_d_0 : svemem_ssz_gpr_shf p10_zer_lo -101001001000xxxx001xxxxxxxxxxxxx n 1061 SVE ld1rqh z_h_0 : svemem_ssz_gpr_simm4 p10_zer_lo -10100100100xxxxx000xxxxxxxxxxxxx n 1061 SVE ld1rqh z_h_0 : svemem_ssz_gpr_shf p10_zer_lo -101001010000xxxx001xxxxxxxxxxxxx n 1062 SVE ld1rqw z_s_0 : svemem_ssz_gpr_simm4 p10_zer_lo -10100101000xxxxx000xxxxxxxxxxxxx n 1062 SVE ld1rqw z_s_0 : svemem_ssz_gpr_shf p10_zer_lo -1000010111xxxxxx110xxxxxxxxxxxxx n 911 SVE ld1rsb z_h_0 : svememx6_b_5 p10_zer_lo -1000010111xxxxxx101xxxxxxxxxxxxx n 911 SVE ld1rsb z_s_0 : svememx6_b_5 p10_zer_lo -1000010111xxxxxx100xxxxxxxxxxxxx n 911 SVE ld1rsb z_d_0 : svememx6_b_5 p10_zer_lo -1000010101xxxxxx101xxxxxxxxxxxxx n 912 SVE ld1rsh z_s_0 : svememx6_h_5 p10_zer_lo -1000010101xxxxxx100xxxxxxxxxxxxx n 912 SVE ld1rsh z_d_0 : svememx6_h_5 p10_zer_lo -1000010011xxxxxx100xxxxxxxxxxxxx n 913 SVE ld1rsw z_d_0 : svememx6_s_5 p10_zer_lo -1000010101xxxxxx110xxxxxxxxxxxxx n 914 SVE ld1rw z_s_0 : svememx6_s_5 p10_zer_lo -1000010101xxxxxx111xxxxxxxxxxxxx n 914 SVE ld1rw z_d_0 : svememx6_s_5 p10_zer_lo -10100101110xxxxx010xxxxxxxxxxxxx n 949 SVE ld1sb z_h_0 : svemem_gpr_shf p10_zer_lo -10100101101xxxxx010xxxxxxxxxxxxx n 949 SVE ld1sb z_s_0 : svemem_gpr_shf p10_zer_lo -10100101100xxxxx010xxxxxxxxxxxxx n 949 SVE ld1sb z_d_0 : svemem_gpr_shf p10_zer_lo -10000100001xxxxx100xxxxxxxxxxxxx n 949 SVE ld1sb z_s_0 : svemem_vec_s_imm5 p10_zer_lo -11000100001xxxxx100xxxxxxxxxxxxx n 949 SVE ld1sb z_d_0 : svemem_vec_d_imm5 p10_zer_lo -11000100010xxxxx100xxxxxxxxxxxxx n 949 SVE ld1sb z_d_0 : svemem_gpr_vec64 p10_zer_lo -110001000x0xxxxx000xxxxxxxxxxxxx n 949 SVE ld1sb z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -100001000x0xxxxx000xxxxxxxxxxxxx n 949 SVE ld1sb z_s_0 : svemem_gpr_vec32_ld p10_zer_lo -101001011100xxxx101xxxxxxxxxxxxx n 949 SVE ld1sb z_h_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001011010xxxx101xxxxxxxxxxxxx n 949 SVE ld1sb z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001011000xxxx101xxxxxxxxxxxxx n 949 SVE ld1sb z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -10000100101xxxxx100xxxxxxxxxxxxx n 977 SVE ld1sh z_s_0 : svemem_vec_s_imm5 p10_zer_lo -11000100101xxxxx100xxxxxxxxxxxxx n 977 SVE ld1sh z_d_0 : svemem_vec_d_imm5 p10_zer_lo -11000100111xxxxx100xxxxxxxxxxxxx n 977 SVE ld1sh z_d_0 : svemem_gpr_vec64 p10_zer_lo -11000100110xxxxx100xxxxxxxxxxxxx n 977 SVE ld1sh z_d_0 : svemem_gpr_vec64 p10_zer_lo -110001001x1xxxxx000xxxxxxxxxxxxx n 977 SVE ld1sh z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -110001001x0xxxxx000xxxxxxxxxxxxx n 977 SVE ld1sh z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -100001001x1xxxxx000xxxxxxxxxxxxx n 977 SVE ld1sh z_s_0 : svemem_gpr_vec32_ld p10_zer_lo -100001001x0xxxxx000xxxxxxxxxxxxx n 977 SVE ld1sh z_s_0 : svemem_gpr_vec32_ld p10_zer_lo -10100101001xxxxx010xxxxxxxxxxxxx n 977 SVE ld1sh z_msz_bhsd_0 : svemem_gpr_shf p10_zer_lo -10100101000xxxxx010xxxxxxxxxxxxx n 977 SVE ld1sh z_d_0 : svemem_gpr_shf p10_zer_lo -101001010010xxxx101xxxxxxxxxxxxx n 977 SVE ld1sh z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001010000xxxx101xxxxxxxxxxxxx n 977 SVE ld1sh z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -11000101001xxxxx100xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_vec_d_imm5 p10_zer_lo -11000101011xxxxx100xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_vec64 p10_zer_lo -11000101010xxxxx100xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_vec64 p10_zer_lo -110001010x1xxxxx000xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -110001010x0xxxxx000xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -11000101001xxxxx100xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_vec_d_imm5 p10_zer_lo -10100100100xxxxx010xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_shf p10_zer_lo -101001001000xxxx101xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -10000101001xxxxx110xxxxxxxxxxxxx n 979 SVE ld1w z_s_0 : svemem_vec_s_imm5 p10_zer_lo -11000101001xxxxx110xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_vec_d_imm5 p10_zer_lo -11000101011xxxxx110xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_gpr_vec64 p10_zer_lo -11000101010xxxxx110xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_gpr_vec64 p10_zer_lo -110001010x1xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -110001010x0xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -100001010x1xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_s_0 : svemem_gpr_vec32_ld p10_zer_lo -100001010x0xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_s_0 : svemem_gpr_vec32_ld p10_zer_lo -10100101010xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_msz_bhsd_0 : svemem_gpr_shf p10_zer_lo -10100101011xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_gpr_shf p10_zer_lo -101001010100xxxx101xxxxxxxxxxxxx n 979 SVE ld1w z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001010110xxxx101xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -10100100001xxxxx110xxxxxxxxxxxxx n 967 SVE ld2b z_b_0 z_msz_bhsd_0p1 : svemem_gprs_bhsdx p10_zer_lo -101001000010xxxx111xxxxxxxxxxxxx n 967 SVE ld2b z_b_0 z_msz_bhsd_0p1 : svemem_gpr_simm4_vl_xreg p10_zer_lo -10100101101xxxxx110xxxxxxxxxxxxx n 983 SVE ld2d z_msz_bhsd_0 z_msz_bhsd_0p1 : svemem_msz_gpr_shf p10_zer_lo -101001011010xxxx111xxxxxxxxxxxxx n 983 SVE ld2d z_d_0 z_msz_bhsd_0p1 : svemem_gpr_simm4_vl_xreg p10_zer_lo -10100100101xxxxx110xxxxxxxxxxxxx n 984 SVE ld2h z_msz_bhsd_0 z_msz_bhsd_0p1 : svemem_msz_gpr_shf p10_zer_lo -101001001010xxxx111xxxxxxxxxxxxx n 984 SVE ld2h z_h_0 z_msz_bhsd_0p1 : svemem_gpr_simm4_vl_xreg p10_zer_lo -10100101001xxxxx110xxxxxxxxxxxxx n 985 SVE ld2w z_msz_bhsd_0 z_msz_bhsd_0p1 : svemem_msz_gpr_shf p10_zer_lo -101001010010xxxx111xxxxxxxxxxxxx n 985 SVE ld2w z_s_0 z_msz_bhsd_0p1 : svemem_gpr_simm4_vl_xreg p10_zer_lo -10100100010xxxxx110xxxxxxxxxxxxx n 968 SVE ld3b z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_gprs_bhsdx p10_zer_lo -10100100010xxxxx110xxxxxxxxxxxxx n 968 SVE ld3b z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_gprs_bhsdx p10_zer_lo -101001000100xxxx111xxxxxxxxxxxxx n 968 SVE ld3b z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_gpr_simm4_vl_xreg p10_zer_lo -10100101110xxxxx110xxxxxxxxxxxxx n 986 SVE ld3d z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_msz_gpr_shf p10_zer_lo -101001011100xxxx111xxxxxxxxxxxxx n 986 SVE ld3d z_d_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_gpr_simm4_vl_xreg p10_zer_lo -10100100110xxxxx110xxxxxxxxxxxxx n 987 SVE ld3h z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_msz_gpr_shf p10_zer_lo -101001001100xxxx111xxxxxxxxxxxxx n 987 SVE ld3h z_h_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_gpr_simm4_vl_xreg p10_zer_lo -10100101010xxxxx110xxxxxxxxxxxxx n 988 SVE ld3w z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_msz_gpr_shf p10_zer_lo -101001010100xxxx111xxxxxxxxxxxxx n 988 SVE ld3w z_s_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_gpr_simm4_vl_xreg p10_zer_lo -10100100011xxxxx110xxxxxxxxxxxxx n 969 SVE ld4b z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_gprs_bhsdx p10_zer_lo -10100100011xxxxx110xxxxxxxxxxxxx n 969 SVE ld4b z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_gprs_bhsdx p10_zer_lo -101001000110xxxx111xxxxxxxxxxxxx n 969 SVE ld4b z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_gpr_simm4_vl_xreg p10_zer_lo -10100101111xxxxx110xxxxxxxxxxxxx n 989 SVE ld4d z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_msz_gpr_shf p10_zer_lo -101001011110xxxx111xxxxxxxxxxxxx n 989 SVE ld4d z_d_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_gpr_simm4_vl_xreg p10_zer_lo -10100100111xxxxx110xxxxxxxxxxxxx n 990 SVE ld4h z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_msz_gpr_shf p10_zer_lo -101001001110xxxx111xxxxxxxxxxxxx n 990 SVE ld4h z_h_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_gpr_simm4_vl_xreg p10_zer_lo -10100101011xxxxx110xxxxxxxxxxxxx n 991 SVE ld4w z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_msz_gpr_shf p10_zer_lo -101001010110xxxx111xxxxxxxxxxxxx n 991 SVE ld4w z_s_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_gpr_simm4_vl_xreg p10_zer_lo -10100100001xxxxx011xxxxxxxxxxxxx n 937 SVE ldff1b z_h_0 : svemem_gpr_shf p10_zer_lo -10100100010xxxxx011xxxxxxxxxxxxx n 937 SVE ldff1b z_s_0 : svemem_gpr_shf p10_zer_lo -10100100011xxxxx011xxxxxxxxxxxxx n 937 SVE ldff1b z_d_0 : svemem_gpr_shf p10_zer_lo -10100100000xxxxx011xxxxxxxxxxxxx n 937 SVE ldff1b z_b_0 : svemem_gpr_shf p10_zer_lo -10000100001xxxxx111xxxxxxxxxxxxx n 937 SVE ldff1b z_s_0 : svemem_vec_s_imm5 p10_zer_lo -11000100001xxxxx111xxxxxxxxxxxxx n 937 SVE ldff1b z_d_0 : svemem_vec_d_imm5 p10_zer_lo -11000100010xxxxx111xxxxxxxxxxxxx n 937 SVE ldff1b z_d_0 : svemem_gpr_vec64 p10_zer_lo -110001000x0xxxxx011xxxxxxxxxxxxx n 937 SVE ldff1b z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -100001000x0xxxxx011xxxxxxxxxxxxx n 937 SVE ldff1b z_s_0 : svemem_gpr_vec32_ld p10_zer_lo -10100101111xxxxx011xxxxxxxxxxxxx n 938 SVE ldff1d z_d_0 : svemem_gpr_shf p10_zer_lo -11000101101xxxxx111xxxxxxxxxxxxx n 938 SVE ldff1d z_d_0 : svemem_vec_d_imm5 p10_zer_lo -11000101111xxxxx111xxxxxxxxxxxxx n 938 SVE ldff1d z_d_0 : svemem_gpr_vec64 p10_zer_lo -11000101110xxxxx111xxxxxxxxxxxxx n 938 SVE ldff1d z_d_0 : svemem_gpr_vec64 p10_zer_lo -110001011x1xxxxx011xxxxxxxxxxxxx n 938 SVE ldff1d z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -110001011x0xxxxx011xxxxxxxxxxxxx n 938 SVE ldff1d z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -10100100101xxxxx011xxxxxxxxxxxxx n 939 SVE ldff1h z_h_0 : svemem_gpr_shf p10_zer_lo -10100100110xxxxx011xxxxxxxxxxxxx n 939 SVE ldff1h z_s_0 : svemem_gpr_shf p10_zer_lo -10100100111xxxxx011xxxxxxxxxxxxx n 939 SVE ldff1h z_d_0 : svemem_gpr_shf p10_zer_lo -10000100101xxxxx111xxxxxxxxxxxxx n 939 SVE ldff1h z_s_0 : svemem_vec_s_imm5 p10_zer_lo -11000100101xxxxx111xxxxxxxxxxxxx n 939 SVE ldff1h z_d_0 : svemem_vec_d_imm5 p10_zer_lo -11000100111xxxxx111xxxxxxxxxxxxx n 939 SVE ldff1h z_d_0 : svemem_gpr_vec64 p10_zer_lo -11000100110xxxxx111xxxxxxxxxxxxx n 939 SVE ldff1h z_d_0 : svemem_gpr_vec64 p10_zer_lo -110001001x1xxxxx011xxxxxxxxxxxxx n 939 SVE ldff1h z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -110001001x0xxxxx011xxxxxxxxxxxxx n 939 SVE ldff1h z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -100001001x1xxxxx011xxxxxxxxxxxxx n 939 SVE ldff1h z_s_0 : svemem_gpr_vec32_ld p10_zer_lo -100001001x0xxxxx011xxxxxxxxxxxxx n 939 SVE ldff1h z_s_0 : svemem_gpr_vec32_ld p10_zer_lo -10100101110xxxxx011xxxxxxxxxxxxx n 940 SVE ldff1sb z_h_0 : svemem_gpr_shf p10_zer_lo -10100101101xxxxx011xxxxxxxxxxxxx n 940 SVE ldff1sb z_s_0 : svemem_gpr_shf p10_zer_lo -10100101100xxxxx011xxxxxxxxxxxxx n 940 SVE ldff1sb z_d_0 : svemem_gpr_shf p10_zer_lo -10000100001xxxxx101xxxxxxxxxxxxx n 940 SVE ldff1sb z_s_0 : svemem_vec_s_imm5 p10_zer_lo -11000100001xxxxx101xxxxxxxxxxxxx n 940 SVE ldff1sb z_d_0 : svemem_vec_d_imm5 p10_zer_lo -11000100010xxxxx101xxxxxxxxxxxxx n 940 SVE ldff1sb z_d_0 : svemem_gpr_vec64 p10_zer_lo -110001000x0xxxxx001xxxxxxxxxxxxx n 940 SVE ldff1sb z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -100001000x0xxxxx001xxxxxxxxxxxxx n 940 SVE ldff1sb z_s_0 : svemem_gpr_vec32_ld p10_zer_lo -10100101001xxxxx011xxxxxxxxxxxxx n 941 SVE ldff1sh z_s_0 : svemem_gpr_shf p10_zer_lo -10100101000xxxxx011xxxxxxxxxxxxx n 941 SVE ldff1sh z_d_0 : svemem_gpr_shf p10_zer_lo -10000100101xxxxx101xxxxxxxxxxxxx n 941 SVE ldff1sh z_s_0 : svemem_vec_s_imm5 p10_zer_lo -11000100101xxxxx101xxxxxxxxxxxxx n 941 SVE ldff1sh z_d_0 : svemem_vec_d_imm5 p10_zer_lo -11000100111xxxxx101xxxxxxxxxxxxx n 941 SVE ldff1sh z_d_0 : svemem_gpr_vec64 p10_zer_lo -11000100110xxxxx101xxxxxxxxxxxxx n 941 SVE ldff1sh z_d_0 : svemem_gpr_vec64 p10_zer_lo -110001001x1xxxxx001xxxxxxxxxxxxx n 941 SVE ldff1sh z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -110001001x0xxxxx001xxxxxxxxxxxxx n 941 SVE ldff1sh z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -100001001x1xxxxx001xxxxxxxxxxxxx n 941 SVE ldff1sh z_s_0 : svemem_gpr_vec32_ld p10_zer_lo -100001001x0xxxxx001xxxxxxxxxxxxx n 941 SVE ldff1sh z_s_0 : svemem_gpr_vec32_ld p10_zer_lo -10100100100xxxxx011xxxxxxxxxxxxx n 942 SVE ldff1sw z_d_0 : svemem_gpr_shf p10_zer_lo -11000101001xxxxx101xxxxxxxxxxxxx n 942 SVE ldff1sw z_d_0 : svemem_vec_d_imm5 p10_zer_lo -11000101011xxxxx101xxxxxxxxxxxxx n 942 SVE ldff1sw z_d_0 : svemem_gpr_vec64 p10_zer_lo -11000101010xxxxx101xxxxxxxxxxxxx n 942 SVE ldff1sw z_d_0 : svemem_gpr_vec64 p10_zer_lo -110001010x1xxxxx001xxxxxxxxxxxxx n 942 SVE ldff1sw z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -110001010x0xxxxx001xxxxxxxxxxxxx n 942 SVE ldff1sw z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -10100101010xxxxx011xxxxxxxxxxxxx n 943 SVE ldff1w z_s_0 : svemem_gpr_shf p10_zer_lo -10100101011xxxxx011xxxxxxxxxxxxx n 943 SVE ldff1w z_d_0 : svemem_gpr_shf p10_zer_lo -10000101001xxxxx111xxxxxxxxxxxxx n 943 SVE ldff1w z_s_0 : svemem_vec_s_imm5 p10_zer_lo -11000101001xxxxx111xxxxxxxxxxxxx n 943 SVE ldff1w z_d_0 : svemem_vec_d_imm5 p10_zer_lo -11000101011xxxxx111xxxxxxxxxxxxx n 943 SVE ldff1w z_d_0 : svemem_gpr_vec64 p10_zer_lo -11000101010xxxxx111xxxxxxxxxxxxx n 943 SVE ldff1w z_d_0 : svemem_gpr_vec64 p10_zer_lo -110001010x1xxxxx011xxxxxxxxxxxxx n 943 SVE ldff1w z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -110001010x0xxxxx011xxxxxxxxxxxxx n 943 SVE ldff1w z_d_0 : svemem_gpr_vec32_ld p10_zer_lo -100001010x1xxxxx011xxxxxxxxxxxxx n 943 SVE ldff1w z_s_0 : svemem_gpr_vec32_ld p10_zer_lo -100001010x0xxxxx011xxxxxxxxxxxxx n 943 SVE ldff1w z_s_0 : svemem_gpr_vec32_ld p10_zer_lo -101001000011xxxx101xxxxxxxxxxxxx n 1007 SVE ldnf1b z_h_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001000101xxxx101xxxxxxxxxxxxx n 1007 SVE ldnf1b z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001000111xxxx101xxxxxxxxxxxxx n 1007 SVE ldnf1b z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001000001xxxx101xxxxxxxxxxxxx n 1007 SVE ldnf1b z_b_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001011111xxxx101xxxxxxxxxxxxx n 1008 SVE ldnf1d z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001001011xxxx101xxxxxxxxxxxxx n 1009 SVE ldnf1h z_h_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001001101xxxx101xxxxxxxxxxxxx n 1009 SVE ldnf1h z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001001111xxxx101xxxxxxxxxxxxx n 1009 SVE ldnf1h z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001011101xxxx101xxxxxxxxxxxxx n 1010 SVE ldnf1sb z_h_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001011011xxxx101xxxxxxxxxxxxx n 1010 SVE ldnf1sb z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001011001xxxx101xxxxxxxxxxxxx n 1010 SVE ldnf1sb z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001010011xxxx101xxxxxxxxxxxxx n 1011 SVE ldnf1sh z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001010001xxxx101xxxxxxxxxxxxx n 1011 SVE ldnf1sh z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001001001xxxx101xxxxxxxxxxxxx n 1012 SVE ldnf1sw z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001010101xxxx101xxxxxxxxxxxxx n 1013 SVE ldnf1w z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -101001010111xxxx101xxxxxxxxxxxxx n 1013 SVE ldnf1w z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo -10100100000xxxxx110xxxxxxxxxxxxx n 950 SVE ldnt1b z_b_0 : svemem_gprs_b1 p10_zer_lo -101001000000xxxx111xxxxxxxxxxxxx n 950 SVE ldnt1b z_b_0 : svemem_gpr_simm4_vl_xreg p10_zer_lo -10100101100xxxxx110xxxxxxxxxxxxx n 992 SVE ldnt1d z_msz_bhsd_0 : svemem_msz_gpr_shf p10_zer_lo -101001011000xxxx111xxxxxxxxxxxxx n 992 SVE ldnt1d z_d_0 : svemem_gpr_simm4_vl_xreg p10_zer_lo -10100100100xxxxx110xxxxxxxxxxxxx n 993 SVE ldnt1h z_msz_bhsd_0 : svemem_msz_gpr_shf p10_zer_lo -101001001000xxxx111xxxxxxxxxxxxx n 993 SVE ldnt1h z_h_0 : svemem_gpr_simm4_vl_xreg p10_zer_lo -10100101000xxxxx110xxxxxxxxxxxxx n 994 SVE ldnt1w z_msz_bhsd_0 : svemem_msz_gpr_shf p10_zer_lo -101001010000xxxx111xxxxxxxxxxxxx n 994 SVE ldnt1w z_s_0 : svemem_gpr_simm4_vl_xreg p10_zer_lo +00000101xx100000101xxxxxxxxxxxxx n 837 SVE lasta wx_size_0_zr : p10_lo.gov z_size_bhsd_5 +00000101xx100010100xxxxxxxxxxxxx n 837 SVE lasta bhsd_size_reg0 : p10_lo.gov z_size_bhsd_5 +00000101xx100001101xxxxxxxxxxxxx n 838 SVE lastb wx_size_0_zr : p10_lo.gov z_size_bhsd_5 +00000101xx100011100xxxxxxxxxxxxx n 838 SVE lastb bhsd_size_reg0 : p10_lo.gov z_size_bhsd_5 +10100100001xxxxx010xxxxxxxxxxxxx n 946 SVE ld1b z_h_0 : svemem_gpr_shf p10_zer_lo.gov +10100100010xxxxx010xxxxxxxxxxxxx n 946 SVE ld1b z_s_0 : svemem_gpr_shf p10_zer_lo.gov +10100100011xxxxx010xxxxxxxxxxxxx n 946 SVE ld1b z_d_0 : svemem_gpr_shf p10_zer_lo.gov +10100100000xxxxx010xxxxxxxxxxxxx n 946 SVE ld1b z_b_0 : svemem_gpr_shf p10_zer_lo.gov +11000100001xxxxx110xxxxxxxxxxxxx n 946 SVE ld1b z_d_0 : svemem_vec_d_imm5 p10_zer_lo.gov +10000100001xxxxx110xxxxxxxxxxxxx n 946 SVE ld1b z_s_0 : svemem_vec_s_imm5 p10_zer_lo.gov +11000100001xxxxx110xxxxxxxxxxxxx n 946 SVE ld1b z_d_0 : svemem_vec_d_imm5 p10_zer_lo.gov +10000100001xxxxx110xxxxxxxxxxxxx n 946 SVE ld1b z_s_0 : svemem_vec_s_imm5 p10_zer_lo.gov +11000100010xxxxx110xxxxxxxxxxxxx n 946 SVE ld1b z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +110001000x0xxxxx010xxxxxxxxxxxxx n 946 SVE ld1b z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +100001000x0xxxxx010xxxxxxxxxxxxx n 946 SVE ld1b z_s_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +101001000010xxxx101xxxxxxxxxxxxx n 946 SVE ld1b z_h_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001000100xxxx101xxxxxxxxxxxxx n 946 SVE ld1b z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001000110xxxx101xxxxxxxxxxxxx n 946 SVE ld1b z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001000000xxxx101xxxxxxxxxxxxx n 946 SVE ld1b z_b_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +11000101101xxxxx110xxxxxxxxxxxxx n 975 SVE ld1d z_d_0 : svemem_vec_d_imm5 p10_zer_lo.gov +11000101111xxxxx110xxxxxxxxxxxxx n 975 SVE ld1d z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +11000101110xxxxx110xxxxxxxxxxxxx n 975 SVE ld1d z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +110001011x1xxxxx010xxxxxxxxxxxxx n 975 SVE ld1d z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +110001011x0xxxxx010xxxxxxxxxxxxx n 975 SVE ld1d z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +10100101111xxxxx010xxxxxxxxxxxxx n 975 SVE ld1d z_msz_bhsd_0 : svemem_gpr_shf p10_zer_lo.gov +101001011110xxxx101xxxxxxxxxxxxx n 975 SVE ld1d z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +10000100101xxxxx110xxxxxxxxxxxxx n 976 SVE ld1h z_s_0 : svemem_vec_s_imm5 p10_zer_lo.gov +11000100101xxxxx110xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_vec_d_imm5 p10_zer_lo.gov +11000100111xxxxx110xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +11000100110xxxxx110xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +110001001x1xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +110001001x0xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +100001001x1xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_s_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +100001001x0xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_s_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +10100100101xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_msz_bhsd_0 : svemem_gpr_shf p10_zer_lo.gov +10100100110xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_s_0 : svemem_gpr_shf p10_zer_lo.gov +10100100111xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_gpr_shf p10_zer_lo.gov +101001001010xxxx101xxxxxxxxxxxxx n 976 SVE ld1h z_h_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001001100xxxx101xxxxxxxxxxxxx n 976 SVE ld1h z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001001110xxxx101xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +1000010001xxxxxx101xxxxxxxxxxxxx n 908 SVE ld1rb z_h_0 : svememx6_b_5 p10_zer_lo.gov +1000010001xxxxxx110xxxxxxxxxxxxx n 908 SVE ld1rb z_s_0 : svememx6_b_5 p10_zer_lo.gov +1000010001xxxxxx111xxxxxxxxxxxxx n 908 SVE ld1rb z_d_0 : svememx6_b_5 p10_zer_lo.gov +1000010001xxxxxx100xxxxxxxxxxxxx n 908 SVE ld1rb z_b_0 : svememx6_b_5 p10_zer_lo.gov +1000010111xxxxxx111xxxxxxxxxxxxx n 909 SVE ld1rd z_d_0 : svememx6_d_5 p10_zer_lo.gov +1000010011xxxxxx101xxxxxxxxxxxxx n 910 SVE ld1rh z_h_0 : svememx6_h_5 p10_zer_lo.gov +1000010011xxxxxx110xxxxxxxxxxxxx n 910 SVE ld1rh z_s_0 : svememx6_h_5 p10_zer_lo.gov +1000010011xxxxxx111xxxxxxxxxxxxx n 910 SVE ld1rh z_d_0 : svememx6_h_5 p10_zer_lo.gov +10100100001xxxxx000xxxxxxxxxxxxx n 947 SVE ld1rob z_b_0 : svemem_ssz_gpr_shf p10_zer_lo.gov +101001000000xxxx001xxxxxxxxxxxxx n 948 SVE ld1rqb z_b_0 : svemem_ssz_gpr_simm4 p10_zer_lo.gov +10100100000xxxxx000xxxxxxxxxxxxx n 948 SVE ld1rqb z_b_0 : svemem_ssz_gpr_shf p10_zer_lo.gov +101001011000xxxx001xxxxxxxxxxxxx n 1060 SVE ld1rqd z_d_0 : svemem_ssz_gpr_simm4 p10_zer_lo.gov +10100101100xxxxx000xxxxxxxxxxxxx n 1060 SVE ld1rqd z_d_0 : svemem_ssz_gpr_shf p10_zer_lo.gov +101001001000xxxx001xxxxxxxxxxxxx n 1061 SVE ld1rqh z_h_0 : svemem_ssz_gpr_simm4 p10_zer_lo.gov +10100100100xxxxx000xxxxxxxxxxxxx n 1061 SVE ld1rqh z_h_0 : svemem_ssz_gpr_shf p10_zer_lo.gov +101001010000xxxx001xxxxxxxxxxxxx n 1062 SVE ld1rqw z_s_0 : svemem_ssz_gpr_simm4 p10_zer_lo.gov +10100101000xxxxx000xxxxxxxxxxxxx n 1062 SVE ld1rqw z_s_0 : svemem_ssz_gpr_shf p10_zer_lo.gov +1000010111xxxxxx110xxxxxxxxxxxxx n 911 SVE ld1rsb z_h_0 : svememx6_b_5 p10_zer_lo.gov +1000010111xxxxxx101xxxxxxxxxxxxx n 911 SVE ld1rsb z_s_0 : svememx6_b_5 p10_zer_lo.gov +1000010111xxxxxx100xxxxxxxxxxxxx n 911 SVE ld1rsb z_d_0 : svememx6_b_5 p10_zer_lo.gov +1000010101xxxxxx101xxxxxxxxxxxxx n 912 SVE ld1rsh z_s_0 : svememx6_h_5 p10_zer_lo.gov +1000010101xxxxxx100xxxxxxxxxxxxx n 912 SVE ld1rsh z_d_0 : svememx6_h_5 p10_zer_lo.gov +1000010011xxxxxx100xxxxxxxxxxxxx n 913 SVE ld1rsw z_d_0 : svememx6_s_5 p10_zer_lo.gov +1000010101xxxxxx110xxxxxxxxxxxxx n 914 SVE ld1rw z_s_0 : svememx6_s_5 p10_zer_lo.gov +1000010101xxxxxx111xxxxxxxxxxxxx n 914 SVE ld1rw z_d_0 : svememx6_s_5 p10_zer_lo.gov +10100101110xxxxx010xxxxxxxxxxxxx n 949 SVE ld1sb z_h_0 : svemem_gpr_shf p10_zer_lo.gov +10100101101xxxxx010xxxxxxxxxxxxx n 949 SVE ld1sb z_s_0 : svemem_gpr_shf p10_zer_lo.gov +10100101100xxxxx010xxxxxxxxxxxxx n 949 SVE ld1sb z_d_0 : svemem_gpr_shf p10_zer_lo.gov +10000100001xxxxx100xxxxxxxxxxxxx n 949 SVE ld1sb z_s_0 : svemem_vec_s_imm5 p10_zer_lo.gov +11000100001xxxxx100xxxxxxxxxxxxx n 949 SVE ld1sb z_d_0 : svemem_vec_d_imm5 p10_zer_lo.gov +11000100010xxxxx100xxxxxxxxxxxxx n 949 SVE ld1sb z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +110001000x0xxxxx000xxxxxxxxxxxxx n 949 SVE ld1sb z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +100001000x0xxxxx000xxxxxxxxxxxxx n 949 SVE ld1sb z_s_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +101001011100xxxx101xxxxxxxxxxxxx n 949 SVE ld1sb z_h_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001011010xxxx101xxxxxxxxxxxxx n 949 SVE ld1sb z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001011000xxxx101xxxxxxxxxxxxx n 949 SVE ld1sb z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +10000100101xxxxx100xxxxxxxxxxxxx n 977 SVE ld1sh z_s_0 : svemem_vec_s_imm5 p10_zer_lo.gov +11000100101xxxxx100xxxxxxxxxxxxx n 977 SVE ld1sh z_d_0 : svemem_vec_d_imm5 p10_zer_lo.gov +11000100111xxxxx100xxxxxxxxxxxxx n 977 SVE ld1sh z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +11000100110xxxxx100xxxxxxxxxxxxx n 977 SVE ld1sh z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +110001001x1xxxxx000xxxxxxxxxxxxx n 977 SVE ld1sh z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +110001001x0xxxxx000xxxxxxxxxxxxx n 977 SVE ld1sh z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +100001001x1xxxxx000xxxxxxxxxxxxx n 977 SVE ld1sh z_s_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +100001001x0xxxxx000xxxxxxxxxxxxx n 977 SVE ld1sh z_s_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +10100101001xxxxx010xxxxxxxxxxxxx n 977 SVE ld1sh z_msz_bhsd_0 : svemem_gpr_shf p10_zer_lo.gov +10100101000xxxxx010xxxxxxxxxxxxx n 977 SVE ld1sh z_d_0 : svemem_gpr_shf p10_zer_lo.gov +101001010010xxxx101xxxxxxxxxxxxx n 977 SVE ld1sh z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001010000xxxx101xxxxxxxxxxxxx n 977 SVE ld1sh z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +11000101001xxxxx100xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_vec_d_imm5 p10_zer_lo.gov +11000101011xxxxx100xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +11000101010xxxxx100xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +110001010x1xxxxx000xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +110001010x0xxxxx000xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +11000101001xxxxx100xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_vec_d_imm5 p10_zer_lo.gov +10100100100xxxxx010xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_shf p10_zer_lo.gov +101001001000xxxx101xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +10000101001xxxxx110xxxxxxxxxxxxx n 979 SVE ld1w z_s_0 : svemem_vec_s_imm5 p10_zer_lo.gov +11000101001xxxxx110xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_vec_d_imm5 p10_zer_lo.gov +11000101011xxxxx110xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +11000101010xxxxx110xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +110001010x1xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +110001010x0xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +100001010x1xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_s_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +100001010x0xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_s_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +10100101010xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_msz_bhsd_0 : svemem_gpr_shf p10_zer_lo.gov +10100101011xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_gpr_shf p10_zer_lo.gov +101001010100xxxx101xxxxxxxxxxxxx n 979 SVE ld1w z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001010110xxxx101xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +10100100001xxxxx110xxxxxxxxxxxxx n 967 SVE ld2b z_b_0 z_msz_bhsd_0p1 : svemem_gprs_bhsdx p10_zer_lo.gov +101001000010xxxx111xxxxxxxxxxxxx n 967 SVE ld2b z_b_0 z_msz_bhsd_0p1 : svemem_gpr_simm4_vl_xreg p10_zer_lo.gov +10100101101xxxxx110xxxxxxxxxxxxx n 983 SVE ld2d z_msz_bhsd_0 z_msz_bhsd_0p1 : svemem_msz_gpr_shf p10_zer_lo.gov +101001011010xxxx111xxxxxxxxxxxxx n 983 SVE ld2d z_d_0 z_msz_bhsd_0p1 : svemem_gpr_simm4_vl_xreg p10_zer_lo.gov +10100100101xxxxx110xxxxxxxxxxxxx n 984 SVE ld2h z_msz_bhsd_0 z_msz_bhsd_0p1 : svemem_msz_gpr_shf p10_zer_lo.gov +101001001010xxxx111xxxxxxxxxxxxx n 984 SVE ld2h z_h_0 z_msz_bhsd_0p1 : svemem_gpr_simm4_vl_xreg p10_zer_lo.gov +10100101001xxxxx110xxxxxxxxxxxxx n 985 SVE ld2w z_msz_bhsd_0 z_msz_bhsd_0p1 : svemem_msz_gpr_shf p10_zer_lo.gov +101001010010xxxx111xxxxxxxxxxxxx n 985 SVE ld2w z_s_0 z_msz_bhsd_0p1 : svemem_gpr_simm4_vl_xreg p10_zer_lo.gov +10100100010xxxxx110xxxxxxxxxxxxx n 968 SVE ld3b z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_gprs_bhsdx p10_zer_lo.gov +10100100010xxxxx110xxxxxxxxxxxxx n 968 SVE ld3b z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_gprs_bhsdx p10_zer_lo.gov +101001000100xxxx111xxxxxxxxxxxxx n 968 SVE ld3b z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_gpr_simm4_vl_xreg p10_zer_lo.gov +10100101110xxxxx110xxxxxxxxxxxxx n 986 SVE ld3d z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_msz_gpr_shf p10_zer_lo.gov +101001011100xxxx111xxxxxxxxxxxxx n 986 SVE ld3d z_d_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_gpr_simm4_vl_xreg p10_zer_lo.gov +10100100110xxxxx110xxxxxxxxxxxxx n 987 SVE ld3h z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_msz_gpr_shf p10_zer_lo.gov +101001001100xxxx111xxxxxxxxxxxxx n 987 SVE ld3h z_h_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_gpr_simm4_vl_xreg p10_zer_lo.gov +10100101010xxxxx110xxxxxxxxxxxxx n 988 SVE ld3w z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_msz_gpr_shf p10_zer_lo.gov +101001010100xxxx111xxxxxxxxxxxxx n 988 SVE ld3w z_s_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_gpr_simm4_vl_xreg p10_zer_lo.gov +10100100011xxxxx110xxxxxxxxxxxxx n 969 SVE ld4b z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_gprs_bhsdx p10_zer_lo.gov +10100100011xxxxx110xxxxxxxxxxxxx n 969 SVE ld4b z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_gprs_bhsdx p10_zer_lo.gov +101001000110xxxx111xxxxxxxxxxxxx n 969 SVE ld4b z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_gpr_simm4_vl_xreg p10_zer_lo.gov +10100101111xxxxx110xxxxxxxxxxxxx n 989 SVE ld4d z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_msz_gpr_shf p10_zer_lo.gov +101001011110xxxx111xxxxxxxxxxxxx n 989 SVE ld4d z_d_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_gpr_simm4_vl_xreg p10_zer_lo.gov +10100100111xxxxx110xxxxxxxxxxxxx n 990 SVE ld4h z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_msz_gpr_shf p10_zer_lo.gov +101001001110xxxx111xxxxxxxxxxxxx n 990 SVE ld4h z_h_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_gpr_simm4_vl_xreg p10_zer_lo.gov +10100101011xxxxx110xxxxxxxxxxxxx n 991 SVE ld4w z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_msz_gpr_shf p10_zer_lo.gov +101001010110xxxx111xxxxxxxxxxxxx n 991 SVE ld4w z_s_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_gpr_simm4_vl_xreg p10_zer_lo.gov +10100100001xxxxx011xxxxxxxxxxxxx n 937 SVE ldff1b z_h_0 : svemem_gpr_shf p10_zer_lo.gov +10100100010xxxxx011xxxxxxxxxxxxx n 937 SVE ldff1b z_s_0 : svemem_gpr_shf p10_zer_lo.gov +10100100011xxxxx011xxxxxxxxxxxxx n 937 SVE ldff1b z_d_0 : svemem_gpr_shf p10_zer_lo.gov +10100100000xxxxx011xxxxxxxxxxxxx n 937 SVE ldff1b z_b_0 : svemem_gpr_shf p10_zer_lo.gov +10000100001xxxxx111xxxxxxxxxxxxx n 937 SVE ldff1b z_s_0 : svemem_vec_s_imm5 p10_zer_lo.gov +11000100001xxxxx111xxxxxxxxxxxxx n 937 SVE ldff1b z_d_0 : svemem_vec_d_imm5 p10_zer_lo.gov +11000100010xxxxx111xxxxxxxxxxxxx n 937 SVE ldff1b z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +110001000x0xxxxx011xxxxxxxxxxxxx n 937 SVE ldff1b z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +100001000x0xxxxx011xxxxxxxxxxxxx n 937 SVE ldff1b z_s_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +10100101111xxxxx011xxxxxxxxxxxxx n 938 SVE ldff1d z_d_0 : svemem_gpr_shf p10_zer_lo.gov +11000101101xxxxx111xxxxxxxxxxxxx n 938 SVE ldff1d z_d_0 : svemem_vec_d_imm5 p10_zer_lo.gov +11000101111xxxxx111xxxxxxxxxxxxx n 938 SVE ldff1d z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +11000101110xxxxx111xxxxxxxxxxxxx n 938 SVE ldff1d z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +110001011x1xxxxx011xxxxxxxxxxxxx n 938 SVE ldff1d z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +110001011x0xxxxx011xxxxxxxxxxxxx n 938 SVE ldff1d z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +10100100101xxxxx011xxxxxxxxxxxxx n 939 SVE ldff1h z_h_0 : svemem_gpr_shf p10_zer_lo.gov +10100100110xxxxx011xxxxxxxxxxxxx n 939 SVE ldff1h z_s_0 : svemem_gpr_shf p10_zer_lo.gov +10100100111xxxxx011xxxxxxxxxxxxx n 939 SVE ldff1h z_d_0 : svemem_gpr_shf p10_zer_lo.gov +10000100101xxxxx111xxxxxxxxxxxxx n 939 SVE ldff1h z_s_0 : svemem_vec_s_imm5 p10_zer_lo.gov +11000100101xxxxx111xxxxxxxxxxxxx n 939 SVE ldff1h z_d_0 : svemem_vec_d_imm5 p10_zer_lo.gov +11000100111xxxxx111xxxxxxxxxxxxx n 939 SVE ldff1h z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +11000100110xxxxx111xxxxxxxxxxxxx n 939 SVE ldff1h z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +110001001x1xxxxx011xxxxxxxxxxxxx n 939 SVE ldff1h z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +110001001x0xxxxx011xxxxxxxxxxxxx n 939 SVE ldff1h z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +100001001x1xxxxx011xxxxxxxxxxxxx n 939 SVE ldff1h z_s_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +100001001x0xxxxx011xxxxxxxxxxxxx n 939 SVE ldff1h z_s_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +10100101110xxxxx011xxxxxxxxxxxxx n 940 SVE ldff1sb z_h_0 : svemem_gpr_shf p10_zer_lo.gov +10100101101xxxxx011xxxxxxxxxxxxx n 940 SVE ldff1sb z_s_0 : svemem_gpr_shf p10_zer_lo.gov +10100101100xxxxx011xxxxxxxxxxxxx n 940 SVE ldff1sb z_d_0 : svemem_gpr_shf p10_zer_lo.gov +10000100001xxxxx101xxxxxxxxxxxxx n 940 SVE ldff1sb z_s_0 : svemem_vec_s_imm5 p10_zer_lo.gov +11000100001xxxxx101xxxxxxxxxxxxx n 940 SVE ldff1sb z_d_0 : svemem_vec_d_imm5 p10_zer_lo.gov +11000100010xxxxx101xxxxxxxxxxxxx n 940 SVE ldff1sb z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +110001000x0xxxxx001xxxxxxxxxxxxx n 940 SVE ldff1sb z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +100001000x0xxxxx001xxxxxxxxxxxxx n 940 SVE ldff1sb z_s_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +10100101001xxxxx011xxxxxxxxxxxxx n 941 SVE ldff1sh z_s_0 : svemem_gpr_shf p10_zer_lo.gov +10100101000xxxxx011xxxxxxxxxxxxx n 941 SVE ldff1sh z_d_0 : svemem_gpr_shf p10_zer_lo.gov +10000100101xxxxx101xxxxxxxxxxxxx n 941 SVE ldff1sh z_s_0 : svemem_vec_s_imm5 p10_zer_lo.gov +11000100101xxxxx101xxxxxxxxxxxxx n 941 SVE ldff1sh z_d_0 : svemem_vec_d_imm5 p10_zer_lo.gov +11000100111xxxxx101xxxxxxxxxxxxx n 941 SVE ldff1sh z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +11000100110xxxxx101xxxxxxxxxxxxx n 941 SVE ldff1sh z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +110001001x1xxxxx001xxxxxxxxxxxxx n 941 SVE ldff1sh z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +110001001x0xxxxx001xxxxxxxxxxxxx n 941 SVE ldff1sh z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +100001001x1xxxxx001xxxxxxxxxxxxx n 941 SVE ldff1sh z_s_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +100001001x0xxxxx001xxxxxxxxxxxxx n 941 SVE ldff1sh z_s_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +10100100100xxxxx011xxxxxxxxxxxxx n 942 SVE ldff1sw z_d_0 : svemem_gpr_shf p10_zer_lo.gov +11000101001xxxxx101xxxxxxxxxxxxx n 942 SVE ldff1sw z_d_0 : svemem_vec_d_imm5 p10_zer_lo.gov +11000101011xxxxx101xxxxxxxxxxxxx n 942 SVE ldff1sw z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +11000101010xxxxx101xxxxxxxxxxxxx n 942 SVE ldff1sw z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +110001010x1xxxxx001xxxxxxxxxxxxx n 942 SVE ldff1sw z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +110001010x0xxxxx001xxxxxxxxxxxxx n 942 SVE ldff1sw z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +10100101010xxxxx011xxxxxxxxxxxxx n 943 SVE ldff1w z_s_0 : svemem_gpr_shf p10_zer_lo.gov +10100101011xxxxx011xxxxxxxxxxxxx n 943 SVE ldff1w z_d_0 : svemem_gpr_shf p10_zer_lo.gov +10000101001xxxxx111xxxxxxxxxxxxx n 943 SVE ldff1w z_s_0 : svemem_vec_s_imm5 p10_zer_lo.gov +11000101001xxxxx111xxxxxxxxxxxxx n 943 SVE ldff1w z_d_0 : svemem_vec_d_imm5 p10_zer_lo.gov +11000101011xxxxx111xxxxxxxxxxxxx n 943 SVE ldff1w z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +11000101010xxxxx111xxxxxxxxxxxxx n 943 SVE ldff1w z_d_0 : svemem_gpr_vec64 p10_zer_lo.gov +110001010x1xxxxx011xxxxxxxxxxxxx n 943 SVE ldff1w z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +110001010x0xxxxx011xxxxxxxxxxxxx n 943 SVE ldff1w z_d_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +100001010x1xxxxx011xxxxxxxxxxxxx n 943 SVE ldff1w z_s_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +100001010x0xxxxx011xxxxxxxxxxxxx n 943 SVE ldff1w z_s_0 : svemem_gpr_vec32_ld p10_zer_lo.gov +101001000011xxxx101xxxxxxxxxxxxx n 1007 SVE ldnf1b z_h_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001000101xxxx101xxxxxxxxxxxxx n 1007 SVE ldnf1b z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001000111xxxx101xxxxxxxxxxxxx n 1007 SVE ldnf1b z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001000001xxxx101xxxxxxxxxxxxx n 1007 SVE ldnf1b z_b_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001011111xxxx101xxxxxxxxxxxxx n 1008 SVE ldnf1d z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001001011xxxx101xxxxxxxxxxxxx n 1009 SVE ldnf1h z_h_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001001101xxxx101xxxxxxxxxxxxx n 1009 SVE ldnf1h z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001001111xxxx101xxxxxxxxxxxxx n 1009 SVE ldnf1h z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001011101xxxx101xxxxxxxxxxxxx n 1010 SVE ldnf1sb z_h_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001011011xxxx101xxxxxxxxxxxxx n 1010 SVE ldnf1sb z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001011001xxxx101xxxxxxxxxxxxx n 1010 SVE ldnf1sb z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001010011xxxx101xxxxxxxxxxxxx n 1011 SVE ldnf1sh z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001010001xxxx101xxxxxxxxxxxxx n 1011 SVE ldnf1sh z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001001001xxxx101xxxxxxxxxxxxx n 1012 SVE ldnf1sw z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001010101xxxx101xxxxxxxxxxxxx n 1013 SVE ldnf1w z_s_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +101001010111xxxx101xxxxxxxxxxxxx n 1013 SVE ldnf1w z_d_0 : svemem_gpr_simm4_vl_1reg p10_zer_lo.gov +10100100000xxxxx110xxxxxxxxxxxxx n 950 SVE ldnt1b z_b_0 : svemem_gprs_b1 p10_zer_lo.gov +101001000000xxxx111xxxxxxxxxxxxx n 950 SVE ldnt1b z_b_0 : svemem_gpr_simm4_vl_xreg p10_zer_lo.gov +10100101100xxxxx110xxxxxxxxxxxxx n 992 SVE ldnt1d z_msz_bhsd_0 : svemem_msz_gpr_shf p10_zer_lo.gov +101001011000xxxx111xxxxxxxxxxxxx n 992 SVE ldnt1d z_d_0 : svemem_gpr_simm4_vl_xreg p10_zer_lo.gov +10100100100xxxxx110xxxxxxxxxxxxx n 993 SVE ldnt1h z_msz_bhsd_0 : svemem_msz_gpr_shf p10_zer_lo.gov +101001001000xxxx111xxxxxxxxxxxxx n 993 SVE ldnt1h z_h_0 : svemem_gpr_simm4_vl_xreg p10_zer_lo.gov +10100101000xxxxx110xxxxxxxxxxxxx n 994 SVE ldnt1w z_msz_bhsd_0 : svemem_msz_gpr_shf p10_zer_lo.gov +101001010000xxxx111xxxxxxxxxxxxx n 994 SVE ldnt1w z_s_0 : svemem_gpr_simm4_vl_xreg p10_zer_lo.gov 1000010110xxxxxx000xxxxxxxx0xxxx n 227 SVE ldr p0 : svemem_gpr_simm9_vl 1000010110xxxxxx010xxxxxxxxxxxxx n 227 SVE ldr z0 : svemem_gpr_simm9_vl -00000100xx000011100xxxxxxxxxxxxx n 902 SVE lsl z_tszl8_bhsd_0 : p10_mrg_lo z_tszl8_bhsd_0 tszl8_imm3_5 -00000100xx011011100xxxxxxxxxxxxx n 902 SVE lsl z_size_bhs_0 : p10_mrg_lo z_size_bhs_0 z_d_5 -00000100xx010011100xxxxxxxxxxxxx n 902 SVE lsl z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +00000100xx000011100xxxxxxxxxxxxx n 902 SVE lsl z_tszl8_bhsd_0 : p10_mrg_lo.gov z_tszl8_bhsd_0 tszl8_imm3_5 +00000100xx011011100xxxxxxxxxxxxx n 902 SVE lsl z_size_bhs_0 : p10_mrg_lo.gov z_size_bhs_0 z_d_5 +00000100xx010011100xxxxxxxxxxxxx n 902 SVE lsl z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 00000100xx1xxxxx100111xxxxxxxxxx n 902 SVE lsl z_tszl19_bhsd_0 : z_tszl19_bhsd_5 tszl19_imm3_16 00000100xx1xxxxx100011xxxxxxxxxx n 902 SVE lsl z_size_bhs_0 : z_size_bhs_5 z_d_16 -00000100xx010111100xxxxxxxxxxxxx n 903 SVE lslr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -00000100xx000001100xxxxxxxxxxxxx n 904 SVE lsr z_tszl8_bhsd_0 : p10_mrg_lo z_tszl8_bhsd_0 tszl8_imm3_5p1 -00000100xx011001100xxxxxxxxxxxxx n 904 SVE lsr z_size_bhs_0 : p10_mrg_lo z_size_bhs_0 z_d_5 -00000100xx010001100xxxxxxxxxxxxx n 904 SVE lsr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +00000100xx010111100xxxxxxxxxxxxx n 903 SVE lslr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +00000100xx000001100xxxxxxxxxxxxx n 904 SVE lsr z_tszl8_bhsd_0 : p10_mrg_lo.gov z_tszl8_bhsd_0 tszl8_imm3_5p1 +00000100xx011001100xxxxxxxxxxxxx n 904 SVE lsr z_size_bhs_0 : p10_mrg_lo.gov z_size_bhs_0 z_d_5 +00000100xx010001100xxxxxxxxxxxxx n 904 SVE lsr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 00000100xx1xxxxx100101xxxxxxxxxx n 904 SVE lsr z_tszl19_bhsd_0 : z_tszl19_bhsd_5 tszl19_imm3_16p1 00000100xx1xxxxx100001xxxxxxxxxx n 904 SVE lsr z_size_bhs_0 : z_size_bhs_5 z_d_16 -00000100xx010101100xxxxxxxxxxxxx n 905 SVE lsrr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -00000100xx0xxxxx110xxxxxxxxxxxxx n 787 SVE mad z_size_bhsd_0 : z_size_bhsd_0 p10_mrg_lo z_size_bhsd_16 z_size_bhsd_5 -00000100xx0xxxxx010xxxxxxxxxxxxx n 312 SVE mla z_size_bhsd_0 : z_size_bhsd_0 p10_mrg_lo z_size_bhsd_5 z_size_bhsd_16 -00000100xx0xxxxx011xxxxxxxxxxxxx n 313 SVE mls z_size_bhsd_0 : z_size_bhsd_0 p10_mrg_lo z_size_bhsd_5 z_size_bhsd_16 +00000100xx010101100xxxxxxxxxxxxx n 905 SVE lsrr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +00000100xx0xxxxx110xxxxxxxxxxxxx n 787 SVE mad z_size_bhsd_0 : z_size_bhsd_0 p10_mrg_lo.gov z_size_bhsd_16 z_size_bhsd_5 +00000100xx0xxxxx010xxxxxxxxxxxxx n 312 SVE mla z_size_bhsd_0 : z_size_bhsd_0 p10_mrg_lo.gov z_size_bhsd_5 z_size_bhsd_16 +00000100xx0xxxxx011xxxxxxxxxxxxx n 313 SVE mls z_size_bhsd_0 : z_size_bhsd_0 p10_mrg_lo.gov z_size_bhsd_5 z_size_bhsd_16 0000010000100000101111xxxxxxxxxx n 783 SVE movprfx z0 : z5 -00000100xx010000001xxxxxxxxxxxxx n 783 SVE movprfx z_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 -00000100xx010001001xxxxxxxxxxxxx n 783 SVE movprfx z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_5 -00000100xx0xxxxx111xxxxxxxxxxxxx n 788 SVE msb z_size_bhsd_0 : z_size_bhsd_0 p10_mrg_lo z_size_bhsd_16 z_size_bhsd_5 -00000100xx010000000xxxxxxxxxxxxx n 321 SVE mul z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +00000100xx010000001xxxxxxxxxxxxx n 783 SVE movprfx z_size_bhsd_0 : p10_zer_lo.gov z_size_bhsd_5 +00000100xx010001001xxxxxxxxxxxxx n 783 SVE movprfx z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_5 +00000100xx0xxxxx111xxxxxxxxxxxxx n 788 SVE msb z_size_bhsd_0 : z_size_bhsd_0 p10_mrg_lo.gov z_size_bhsd_16 z_size_bhsd_5 +00000100xx010000000xxxxxxxxxxxxx n 321 SVE mul z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 00100101xx110000110xxxxxxxxxxxxx n 321 SVE mul z_size_bhsd_0 : z_size_bhsd_0 simm8_5 -001001011000xxxx01xxxx1xxxx1xxxx n 829 SVE nand p_b_0 : p10_zer p_b_5 p_b_16 -001001011100xxxx01xxxx1xxxx1xxxx w 830 SVE nands p_b_0 : p10_zer p_b_5 p_b_16 -00000100xx010111101xxxxxxxxxxxxx n 323 SVE neg z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_5 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SVE orv d0 : p10_lo z_size_bhsd_5 +00000100xx011000000xxxxxxxxxxxxx n 327 SVE orr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +001001011100xxxx01xxxx0xxxx0xxxx w 834 SVE orrs p_b_0 : p10_zer.gov p_b_5 p_b_16 +0000010000011000001xxxxxxxxxxxxx n 919 SVE orv b0 : p10_lo.gov z_size_bhsd_5 +0000010001011000001xxxxxxxxxxxxx n 919 SVE orv h0 : p10_lo.gov z_size_bhsd_5 +0000010010011000001xxxxxxxxxxxxx n 919 SVE orv s0 : p10_lo.gov z_size_bhsd_5 +0000010011011000001xxxxxxxxxxxxx n 919 SVE orv d0 : p10_lo.gov z_size_bhsd_5 0010010100011000111001000000xxxx n 894 SVE pfalse p_b_0 : -00100101010110001100000xxxx0xxxx w 895 SVE pfirst p_b_0 : p5 p_b_0 -00100101xx0110011100010xxxx0xxxx w 925 SVE pnext p_size_bhsd_0 : p5 p_size_bhsd_0 -1000010111xxxxxx000xxxxxxxx0xxxx n 963 SVE prfb : prfop4 p10_lo svemem_gpr_simm6_vl -10000100000xxxxx111xxxxxxxx0xxxx n 963 SVE prfb : prfop4 p10_lo svemem_vec_s_imm5 -11000100000xxxxx111xxxxxxxx0xxxx n 963 SVE prfb : prfop4 p10_lo svemem_vec_d_imm5 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: prfop4 p10_lo.gov sveprf_gpr_vec32 +10000100100xxxxx110xxxxxxxx0xxxx n 965 SVE prfh : prfop4 p10_lo.gov sveprf_gpr_shf +1000010111xxxxxx010xxxxxxxx0xxxx n 966 SVE prfw : prfop4 p10_lo.gov svemem_gpr_simm6_vl +10000101000xxxxx111xxxxxxxx0xxxx n 966 SVE prfw : prfop4 p10_lo.gov svemem_vec_s_imm5 +11000101000xxxxx111xxxxxxxx0xxxx n 966 SVE prfw : prfop4 p10_lo.gov svemem_vec_d_imm5 +11000100011xxxxx110xxxxxxxx0xxxx n 966 SVE prfw : prfop4 p10_lo.gov sveprf_gpr_vec64 +110001000x1xxxxx010xxxxxxxx0xxxx n 966 SVE prfw : prfop4 p10_lo.gov sveprf_gpr_vec32 +100001000x1xxxxx010xxxxxxxx0xxxx n 966 SVE prfw : prfop4 p10_lo.gov sveprf_gpr_vec32 +10000101000xxxxx110xxxxxxxx0xxxx n 966 SVE prfw : prfop4 p10_lo.gov sveprf_gpr_shf +001001010101000011xxxx0xxxx00000 w 786 SVE ptest : p10.gov p_b_5 00100101xx011000111000xxxxx0xxxx n 897 SVE ptrue p_size_bhsd_0 : pred_constr 00100101xx011001111000xxxxx0xxxx w 898 SVE ptrues p_size_bhsd_0 : pred_constr 00000101001100010100000xxxx0xxxx n 887 SVE punpkhi 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SVE splice z_size_bhsd_0 : p10_lo z_size_bhsd_0 z_size_bhsd_5 +00000100xx010010000xxxxxxxxxxxxx n 399 SVE smulh z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +00000101xx101100100xxxxxxxxxxxxx n 882 SVE splice z_size_bhsd_0 : p10_lo.gov z_size_bhsd_0 z_size_bhsd_5 00000100xx1xxxxx000100xxxxxxxxxx n 403 SVE sqadd z0 : z5 z16 bhsd_sz 00100101xx10010011xxxxxxxxxxxxxx n 403 SVE sqadd z_size_bhsd_0 : z_size_bhsd_0 imm8_5 lsl shift1 00000100xx1xxxxx000100xxxxxxxxxx n 403 SVE sqadd z_size_bhsd_0 : z_size_bhsd_5 z_size_bhsd_16 @@ -668,93 +668,93 @@ 00000100xx1xxxxx000110xxxxxxxxxx n 425 SVE sqsub z0 : z5 z16 bhsd_sz 00100101xx10011011xxxxxxxxxxxxxx n 425 SVE sqsub z_size_bhsd_0 : z_size_bhsd_0 imm8_5 lsl shift1 00000100xx1xxxxx000110xxxxxxxxxx n 425 SVE sqsub z_size_bhsd_0 : z_size_bhsd_5 z_size_bhsd_16 -11100100000xxxxx010xxxxxxxxxxxxx n 951 SVE st1b svemem_gpr_shf : z_b_0 p10_lo -11100100001xxxxx010xxxxxxxxxxxxx n 951 SVE st1b svemem_gpr_shf : z_h_0 p10_lo -11100100010xxxxx010xxxxxxxxxxxxx n 951 SVE st1b svemem_gpr_shf : z_s_0 p10_lo -11100100011xxxxx010xxxxxxxxxxxxx n 951 SVE st1b svemem_gpr_shf : z_d_0 p10_lo -11100100011xxxxx101xxxxxxxxxxxxx n 951 SVE st1b svemem_vec_s_imm5 : z_s_0 p10_lo -11100100010xxxxx101xxxxxxxxxxxxx n 951 SVE st1b svemem_vec_d_imm5 : z_d_0 p10_lo -11100100000xxxxx101xxxxxxxxxxxxx n 951 SVE st1b svemem_gpr_vec64 : z_d_0 p10_lo -11100100000xxxxx1x0xxxxxxxxxxxxx n 951 SVE st1b svemem_gpr_vec32_st : z_d_0 p10_lo -11100100010xxxxx1x0xxxxxxxxxxxxx n 951 SVE st1b svemem_gpr_vec32_st : z_s_0 p10_lo -111001000xx0xxxx111xxxxxxxxxxxxx n 951 SVE st1b svemem_gpr_simm4_vl_1reg : z_size21_bhsd_0 p10_lo -11100101110xxxxx101xxxxxxxxxxxxx n 981 SVE st1d svemem_vec_d_imm5 : z_d_0 p10_lo -11100101101xxxxx101xxxxxxxxxxxxx n 981 SVE st1d svemem_gpr_vec64 : z_d_0 p10_lo -11100101100xxxxx101xxxxxxxxxxxxx n 981 SVE st1d svemem_gpr_vec64 : z_d_0 p10_lo -11100101101xxxxx1x0xxxxxxxxxxxxx n 981 SVE st1d svemem_gpr_vec32_st : z_d_0 p10_lo -11100101100xxxxx1x0xxxxxxxxxxxxx n 981 SVE st1d svemem_gpr_vec32_st : z_d_0 p10_lo -11100101111xxxxx010xxxxxxxxxxxxx n 981 SVE st1d svemem_gpr_shf : z_msz_bhsd_0 p10_lo -111001011110xxxx111xxxxxxxxxxxxx n 981 SVE st1d svemem_gpr_simm4_vl_1reg : z_d_0 p10_lo -11100100111xxxxx101xxxxxxxxxxxxx n 980 SVE st1h svemem_vec_s_imm5 : z_s_0 p10_lo -11100100110xxxxx101xxxxxxxxxxxxx n 980 SVE st1h svemem_vec_d_imm5 : z_d_0 p10_lo -11100100101xxxxx101xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_vec64 : z_d_0 p10_lo -11100100100xxxxx101xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_vec64 : z_d_0 p10_lo -11100100101xxxxx1x0xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_vec32_st : z_d_0 p10_lo -11100100100xxxxx1x0xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_vec32_st : z_d_0 p10_lo -11100100111xxxxx1x0xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_vec32_st : z_s_0 p10_lo -11100100110xxxxx1x0xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_vec32_st : z_s_0 p10_lo -111001001xxxxxxx010xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_shf : z_size21_hsd_0 p10_lo -111001001xx0xxxx111xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_simm4_vl_1reg : z_size21_hsd_0 p10_lo -11100101011xxxxx101xxxxxxxxxxxxx n 982 SVE st1w svemem_vec_s_imm5 : z_s_0 p10_lo -11100101010xxxxx101xxxxxxxxxxxxx n 982 SVE st1w svemem_vec_d_imm5 : z_d_0 p10_lo -11100101001xxxxx101xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_vec64 : z_d_0 p10_lo -11100101000xxxxx101xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_vec64 : z_d_0 p10_lo -11100101001xxxxx1x0xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_vec32_st : z_d_0 p10_lo -11100101000xxxxx1x0xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_vec32_st : z_d_0 p10_lo -11100101011xxxxx1x0xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_vec32_st : z_s_0 p10_lo -11100101010xxxxx1x0xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_vec32_st : z_s_0 p10_lo -11100101010xxxxx010xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_shf : z_s_0 p10_lo -11100101011xxxxx010xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_shf : z_d_0 p10_lo -1110010101x0xxxx111xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_simm4_vl_1reg : z_sz21_sd_0 p10_lo -11100100001xxxxx011xxxxxxxxxxxxx n 970 SVE st2b svemem_gprs_bhsdx : z_b_0 z_msz_bhsd_0p1 p10_lo -111001000011xxxx111xxxxxxxxxxxxx n 970 SVE st2b svemem_gpr_simm4_vl_xreg : z_b_0 z_msz_bhsd_0p1 p10_lo -11100101101xxxxx011xxxxxxxxxxxxx n 995 SVE st2d svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 p10_lo -111001011011xxxx111xxxxxxxxxxxxx n 995 SVE st2d svemem_gpr_simm4_vl_xreg : z_d_0 z_msz_bhsd_0p1 p10_lo -11100100101xxxxx011xxxxxxxxxxxxx n 996 SVE st2h svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 p10_lo -111001001011xxxx111xxxxxxxxxxxxx n 996 SVE st2h svemem_gpr_simm4_vl_xreg : z_h_0 z_msz_bhsd_0p1 p10_lo -11100101001xxxxx011xxxxxxxxxxxxx n 997 SVE st2w svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 p10_lo -111001010011xxxx111xxxxxxxxxxxxx n 997 SVE st2w svemem_gpr_simm4_vl_xreg : z_s_0 z_msz_bhsd_0p1 p10_lo -11100100010xxxxx011xxxxxxxxxxxxx n 971 SVE st3b svemem_gprs_bhsdx : z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo -11100100010xxxxx011xxxxxxxxxxxxx n 971 SVE st3b svemem_gprs_bhsdx : z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo -111001000101xxxx111xxxxxxxxxxxxx n 971 SVE st3b svemem_gpr_simm4_vl_xreg : z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo -11100101110xxxxx011xxxxxxxxxxxxx n 998 SVE st3d svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo -111001011101xxxx111xxxxxxxxxxxxx n 998 SVE st3d svemem_gpr_simm4_vl_xreg : z_d_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo -11100100110xxxxx011xxxxxxxxxxxxx n 999 SVE st3h svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo -111001001101xxxx111xxxxxxxxxxxxx n 999 SVE st3h svemem_gpr_simm4_vl_xreg : z_h_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo -11100101010xxxxx011xxxxxxxxxxxxx n 1000 SVE st3w svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo -111001010101xxxx111xxxxxxxxxxxxx n 1000 SVE st3w svemem_gpr_simm4_vl_xreg : z_s_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo -11100100011xxxxx011xxxxxxxxxxxxx n 972 SVE st4b svemem_gprs_bhsdx : z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo -11100100011xxxxx011xxxxxxxxxxxxx n 972 SVE st4b svemem_gprs_bhsdx : z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo -111001000111xxxx111xxxxxxxxxxxxx n 972 SVE st4b svemem_gpr_simm4_vl_xreg : z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo -11100101111xxxxx011xxxxxxxxxxxxx n 1001 SVE st4d svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo -111001011111xxxx111xxxxxxxxxxxxx n 1001 SVE st4d svemem_gpr_simm4_vl_xreg : z_d_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo -11100100111xxxxx011xxxxxxxxxxxxx n 1002 SVE st4h svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo -111001001111xxxx111xxxxxxxxxxxxx n 1002 SVE st4h svemem_gpr_simm4_vl_xreg : z_h_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo -11100101011xxxxx011xxxxxxxxxxxxx n 1003 SVE st4w svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo -111001010111xxxx111xxxxxxxxxxxxx n 1003 SVE st4w svemem_gpr_simm4_vl_xreg : z_s_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo -11100100000xxxxx011xxxxxxxxxxxxx n 952 SVE stnt1b svemem_gprs_b1 : z_b_0 p10_lo -11100100000xxxxx011xxxxxxxxxxxxx n 952 SVE stnt1b svemem_gprs_b1 : z_b_0 p10_lo -111001000001xxxx111xxxxxxxxxxxxx n 952 SVE stnt1b svemem_gpr_simm4_vl_xreg : z_b_0 p10_lo -11100101100xxxxx011xxxxxxxxxxxxx n 1004 SVE stnt1d svemem_msz_stgpr_shf : z_msz_bhsd_0 p10_lo -111001011001xxxx111xxxxxxxxxxxxx n 1004 SVE stnt1d svemem_gpr_simm4_vl_xreg : z_d_0 p10_lo -11100100100xxxxx011xxxxxxxxxxxxx n 1005 SVE stnt1h svemem_msz_stgpr_shf : z_msz_bhsd_0 p10_lo -111001001001xxxx111xxxxxxxxxxxxx n 1005 SVE stnt1h svemem_gpr_simm4_vl_xreg : z_h_0 p10_lo -11100101000xxxxx011xxxxxxxxxxxxx n 1006 SVE stnt1w svemem_msz_stgpr_shf : z_msz_bhsd_0 p10_lo -111001010001xxxx111xxxxxxxxxxxxx n 1006 SVE stnt1w svemem_gpr_simm4_vl_xreg : z_s_0 p10_lo +11100100000xxxxx010xxxxxxxxxxxxx n 951 SVE st1b svemem_gpr_shf : z_b_0 p10_lo.gov +11100100001xxxxx010xxxxxxxxxxxxx n 951 SVE st1b svemem_gpr_shf : z_h_0 p10_lo.gov +11100100010xxxxx010xxxxxxxxxxxxx n 951 SVE st1b svemem_gpr_shf : z_s_0 p10_lo.gov +11100100011xxxxx010xxxxxxxxxxxxx n 951 SVE st1b svemem_gpr_shf : z_d_0 p10_lo.gov +11100100011xxxxx101xxxxxxxxxxxxx n 951 SVE st1b svemem_vec_s_imm5 : z_s_0 p10_lo.gov +11100100010xxxxx101xxxxxxxxxxxxx n 951 SVE st1b svemem_vec_d_imm5 : z_d_0 p10_lo.gov +11100100000xxxxx101xxxxxxxxxxxxx n 951 SVE st1b svemem_gpr_vec64 : z_d_0 p10_lo.gov +11100100000xxxxx1x0xxxxxxxxxxxxx n 951 SVE st1b svemem_gpr_vec32_st : z_d_0 p10_lo.gov +11100100010xxxxx1x0xxxxxxxxxxxxx n 951 SVE st1b svemem_gpr_vec32_st : z_s_0 p10_lo.gov +111001000xx0xxxx111xxxxxxxxxxxxx n 951 SVE st1b svemem_gpr_simm4_vl_1reg : z_size21_bhsd_0 p10_lo.gov +11100101110xxxxx101xxxxxxxxxxxxx n 981 SVE st1d svemem_vec_d_imm5 : z_d_0 p10_lo.gov +11100101101xxxxx101xxxxxxxxxxxxx n 981 SVE st1d svemem_gpr_vec64 : z_d_0 p10_lo.gov +11100101100xxxxx101xxxxxxxxxxxxx n 981 SVE st1d svemem_gpr_vec64 : z_d_0 p10_lo.gov +11100101101xxxxx1x0xxxxxxxxxxxxx n 981 SVE st1d svemem_gpr_vec32_st : z_d_0 p10_lo.gov +11100101100xxxxx1x0xxxxxxxxxxxxx n 981 SVE st1d svemem_gpr_vec32_st : z_d_0 p10_lo.gov +11100101111xxxxx010xxxxxxxxxxxxx n 981 SVE st1d svemem_gpr_shf : z_msz_bhsd_0 p10_lo.gov +111001011110xxxx111xxxxxxxxxxxxx n 981 SVE st1d svemem_gpr_simm4_vl_1reg : z_d_0 p10_lo.gov +11100100111xxxxx101xxxxxxxxxxxxx n 980 SVE st1h svemem_vec_s_imm5 : z_s_0 p10_lo.gov +11100100110xxxxx101xxxxxxxxxxxxx n 980 SVE st1h svemem_vec_d_imm5 : z_d_0 p10_lo.gov +11100100101xxxxx101xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_vec64 : z_d_0 p10_lo.gov +11100100100xxxxx101xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_vec64 : z_d_0 p10_lo.gov +11100100101xxxxx1x0xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_vec32_st : z_d_0 p10_lo.gov +11100100100xxxxx1x0xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_vec32_st : z_d_0 p10_lo.gov +11100100111xxxxx1x0xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_vec32_st : z_s_0 p10_lo.gov +11100100110xxxxx1x0xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_vec32_st : z_s_0 p10_lo.gov +111001001xxxxxxx010xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_shf : z_size21_hsd_0 p10_lo.gov +111001001xx0xxxx111xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_simm4_vl_1reg : z_size21_hsd_0 p10_lo.gov +11100101011xxxxx101xxxxxxxxxxxxx n 982 SVE st1w svemem_vec_s_imm5 : z_s_0 p10_lo.gov +11100101010xxxxx101xxxxxxxxxxxxx n 982 SVE st1w svemem_vec_d_imm5 : z_d_0 p10_lo.gov +11100101001xxxxx101xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_vec64 : z_d_0 p10_lo.gov +11100101000xxxxx101xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_vec64 : z_d_0 p10_lo.gov +11100101001xxxxx1x0xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_vec32_st : z_d_0 p10_lo.gov +11100101000xxxxx1x0xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_vec32_st : z_d_0 p10_lo.gov +11100101011xxxxx1x0xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_vec32_st : z_s_0 p10_lo.gov +11100101010xxxxx1x0xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_vec32_st : z_s_0 p10_lo.gov +11100101010xxxxx010xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_shf : z_s_0 p10_lo.gov +11100101011xxxxx010xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_shf : z_d_0 p10_lo.gov +1110010101x0xxxx111xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_simm4_vl_1reg : z_sz21_sd_0 p10_lo.gov +11100100001xxxxx011xxxxxxxxxxxxx n 970 SVE st2b svemem_gprs_bhsdx : z_b_0 z_msz_bhsd_0p1 p10_lo.gov +111001000011xxxx111xxxxxxxxxxxxx n 970 SVE st2b svemem_gpr_simm4_vl_xreg : z_b_0 z_msz_bhsd_0p1 p10_lo.gov +11100101101xxxxx011xxxxxxxxxxxxx n 995 SVE st2d svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 p10_lo.gov +111001011011xxxx111xxxxxxxxxxxxx n 995 SVE st2d svemem_gpr_simm4_vl_xreg : z_d_0 z_msz_bhsd_0p1 p10_lo.gov +11100100101xxxxx011xxxxxxxxxxxxx n 996 SVE st2h svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 p10_lo.gov +111001001011xxxx111xxxxxxxxxxxxx n 996 SVE st2h svemem_gpr_simm4_vl_xreg : z_h_0 z_msz_bhsd_0p1 p10_lo.gov +11100101001xxxxx011xxxxxxxxxxxxx n 997 SVE st2w svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 p10_lo.gov +111001010011xxxx111xxxxxxxxxxxxx n 997 SVE st2w svemem_gpr_simm4_vl_xreg : z_s_0 z_msz_bhsd_0p1 p10_lo.gov +11100100010xxxxx011xxxxxxxxxxxxx n 971 SVE st3b svemem_gprs_bhsdx : z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo.gov +11100100010xxxxx011xxxxxxxxxxxxx n 971 SVE st3b svemem_gprs_bhsdx : z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo.gov +111001000101xxxx111xxxxxxxxxxxxx n 971 SVE st3b svemem_gpr_simm4_vl_xreg : z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo.gov +11100101110xxxxx011xxxxxxxxxxxxx n 998 SVE st3d svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo.gov +111001011101xxxx111xxxxxxxxxxxxx n 998 SVE st3d svemem_gpr_simm4_vl_xreg : z_d_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo.gov +11100100110xxxxx011xxxxxxxxxxxxx n 999 SVE st3h svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo.gov +111001001101xxxx111xxxxxxxxxxxxx n 999 SVE st3h svemem_gpr_simm4_vl_xreg : z_h_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo.gov +11100101010xxxxx011xxxxxxxxxxxxx n 1000 SVE st3w svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo.gov +111001010101xxxx111xxxxxxxxxxxxx n 1000 SVE st3w svemem_gpr_simm4_vl_xreg : z_s_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo.gov +11100100011xxxxx011xxxxxxxxxxxxx n 972 SVE st4b svemem_gprs_bhsdx : z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo.gov +11100100011xxxxx011xxxxxxxxxxxxx n 972 SVE st4b svemem_gprs_bhsdx : z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo.gov +111001000111xxxx111xxxxxxxxxxxxx n 972 SVE st4b svemem_gpr_simm4_vl_xreg : z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo.gov +11100101111xxxxx011xxxxxxxxxxxxx n 1001 SVE st4d svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo.gov +111001011111xxxx111xxxxxxxxxxxxx n 1001 SVE st4d svemem_gpr_simm4_vl_xreg : z_d_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo.gov +11100100111xxxxx011xxxxxxxxxxxxx n 1002 SVE st4h svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo.gov +111001001111xxxx111xxxxxxxxxxxxx n 1002 SVE st4h svemem_gpr_simm4_vl_xreg : z_h_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo.gov +11100101011xxxxx011xxxxxxxxxxxxx n 1003 SVE st4w svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo.gov +111001010111xxxx111xxxxxxxxxxxxx n 1003 SVE st4w svemem_gpr_simm4_vl_xreg : z_s_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo.gov +11100100000xxxxx011xxxxxxxxxxxxx n 952 SVE stnt1b svemem_gprs_b1 : z_b_0 p10_lo.gov +11100100000xxxxx011xxxxxxxxxxxxx n 952 SVE stnt1b svemem_gprs_b1 : z_b_0 p10_lo.gov +111001000001xxxx111xxxxxxxxxxxxx n 952 SVE stnt1b svemem_gpr_simm4_vl_xreg : z_b_0 p10_lo.gov +11100101100xxxxx011xxxxxxxxxxxxx n 1004 SVE stnt1d svemem_msz_stgpr_shf : z_msz_bhsd_0 p10_lo.gov +111001011001xxxx111xxxxxxxxxxxxx n 1004 SVE stnt1d svemem_gpr_simm4_vl_xreg : z_d_0 p10_lo.gov +11100100100xxxxx011xxxxxxxxxxxxx n 1005 SVE stnt1h svemem_msz_stgpr_shf : z_msz_bhsd_0 p10_lo.gov +111001001001xxxx111xxxxxxxxxxxxx n 1005 SVE stnt1h svemem_gpr_simm4_vl_xreg : z_h_0 p10_lo.gov +11100101000xxxxx011xxxxxxxxxxxxx n 1006 SVE stnt1w svemem_msz_stgpr_shf : z_msz_bhsd_0 p10_lo.gov +111001010001xxxx111xxxxxxxxxxxxx n 1006 SVE stnt1w svemem_gpr_simm4_vl_xreg : z_s_0 p10_lo.gov 1110010110xxxxxx000xxxxxxxx0xxxx n 457 SVE str svemem_gpr_simm9_vl : p0 1110010110xxxxxx010xxxxxxxxxxxxx n 457 SVE str svemem_gpr_simm9_vl : z0 00000100xx1xxxxx000001xxxxxxxxxx n 470 SVE sub z0 : z5 z16 bhsd_sz -00000100xx000001000xxxxxxxxxxxxx n 470 SVE sub z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +00000100xx000001000xxxxxxxxxxxxx n 470 SVE sub z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 00100101xx10000111xxxxxxxxxxxxxx n 470 SVE sub z_size_bhsd_0 : z_size_bhsd_0 imm8_5 lsl shift1 00000100xx1xxxxx000001xxxxxxxxxx n 470 SVE sub z_size_bhsd_0 : z_size_bhsd_5 z_size_bhsd_16 -00000100xx000011000xxxxxxxxxxxxx n 784 SVE subr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +00000100xx000011000xxxxxxxxxxxxx n 784 SVE subr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 00100101xx10001111xxxxxxxxxxxxxx n 784 SVE subr z_size_bhsd_0 : z_size_bhsd_0 imm8_5 lsl shift1 01000100101xxxxx000111xxxxxxxxxx n 959 I8MM sudot z_s_0 : z_s_0 z_b_5 z3_b_16 i2_index_19 00000101xx110001001110xxxxxxxxxx n 889 SVE sunpkhi z_size_hsd_0 : z_tb_bhs_5 00000101xx110000001110xxxxxxxxxx n 890 SVE sunpklo z_size_hsd_0 : z_tb_bhs_5 -00000100xx010000101xxxxxxxxxxxxx n 799 SVE sxtb z_size_hsd_0 : p10_mrg_lo z_size_hsd_5 -00000100xx010010101xxxxxxxxxxxxx n 800 SVE sxth z_size_sd_0 : p10_mrg_lo z_size_sd_5 -0000010011010100101xxxxxxxxxxxxx n 801 SVE sxtw z_d_0 : p10_mrg_lo z_d_5 +00000100xx010000101xxxxxxxxxxxxx n 799 SVE sxtb z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_5 +00000100xx010010101xxxxxxxxxxxxx n 800 SVE sxth z_size_sd_0 : p10_mrg_lo.gov z_size_sd_5 +0000010011010100101xxxxxxxxxxxxx n 801 SVE sxtw z_d_0 : p10_mrg_lo.gov z_d_5 00000101xx1xxxxx001100xxxxxxxxxx n 490 SVE tbl z_size_bhsd_0 : z_size_bhsd_5 z_size_bhsd_16 00000101xx10xxxx0101000xxxx0xxxx n 494 SVE trn1 p_size_bhsd_0 : p_size_bhsd_5 p_size_bhsd_16 00000101xx1xxxxx011100xxxxxxxxxx n 494 SVE trn1 z_size_bhsd_0 : z_size_bhsd_5 z_size_bhsd_16 @@ -762,35 +762,35 @@ 00000101xx10xxxx0101010xxxx0xxxx n 495 SVE trn2 p_size_bhsd_0 : p_size_bhsd_5 p_size_bhsd_16 00000101xx1xxxxx011101xxxxxxxxxx n 495 SVE trn2 z_size_bhsd_0 : z_size_bhsd_5 z_size_bhsd_16 00000101101xxxxx000111xxxxxxxxxx n 495 F64MM trn2 z_q_0 : z_q_5 z_q_16 -00000100xx001101000xxxxxxxxxxxxx n 499 SVE uabd z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -00000100xx000001001xxxxxxxxxxxxx n 921 SVE uaddv d0 : p10_lo z_size_bhsd_5 -0110010101010011101xxxxxxxxxxxxx n 510 SVE ucvtf z_h_0 : p10_mrg_lo z_h_5 -0110010111010001101xxxxxxxxxxxxx n 510 SVE ucvtf z_d_0 : p10_mrg_lo z_s_5 -0110010101010101101xxxxxxxxxxxxx n 510 SVE ucvtf z_h_0 : p10_mrg_lo z_s_5 -0110010110010101101xxxxxxxxxxxxx n 510 SVE ucvtf z_s_0 : p10_mrg_lo z_s_5 -0110010111010111101xxxxxxxxxxxxx n 510 SVE ucvtf z_d_0 : p10_mrg_lo z_d_5 -0110010101010111101xxxxxxxxxxxxx n 510 SVE ucvtf z_h_0 : p10_mrg_lo z_d_5 -0110010111010101101xxxxxxxxxxxxx n 510 SVE ucvtf z_s_0 : p10_mrg_lo z_d_5 -00000100xx010101000xxxxxxxxxxxxx n 511 SVE udiv z_size_sd_0 : p10_mrg_lo z_size_sd_0 z_size_sd_5 -00000100xx010111000xxxxxxxxxxxxx n 795 SVE udivr z_size_sd_0 : p10_mrg_lo z_size_sd_0 z_size_sd_5 +00000100xx001101000xxxxxxxxxxxxx n 499 SVE uabd z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +00000100xx000001001xxxxxxxxxxxxx n 921 SVE uaddv d0 : p10_lo.gov z_size_bhsd_5 +0110010101010011101xxxxxxxxxxxxx n 510 SVE ucvtf z_h_0 : p10_mrg_lo.gov z_h_5 +0110010111010001101xxxxxxxxxxxxx n 510 SVE ucvtf z_d_0 : p10_mrg_lo.gov z_s_5 +0110010101010101101xxxxxxxxxxxxx n 510 SVE ucvtf z_h_0 : p10_mrg_lo.gov z_s_5 +0110010110010101101xxxxxxxxxxxxx n 510 SVE ucvtf z_s_0 : p10_mrg_lo.gov z_s_5 +0110010111010111101xxxxxxxxxxxxx n 510 SVE ucvtf z_d_0 : p10_mrg_lo.gov z_d_5 +0110010101010111101xxxxxxxxxxxxx n 510 SVE ucvtf z_h_0 : p10_mrg_lo.gov z_d_5 +0110010111010101101xxxxxxxxxxxxx n 510 SVE ucvtf z_s_0 : p10_mrg_lo.gov z_d_5 +00000100xx010101000xxxxxxxxxxxxx n 511 SVE udiv z_size_sd_0 : p10_mrg_lo.gov z_size_sd_0 z_size_sd_5 +00000100xx010111000xxxxxxxxxxxxx n 795 SVE udivr z_size_sd_0 : p10_mrg_lo.gov z_size_sd_0 z_size_sd_5 01000100110xxxxx000001xxxxxxxxxx n 512 SVE udot z_d_0 : z_d_0 z_h_5 z_h_16 01000100100xxxxx000001xxxxxxxxxx n 512 SVE udot z_s_0 : z_s_0 z_b_5 z_b_16 01000100111xxxxx000001xxxxxxxxxx n 512 SVE udot z_d_0 : z_d_0 z_h_5 z4_h_16 i1_index_20 01000100101xxxxx000001xxxxxxxxxx n 512 SVE udot z_s_0 : z_s_0 z_b_5 z3_b_16 i2_index_19 -00000100xx001001000xxxxxxxxxxxxx n 516 SVE umax z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +00000100xx001001000xxxxxxxxxxxxx n 516 SVE umax z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 00100101xx101001110xxxxxxxxxxxxx n 516 SVE umax z_size_bhsd_0 : z_size_bhsd_0 imm8_5 -0000010000001001001xxxxxxxxxxxxx n 518 SVE umaxv b0 : p10_lo z_size_bhsd_5 -0000010001001001001xxxxxxxxxxxxx n 518 SVE umaxv h0 : p10_lo z_size_bhsd_5 -0000010010001001001xxxxxxxxxxxxx n 518 SVE umaxv s0 : p10_lo z_size_bhsd_5 -0000010011001001001xxxxxxxxxxxxx n 518 SVE umaxv d0 : p10_lo z_size_bhsd_5 -00000100xx001011000xxxxxxxxxxxxx n 519 SVE umin z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +0000010000001001001xxxxxxxxxxxxx n 518 SVE umaxv b0 : p10_lo.gov z_size_bhsd_5 +0000010001001001001xxxxxxxxxxxxx n 518 SVE umaxv h0 : p10_lo.gov z_size_bhsd_5 +0000010010001001001xxxxxxxxxxxxx n 518 SVE umaxv s0 : p10_lo.gov z_size_bhsd_5 +0000010011001001001xxxxxxxxxxxxx n 518 SVE umaxv d0 : p10_lo.gov z_size_bhsd_5 +00000100xx001011000xxxxxxxxxxxxx n 519 SVE umin z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 00100101xx101011110xxxxxxxxxxxxx n 519 SVE umin z_size_bhsd_0 : z_size_bhsd_0 imm8_5 -0000010000001011001xxxxxxxxxxxxx n 521 SVE uminv b0 : p10_lo z_size_bhsd_5 -0000010001001011001xxxxxxxxxxxxx n 521 SVE uminv h0 : p10_lo z_size_bhsd_5 -0000010010001011001xxxxxxxxxxxxx n 521 SVE uminv s0 : p10_lo z_size_bhsd_5 -0000010011001011001xxxxxxxxxxxxx n 521 SVE uminv d0 : p10_lo z_size_bhsd_5 +0000010000001011001xxxxxxxxxxxxx n 521 SVE uminv b0 : p10_lo.gov z_size_bhsd_5 +0000010001001011001xxxxxxxxxxxxx n 521 SVE uminv h0 : p10_lo.gov z_size_bhsd_5 +0000010010001011001xxxxxxxxxxxxx n 521 SVE uminv s0 : p10_lo.gov z_size_bhsd_5 +0000010011001011001xxxxxxxxxxxxx n 521 SVE uminv d0 : p10_lo.gov z_size_bhsd_5 01000101110xxxxx100110xxxxxxxxxx n 960 I8MM ummla z_s_0 : z_s_0 z_b_5 z_b_16 -00000100xx010011000xxxxxxxxxxxxx n 528 SVE umulh z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +00000100xx010011000xxxxxxxxxxxxx n 528 SVE umulh z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 00000100xx1xxxxx000101xxxxxxxxxx n 531 SVE uqadd z0 : z5 z16 bhsd_sz 00100101xx10010111xxxxxxxxxxxxxx n 531 SVE uqadd z_size_bhsd_0 : z_size_bhsd_0 imm8_5 lsl shift1 00000100xx1xxxxx000101xxxxxxxxxx n 531 SVE uqadd z_size_bhsd_0 : z_size_bhsd_5 z_size_bhsd_16 @@ -830,9 +830,9 @@ 01000101100xxxxx100110xxxxxxxxxx n 962 I8MM usmmla z_s_0 : z_s_0 z_b_5 z_b_16 00000101xx110011001110xxxxxxxxxx n 891 SVE uunpkhi z_size_hsd_0 : z_tb_bhs_5 00000101xx110010001110xxxxxxxxxx n 892 SVE uunpklo z_size_hsd_0 : z_tb_bhs_5 -00000100xx010001101xxxxxxxxxxxxx n 802 SVE uxtb z_size_hsd_0 : p10_mrg_lo z_size_hsd_5 -00000100xx010011101xxxxxxxxxxxxx n 803 SVE uxth z_size_sd_0 : p10_mrg_lo z_size_sd_5 -0000010011010101101xxxxxxxxxxxxx n 804 SVE uxtw z_d_0 : p10_mrg_lo z_d_5 +00000100xx010001101xxxxxxxxxxxxx n 802 SVE uxtb z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_5 +00000100xx010011101xxxxxxxxxxxxx n 803 SVE uxth z_size_sd_0 : p10_mrg_lo.gov z_size_sd_5 +0000010011010101101xxxxxxxxxxxxx n 804 SVE uxtw z_d_0 : p10_mrg_lo.gov z_d_5 00000101xx10xxxx0100100xxxx0xxxx n 557 SVE uzp1 p_size_bhsd_0 : p_size_bhsd_5 p_size_bhsd_16 00000101xx1xxxxx011010xxxxxxxxxx n 557 SVE uzp1 z_size_bhsd_0 : z_size_bhsd_5 z_size_bhsd_16 00000101101xxxxx000010xxxxxxxxxx n 557 F64MM uzp1 z_q_0 : z_q_5 z_q_16 diff --git a/core/ir/aarch64/codec_sve2.txt b/core/ir/aarch64/codec_sve2.txt index b041942fec1..4b3dda25493 100644 --- a/core/ir/aarch64/codec_sve2.txt +++ b/core/ir/aarch64/codec_sve2.txt @@ -42,7 +42,7 @@ 01000101010xxxxx110101xxxxxxxxxx n 1074 SVE2 adclt z_d_0 : z_d_0 z_d_5 z_d_16 01000101xx1xxxxx011000xxxxxxxxxx n 1082 SVE2 addhnb z_sizep1_bhs_0 : z_size_hsd_5 z_size_hsd_16 01000101xx1xxxxx011001xxxxxxxxxx n 1083 SVE2 addhnt z_sizep1_bhs_0 : z_sizep1_bhs_0 z_size_hsd_5 z_size_hsd_16 -01000100xx010001101xxxxxxxxxxxxx n 12 SVE2 addp z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +01000100xx010001101xxxxxxxxxxxxx n 12 SVE2 addp z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 0100010100100010111001xxxxxxxxxx n 17 SVEAES aesd z_b_0 : z_b_0 z_b_5 0100010100100010111000xxxxxxxxxx n 18 SVEAES aese z_b_0 : z_b_0 z_b_5 010001010010000011100100000xxxxx n 19 SVEAES aesimc z_b_0 : z_b_0 @@ -64,18 +64,18 @@ 00000100001xxxxx001110xxxxxxxxxx n 600 SVE2 eor3 z_d_0 : z_d_0 z_d_16 z_d_5 01000101xx0xxxxx100100xxxxxxxxxx n 1078 SVE2 eorbt z_size_bhsd_0 : z_size_bhsd_0 z_size_bhsd_5 z_size_bhsd_16 01000101xx0xxxxx100101xxxxxxxxxx n 1079 SVE2 eortb z_size_bhsd_0 : z_size_bhsd_0 z_size_bhsd_5 z_size_bhsd_16 -01100100xx010000100xxxxxxxxxxxxx n 99 SVE2 faddp z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 -0110010010001001101xxxxxxxxxxxxx n 1156 SVE2 fcvtlt z_s_0 : p10_mrg_lo z_msz_bhsd_5 -0110010011001011101xxxxxxxxxxxxx n 1156 SVE2 fcvtlt z_d_0 : p10_mrg_lo z_s_5 -0110010011001010101xxxxxxxxxxxxx n 1157 SVE2 fcvtnt z_s_0 : z_s_0 p10_mrg_lo z_d_5 -0110010010001000101xxxxxxxxxxxxx n 1157 SVE2 fcvtnt z_msz_bhsd_0 : z_msz_bhsd_0 p10_mrg_lo z_s_5 -0110010100001010101xxxxxxxxxxxxx n 1158 SVE2 fcvtx z_msz_bhsd_0 : p10_mrg_lo z_d_5 -0110010000001010101xxxxxxxxxxxxx n 1159 SVE2 fcvtxnt z_s_0 : z_s_0 p10_mrg_lo z_d_5 -0110010100011xx0101xxxxxxxxxxxxx n 1160 SVE2 flogb z_size17_hsd_0 : p10_mrg_lo z_size17_hsd_5 -01100100xx010100100xxxxxxxxxxxxx n 131 SVE2 fmaxnmp z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 -01100100xx010110100xxxxxxxxxxxxx n 133 SVE2 fmaxp z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 -01100100xx010101100xxxxxxxxxxxxx n 137 SVE2 fminnmp z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 -01100100xx010111100xxxxxxxxxxxxx n 139 SVE2 fminp z_size_hsd_0 : p10_mrg_lo z_size_hsd_0 z_size_hsd_5 +01100100xx010000100xxxxxxxxxxxxx n 99 SVE2 faddp z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 +0110010010001001101xxxxxxxxxxxxx n 1156 SVE2 fcvtlt z_s_0 : p10_mrg_lo.gov z_msz_bhsd_5 +0110010011001011101xxxxxxxxxxxxx n 1156 SVE2 fcvtlt z_d_0 : p10_mrg_lo.gov z_s_5 +0110010011001010101xxxxxxxxxxxxx n 1157 SVE2 fcvtnt z_s_0 : z_s_0 p10_mrg_lo.gov z_d_5 +0110010010001000101xxxxxxxxxxxxx n 1157 SVE2 fcvtnt z_msz_bhsd_0 : z_msz_bhsd_0 p10_mrg_lo.gov z_s_5 +0110010100001010101xxxxxxxxxxxxx n 1158 SVE2 fcvtx z_msz_bhsd_0 : p10_mrg_lo.gov z_d_5 +0110010000001010101xxxxxxxxxxxxx n 1159 SVE2 fcvtxnt z_s_0 : z_s_0 p10_mrg_lo.gov z_d_5 +0110010100011xx0101xxxxxxxxxxxxx n 1160 SVE2 flogb z_size17_hsd_0 : p10_mrg_lo.gov z_size17_hsd_5 +01100100xx010100100xxxxxxxxxxxxx n 131 SVE2 fmaxnmp z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 +01100100xx010110100xxxxxxxxxxxxx n 133 SVE2 fmaxp z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 +01100100xx010101100xxxxxxxxxxxxx n 137 SVE2 fminnmp z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 +01100100xx010111100xxxxxxxxxxxxx n 139 SVE2 fminp z_size_hsd_0 : p10_mrg_lo.gov z_size_hsd_0 z_size_hsd_5 01100100101xxxxx100000xxxxxxxxxx n 1067 SVE2 fmlalb z_s_0 : z_s_0 z_msz_bhsd_5 z_msz_bhsd_16 01100100101xxxxx0100x0xxxxxxxxxx n 1067 SVE2 fmlalb z_s_0 : z_s_0 z_msz_bhsd_5 z3_msz_bhsd_16 i3_index_11 01100100101xxxxx100001xxxxxxxxxx n 1068 SVE2 fmlalt z_s_0 : z_s_0 z_msz_bhsd_5 z_msz_bhsd_16 @@ -84,27 +84,27 @@ 01100100101xxxxx0110x0xxxxxxxxxx n 1069 SVE2 fmlslb z_s_0 : z_s_0 z_msz_bhsd_5 z3_msz_bhsd_16 i3_index_11 01100100101xxxxx101001xxxxxxxxxx n 1070 SVE2 fmlslt z_s_0 : z_s_0 z_msz_bhsd_5 z_msz_bhsd_16 01100100101xxxxx0110x1xxxxxxxxxx n 1070 SVE2 fmlslt z_s_0 : z_s_0 z_msz_bhsd_5 z3_msz_bhsd_16 i3_index_11 -01000101xx1xxxxx110xxxxxxxxxxxxx n 1145 SVE2 histcnt z_size_sd_0 : p10_zer_lo z_size_sd_5 z_size_sd_16 +01000101xx1xxxxx110xxxxxxxxxxxxx n 1145 SVE2 histcnt z_size_sd_0 : p10_zer_lo.gov z_size_sd_5 z_size_sd_16 01000101001xxxxx101000xxxxxxxxxx n 1071 SVE2 histseg z_b_0 : z_b_5 z_b_16 -11000100000xxxxx110xxxxxxxxxxxxx n 950 SVE2 ldnt1b z_d_0 : svemem_vec_30sd_gpr16 p10_zer_lo -10000100000xxxxx101xxxxxxxxxxxxx n 950 SVE2 ldnt1b z_s_0 : svemem_vec_30sd_gpr16 p10_zer_lo -11000101100xxxxx110xxxxxxxxxxxxx n 992 SVE2 ldnt1d z_d_0 : svemem_vec_30sd_gpr16 p10_zer_lo -11000100100xxxxx110xxxxxxxxxxxxx n 993 SVE2 ldnt1h z_d_0 : svemem_vec_30sd_gpr16 p10_zer_lo -10000100100xxxxx101xxxxxxxxxxxxx n 993 SVE2 ldnt1h z_s_0 : svemem_vec_30sd_gpr16 p10_zer_lo -11000100000xxxxx100xxxxxxxxxxxxx n 1186 SVE2 ldnt1sb z_d_0 : svemem_vec_30sd_gpr16 p10_zer_lo -10000100000xxxxx100xxxxxxxxxxxxx n 1186 SVE2 ldnt1sb z_s_0 : svemem_vec_30sd_gpr16 p10_zer_lo -11000100100xxxxx100xxxxxxxxxxxxx n 1187 SVE2 ldnt1sh z_d_0 : svemem_vec_30sd_gpr16 p10_zer_lo -10000100100xxxxx100xxxxxxxxxxxxx n 1187 SVE2 ldnt1sh z_s_0 : svemem_vec_30sd_gpr16 p10_zer_lo -11000101000xxxxx100xxxxxxxxxxxxx n 1188 SVE2 ldnt1sw z_d_0 : svemem_vec_30sd_gpr16 p10_zer_lo -11000101000xxxxx110xxxxxxxxxxxxx n 994 SVE2 ldnt1w z_d_0 : svemem_vec_30sd_gpr16 p10_zer_lo -10000101000xxxxx101xxxxxxxxxxxxx n 994 SVE2 ldnt1w z_s_0 : svemem_vec_30sd_gpr16 p10_zer_lo -01000101xx1xxxxx100xxxxxxxx0xxxx w 1189 SVE2 match p_size_bh_0 : p10_zer_lo z_size_bh_5 z_size_bh_16 +11000100000xxxxx110xxxxxxxxxxxxx n 950 SVE2 ldnt1b z_d_0 : svemem_vec_30sd_gpr16 p10_zer_lo.gov +10000100000xxxxx101xxxxxxxxxxxxx n 950 SVE2 ldnt1b z_s_0 : svemem_vec_30sd_gpr16 p10_zer_lo.gov +11000101100xxxxx110xxxxxxxxxxxxx n 992 SVE2 ldnt1d z_d_0 : svemem_vec_30sd_gpr16 p10_zer_lo.gov +11000100100xxxxx110xxxxxxxxxxxxx n 993 SVE2 ldnt1h z_d_0 : svemem_vec_30sd_gpr16 p10_zer_lo.gov +10000100100xxxxx101xxxxxxxxxxxxx n 993 SVE2 ldnt1h z_s_0 : svemem_vec_30sd_gpr16 p10_zer_lo.gov +11000100000xxxxx100xxxxxxxxxxxxx n 1186 SVE2 ldnt1sb z_d_0 : svemem_vec_30sd_gpr16 p10_zer_lo.gov +10000100000xxxxx100xxxxxxxxxxxxx n 1186 SVE2 ldnt1sb z_s_0 : svemem_vec_30sd_gpr16 p10_zer_lo.gov +11000100100xxxxx100xxxxxxxxxxxxx n 1187 SVE2 ldnt1sh z_d_0 : svemem_vec_30sd_gpr16 p10_zer_lo.gov +10000100100xxxxx100xxxxxxxxxxxxx n 1187 SVE2 ldnt1sh z_s_0 : svemem_vec_30sd_gpr16 p10_zer_lo.gov +11000101000xxxxx100xxxxxxxxxxxxx n 1188 SVE2 ldnt1sw z_d_0 : svemem_vec_30sd_gpr16 p10_zer_lo.gov +11000101000xxxxx110xxxxxxxxxxxxx n 994 SVE2 ldnt1w z_d_0 : svemem_vec_30sd_gpr16 p10_zer_lo.gov +10000101000xxxxx101xxxxxxxxxxxxx n 994 SVE2 ldnt1w z_s_0 : svemem_vec_30sd_gpr16 p10_zer_lo.gov +01000101xx1xxxxx100xxxxxxxx0xxxx w 1189 SVE2 match p_size_bh_0 : p10_zer_lo.gov z_size_bh_5 z_size_bh_16 00000100xx1xxxxx011000xxxxxxxxxx n 321 SVE2 mul z_size_bhsd_0 : z_size_bhsd_5 z_size_bhsd_16 01000100111xxxxx111110xxxxxxxxxx n 321 SVE2 mul z_d_0 : z_d_5 z4_d_16 i1_index_20 010001000x1xxxxx111110xxxxxxxxxx n 321 SVE2 mul z_h_0 : z_h_5 z3_h_16 i3_index_19 01000100101xxxxx111110xxxxxxxxxx n 321 SVE2 mul z_s_0 : z_s_5 z3_s_16 i2_index_19 00000100111xxxxx001111xxxxxxxxxx n 1072 SVE2 nbsl z_d_0 : z_d_0 z_d_16 z_d_5 -01000101xx1xxxxx100xxxxxxxx1xxxx w 1190 SVE2 nmatch p_size_bh_0 : p10_zer_lo z_size_bh_5 z_size_bh_16 +01000101xx1xxxxx100xxxxxxxx1xxxx w 1190 SVE2 nmatch p_size_bh_0 : p10_zer_lo.gov z_size_bh_5 z_size_bh_16 00000100001xxxxx011001xxxxxxxxxx n 328 SVE2 pmul z_msz_bhsd_0 : z_msz_bhsd_5 z_msz_bhsd_16 01000101xx0xxxxx011010xxxxxxxxxx n 1084 SVE2 pmullb z_size_hd_0 : z_sizep1_bs_5 z_sizep1_bs_16 01000101xx0xxxxx011011xxxxxxxxxx n 1085 SVE2 pmullt z_size_hd_0 : z_sizep1_bs_5 z_sizep1_bs_16 @@ -120,7 +120,7 @@ 01000101xx0xxxxx110001xxxxxxxxxx n 1091 SVE2 sabalt z_size_hsd_0 : z_size_hsd_0 z_sizep1_bhs_5 z_sizep1_bhs_16 01000101xx0xxxxx001100xxxxxxxxxx n 1092 SVE2 sabdlb z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16 01000101xx0xxxxx001101xxxxxxxxxx n 1093 SVE2 sabdlt z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16 -01000100xx000100101xxxxxxxxxxxxx n 352 SVE2 sadalp z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo z_sizep1_bhs_5 +01000100xx000100101xxxxxxxxxxxxx n 352 SVE2 sadalp z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo.gov z_sizep1_bhs_5 01000101xx0xxxxx000000xxxxxxxxxx n 1094 SVE2 saddlb z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16 01000101xx0xxxxx100000xxxxxxxxxx n 1095 SVE2 saddlbt z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16 01000101xx0xxxxx000001xxxxxxxxxx n 1096 SVE2 saddlt z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16 @@ -130,16 +130,16 @@ 01000101110xxxxx110100xxxxxxxxxx n 1080 SVE2 sbclb z_d_0 : z_d_0 z_d_5 z_d_16 01000101100xxxxx110101xxxxxxxxxx n 1081 SVE2 sbclt z_s_0 : z_s_0 z_s_5 z_s_16 01000101110xxxxx110101xxxxxxxxxx n 1081 SVE2 sbclt z_d_0 : z_d_0 z_d_5 z_d_16 -01000100xx010000100xxxxxxxxxxxxx n 377 SVE2 shadd z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +01000100xx010000100xxxxxxxxxxxxx n 377 SVE2 shadd z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 010001010x1xxxxx000100xxxxxxxxxx n 1166 SVE2 shrnb z_tszl19_bhs_0 : z_tszl19p1_hsd_5 tszl19lo_imm3_16p1 010001010x1xxxxx000101xxxxxxxxxx n 1167 SVE2 shrnt z_tszl19_bhs_0 : z_tszl19_bhs_0 z_tszl19p1_hsd_5 tszl19lo_imm3_16p1 -01000100xx010010100xxxxxxxxxxxxx n 383 SVE2 shsub z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -01000100xx010110100xxxxxxxxxxxxx n 1146 SVE2 shsubr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +01000100xx010010100xxxxxxxxxxxxx n 383 SVE2 shsub z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +01000100xx010110100xxxxxxxxxxxxx n 1146 SVE2 shsubr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 01000101xx0xxxxx111101xxxxxxxxxx n 384 SVE2 sli z_tszl19_bhsd_0 : z_tszl19_bhsd_0 z_tszl19_bhsd_5 tszl19_imm3_16 0100010100100011111000xxxxxxxxxx n 593 SVESM4 sm4e z_msz_bhsd_0 : z_msz_bhsd_0 z_msz_bhsd_5 01000101001xxxxx111100xxxxxxxxxx n 594 SVESM4 sm4ekey z_msz_bhsd_0 : z_msz_bhsd_5 z_msz_bhsd_16 -01000100xx010100101xxxxxxxxxxxxx n 387 SVE2 smaxp z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -01000100xx010110101xxxxxxxxxxxxx n 391 SVE2 sminp z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +01000100xx010100101xxxxxxxxxxxxx n 387 SVE2 smaxp z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +01000100xx010110101xxxxxxxxxxxxx n 391 SVE2 sminp z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 01000100xx0xxxxx010000xxxxxxxxxx n 1099 SVE2 smlalb z_size_hsd_0 : z_size_hsd_0 z_sizep1_bhs_5 z_sizep1_bhs_16 01000100111xxxxx1000x0xxxxxxxxxx n 1099 SVE2 smlalb z_d_0 : z_d_0 z_s_5 z4_s_16 i2_index_11 01000100101xxxxx1000x0xxxxxxxxxx n 1099 SVE2 smlalb z_s_0 : z_s_0 z_msz_bhsd_5 z3_msz_bhsd_16 i3_index_11 @@ -158,8 +158,8 @@ 01000101xx0xxxxx011101xxxxxxxxxx n 1104 SVE2 smullt z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16 01000100111xxxxx1100x1xxxxxxxxxx n 1104 SVE2 smullt z_d_0 : z_s_5 z4_s_16 i2_index_11 01000100101xxxxx1100x1xxxxxxxxxx n 1104 SVE2 smullt z_s_0 : z_msz_bhsd_5 z3_msz_bhsd_16 i3_index_11 -00000101xx101101100xxxxxxxxxxxxx n 882 SVE2 splice z_size_bhsd_0 : p10_lo z_size_bhsd_5 z_size_bhsd_5p1 -01000100xx001000101xxxxxxxxxxxxx n 402 SVE2 sqabs z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_5 +00000101xx101101100xxxxxxxxxxxxx n 882 SVE2 splice z_size_bhsd_0 : p10_lo.gov z_size_bhsd_5 z_size_bhsd_5p1 +01000100xx001000101xxxxxxxxxxxxx n 402 SVE2 sqabs z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_5 01000101xx00000111011xxxxxxxxxxx n 1168 SVE2 sqcadd z_size_bhsd_0 : z_size_bhsd_0 z_size_bhsd_5 imm1_ew_10 01000100xx0xxxxx011000xxxxxxxxxx n 1105 SVE2 sqdmlalb z_size_hsd_0 : z_size_hsd_0 z_sizep1_bhs_5 z_sizep1_bhs_16 01000100111xxxxx0010x0xxxxxxxxxx n 1105 SVE2 sqdmlalb z_d_0 : z_d_0 z_s_5 z4_s_16 i2_index_11 @@ -185,7 +185,7 @@ 01000101xx0xxxxx011001xxxxxxxxxx n 1112 SVE2 sqdmullt z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16 01000100111xxxxx1110x1xxxxxxxxxx n 1112 SVE2 sqdmullt z_d_0 : z_s_5 z4_s_16 i2_index_11 01000100101xxxxx1110x1xxxxxxxxxx n 1112 SVE2 sqdmullt z_s_0 : z_msz_bhsd_5 z3_msz_bhsd_16 i3_index_11 -01000100xx001001101xxxxxxxxxxxxx n 411 SVE2 sqneg z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_5 +01000100xx001001101xxxxxxxxxxxxx n 411 SVE2 sqneg z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_5 01000100xx0xxxxx0011xxxxxxxxxxxx n 1169 SVE2 sqrdcmlah z_size_bhsd_0 : z_size_bhsd_0 z_size_bhsd_5 z_size_bhsd_16 imm2_nesw_10 01000100101xxxxx0111xxxxxxxxxxxx n 1169 SVE2 sqrdcmlah z_msz_bhsd_0 : z_msz_bhsd_0 z_msz_bhsd_5 z3_msz_bhsd_16 i2_index_19 imm2_nesw_10 01000100111xxxxx0111xxxxxxxxxxxx n 1169 SVE2 sqrdcmlah z_s_0 : z_s_0 z_s_5 z4_s_16 i1_index_20 imm2_nesw_10 @@ -201,30 +201,30 @@ 01000100111xxxxx111101xxxxxxxxxx n 413 SVE2 sqrdmulh z_d_0 : z_d_5 z4_d_16 i1_index_20 010001000x1xxxxx111101xxxxxxxxxx n 413 SVE2 sqrdmulh z_h_0 : z_h_5 z3_h_16 i3_index_19 01000100101xxxxx111101xxxxxxxxxx n 413 SVE2 sqrdmulh z_s_0 : z_s_5 z3_s_16 i2_index_19 -01000100xx001010100xxxxxxxxxxxxx n 414 SVE2 sqrshl z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -01000100xx001110100xxxxxxxxxxxxx n 1147 SVE2 sqrshlr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +01000100xx001010100xxxxxxxxxxxxx n 414 SVE2 sqrshl z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +01000100xx001110100xxxxxxxxxxxxx n 1147 SVE2 sqrshlr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 010001010x1xxxxx001010xxxxxxxxxx n 1170 SVE2 sqrshrnb z_tszl19_bhs_0 : z_tszl19p1_hsd_5 tszl19lo_imm3_16p1 010001010x1xxxxx001011xxxxxxxxxx n 1171 SVE2 sqrshrnt z_tszl19_bhs_0 : z_tszl19_bhs_0 z_tszl19p1_hsd_5 tszl19lo_imm3_16p1 010001010x1xxxxx000010xxxxxxxxxx n 1172 SVE2 sqrshrunb z_tszl19_bhs_0 : z_tszl19p1_hsd_5 tszl19lo_imm3_16p1 010001010x1xxxxx000011xxxxxxxxxx n 1173 SVE2 sqrshrunt z_tszl19_bhs_0 : z_tszl19_bhs_0 z_tszl19p1_hsd_5 tszl19lo_imm3_16p1 -01000100xx001000100xxxxxxxxxxxxx n 419 SVE2 sqshl z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -00000100xx000110100xxxxxxxxxxxxx n 419 SVE2 sqshl z_tszl8_bhsd_0 : p10_mrg_lo z_tszl8_bhsd_0 tszl8_imm3_5 -01000100xx001100100xxxxxxxxxxxxx n 1148 SVE2 sqshlr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -00000100xx001111100xxxxxxxxxxxxx n 420 SVE2 sqshlu z_tszl8_bhsd_0 : p10_mrg_lo z_tszl8_bhsd_0 tszl8_imm3_5 +01000100xx001000100xxxxxxxxxxxxx n 419 SVE2 sqshl z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +00000100xx000110100xxxxxxxxxxxxx n 419 SVE2 sqshl z_tszl8_bhsd_0 : p10_mrg_lo.gov z_tszl8_bhsd_0 tszl8_imm3_5 +01000100xx001100100xxxxxxxxxxxxx n 1148 SVE2 sqshlr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +00000100xx001111100xxxxxxxxxxxxx n 420 SVE2 sqshlu z_tszl8_bhsd_0 : p10_mrg_lo.gov z_tszl8_bhsd_0 tszl8_imm3_5 010001010x1xxxxx001000xxxxxxxxxx n 1174 SVE2 sqshrnb z_tszl19_bhs_0 : z_tszl19p1_hsd_5 tszl19lo_imm3_16p1 010001010x1xxxxx001001xxxxxxxxxx n 1175 SVE2 sqshrnt z_tszl19_bhs_0 : z_tszl19_bhs_0 z_tszl19p1_hsd_5 tszl19lo_imm3_16p1 010001010x1xxxxx000000xxxxxxxxxx n 1176 SVE2 sqshrunb z_tszl19_bhs_0 : z_tszl19p1_hsd_5 tszl19lo_imm3_16p1 010001010x1xxxxx000001xxxxxxxxxx n 1177 SVE2 sqshrunt z_tszl19_bhs_0 : z_tszl19_bhs_0 z_tszl19p1_hsd_5 tszl19lo_imm3_16p1 -01000100xx011110100xxxxxxxxxxxxx n 1149 SVE2 sqsubr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +01000100xx011110100xxxxxxxxxxxxx n 1149 SVE2 sqsubr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 010001010x1xx000010000xxxxxxxxxx n 1139 SVE2 sqxtnb z_wtszl19_bhsd_0 : z_wtszl19p1_bhsd_5 010001010x1xx000010001xxxxxxxxxx n 1140 SVE2 sqxtnt z_wtszl19_bhsd_0 : z_wtszl19_bhsd_0 z_wtszl19p1_bhsd_5 010001010x1xx000010100xxxxxxxxxx n 1141 SVE2 sqxtunb z_wtszl19_bhsd_0 : z_wtszl19p1_bhsd_5 010001010x1xx000010101xxxxxxxxxx n 1142 SVE2 sqxtunt z_wtszl19_bhsd_0 : z_wtszl19_bhsd_0 z_wtszl19p1_bhsd_5 -01000100xx010100100xxxxxxxxxxxxx n 430 SVE2 srhadd z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +01000100xx010100100xxxxxxxxxxxxx n 430 SVE2 srhadd z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 01000101xx0xxxxx111100xxxxxxxxxx n 431 SVE2 sri z_tszl19_bhsd_0 : z_tszl19_bhsd_0 z_tszl19_bhsd_5 tszl19_imm3_16p1 -01000100xx000010100xxxxxxxxxxxxx n 432 SVE2 srshl z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -01000100xx000110100xxxxxxxxxxxxx n 1150 SVE2 srshlr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -00000100xx001100100xxxxxxxxxxxxx n 433 SVE2 srshr z_tszl8_bhsd_0 : p10_mrg_lo z_tszl8_bhsd_0 tszl8_imm3_5p1 +01000100xx000010100xxxxxxxxxxxxx n 432 SVE2 srshl z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +01000100xx000110100xxxxxxxxxxxxx n 1150 SVE2 srshlr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +00000100xx001100100xxxxxxxxxxxxx n 433 SVE2 srshr z_tszl8_bhsd_0 : p10_mrg_lo.gov z_tszl8_bhsd_0 tszl8_imm3_5p1 01000101xx0xxxxx111010xxxxxxxxxx n 434 SVE2 srsra z_tszl19_bhsd_0 : z_tszl19_bhsd_0 z_tszl19_bhsd_5 tszl19_imm3_16p1 010001010x0xxxxx101000xxxxxxxxxx n 1178 SVE2 sshllb z_tszl19p1_hsd_0 : z_tszl19_bhs_5 tszl19lo_imm3_16 010001010x0xxxxx101001xxxxxxxxxx n 1179 SVE2 sshllt z_tszl19p1_hsd_0 : z_tszl19_bhs_5 tszl19lo_imm3_16 @@ -235,16 +235,16 @@ 01000101xx0xxxxx100011xxxxxxxxxx n 1116 SVE2 ssubltb z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16 01000101xx0xxxxx010100xxxxxxxxxx n 1117 SVE2 ssubwb z_size_hsd_0 : z_size_hsd_5 z_sizep1_bhs_16 01000101xx0xxxxx010101xxxxxxxxxx n 1118 SVE2 ssubwt z_size_hsd_0 : z_size_hsd_5 z_sizep1_bhs_16 -11100100000xxxxx001xxxxxxxxxxxxx n 952 SVE2 stnt1b svemem_vec_22sd_gpr16 : z_d_0 p10_lo -11100100010xxxxx001xxxxxxxxxxxxx n 952 SVE2 stnt1b svemem_vec_22sd_gpr16 : z_s_0 p10_lo -11100101100xxxxx001xxxxxxxxxxxxx n 1004 SVE2 stnt1d svemem_vec_30sd_gpr16 : z_d_0 p10_lo -11100100100xxxxx001xxxxxxxxxxxxx n 1005 SVE2 stnt1h svemem_vec_22sd_gpr16 : z_d_0 p10_lo -11100100110xxxxx001xxxxxxxxxxxxx n 1005 SVE2 stnt1h svemem_vec_22sd_gpr16 : z_s_0 p10_lo -11100101000xxxxx001xxxxxxxxxxxxx n 1006 SVE2 stnt1w svemem_vec_22sd_gpr16 : z_d_0 p10_lo -11100101010xxxxx001xxxxxxxxxxxxx n 1006 SVE2 stnt1w svemem_vec_22sd_gpr16 : z_s_0 p10_lo +11100100000xxxxx001xxxxxxxxxxxxx n 952 SVE2 stnt1b svemem_vec_22sd_gpr16 : z_d_0 p10_lo.gov +11100100010xxxxx001xxxxxxxxxxxxx n 952 SVE2 stnt1b svemem_vec_22sd_gpr16 : z_s_0 p10_lo.gov +11100101100xxxxx001xxxxxxxxxxxxx n 1004 SVE2 stnt1d svemem_vec_30sd_gpr16 : z_d_0 p10_lo.gov +11100100100xxxxx001xxxxxxxxxxxxx n 1005 SVE2 stnt1h svemem_vec_22sd_gpr16 : z_d_0 p10_lo.gov +11100100110xxxxx001xxxxxxxxxxxxx n 1005 SVE2 stnt1h svemem_vec_22sd_gpr16 : z_s_0 p10_lo.gov +11100101000xxxxx001xxxxxxxxxxxxx n 1006 SVE2 stnt1w svemem_vec_22sd_gpr16 : z_d_0 p10_lo.gov +11100101010xxxxx001xxxxxxxxxxxxx n 1006 SVE2 stnt1w svemem_vec_22sd_gpr16 : z_s_0 p10_lo.gov 01000101xx1xxxxx011100xxxxxxxxxx n 1119 SVE2 subhnb z_sizep1_bhs_0 : z_size_hsd_5 z_size_hsd_16 01000101xx1xxxxx011101xxxxxxxxxx n 1120 SVE2 subhnt z_sizep1_bhs_0 : z_sizep1_bhs_0 z_size_hsd_5 z_size_hsd_16 -01000100xx011100100xxxxxxxxxxxxx n 474 SVE2 suqadd z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +01000100xx011100100xxxxxxxxxxxxx n 474 SVE2 suqadd z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 00000101xx1xxxxx001010xxxxxxxxxx n 490 SVE2 tbl z_size_bhsd_0 : z_size_bhsd_5 z_size_bhsd_5p1 z_size_bhsd_16 00000101xx1xxxxx001011xxxxxxxxxx n 492 SVE2 tbx z_size_bhsd_0 : z_size_bhsd_0 z_size_bhsd_5 z_size_bhsd_16 01000101xx0xxxxx111111xxxxxxxxxx n 496 SVE2 uaba z_size_bhsd_0 : z_size_bhsd_0 z_size_bhsd_5 z_size_bhsd_16 @@ -252,16 +252,16 @@ 01000101xx0xxxxx110011xxxxxxxxxx n 1122 SVE2 uabalt z_size_hsd_0 : z_size_hsd_0 z_sizep1_bhs_5 z_sizep1_bhs_16 01000101xx0xxxxx001110xxxxxxxxxx n 1123 SVE2 uabdlb z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16 01000101xx0xxxxx001111xxxxxxxxxx n 1124 SVE2 uabdlt z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16 -01000100xx000101101xxxxxxxxxxxxx n 502 SVE2 uadalp z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo z_sizep1_bhs_5 +01000100xx000101101xxxxxxxxxxxxx n 502 SVE2 uadalp z_size_hsd_0 : z_size_hsd_0 p10_mrg_lo.gov z_sizep1_bhs_5 01000101xx0xxxxx000010xxxxxxxxxx n 1125 SVE2 uaddlb z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16 01000101xx0xxxxx000011xxxxxxxxxx n 1126 SVE2 uaddlt z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16 01000101xx0xxxxx010010xxxxxxxxxx n 1127 SVE2 uaddwb z_size_hsd_0 : z_size_hsd_5 z_sizep1_bhs_16 01000101xx0xxxxx010011xxxxxxxxxx n 1128 SVE2 uaddwt z_size_hsd_0 : z_size_hsd_5 z_sizep1_bhs_16 -01000100xx010001100xxxxxxxxxxxxx n 513 SVE2 uhadd z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -01000100xx010011100xxxxxxxxxxxxx n 514 SVE2 uhsub z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -01000100xx010111100xxxxxxxxxxxxx n 1151 SVE2 uhsubr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -01000100xx010101101xxxxxxxxxxxxx n 517 SVE2 umaxp z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -01000100xx010111101xxxxxxxxxxxxx n 520 SVE2 uminp z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +01000100xx010001100xxxxxxxxxxxxx n 513 SVE2 uhadd z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +01000100xx010011100xxxxxxxxxxxxx n 514 SVE2 uhsub z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +01000100xx010111100xxxxxxxxxxxxx n 1151 SVE2 uhsubr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +01000100xx010101101xxxxxxxxxxxxx n 517 SVE2 umaxp z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +01000100xx010111101xxxxxxxxxxxxx n 520 SVE2 uminp z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 01000100xx0xxxxx010010xxxxxxxxxx n 1129 SVE2 umlalb z_size_hsd_0 : z_size_hsd_0 z_sizep1_bhs_5 z_sizep1_bhs_16 01000100111xxxxx1001x0xxxxxxxxxx n 1129 SVE2 umlalb z_d_0 : z_d_0 z_s_5 z4_s_16 i2_index_11 01000100101xxxxx1001x0xxxxxxxxxx n 1129 SVE2 umlalb z_s_0 : z_s_0 z_msz_bhsd_5 z3_msz_bhsd_16 i3_index_11 @@ -280,28 +280,28 @@ 01000101xx0xxxxx011111xxxxxxxxxx n 1134 SVE2 umullt z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16 01000100111xxxxx1101x1xxxxxxxxxx n 1134 SVE2 umullt z_d_0 : z_s_5 z4_s_16 i2_index_11 01000100101xxxxx1101x1xxxxxxxxxx n 1134 SVE2 umullt z_s_0 : z_msz_bhsd_5 z3_msz_bhsd_16 i3_index_11 -01000100xx001011100xxxxxxxxxxxxx n 532 SVE2 uqrshl z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -01000100xx001111100xxxxxxxxxxxxx n 1152 SVE2 uqrshlr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +01000100xx001011100xxxxxxxxxxxxx n 532 SVE2 uqrshl z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +01000100xx001111100xxxxxxxxxxxxx n 1152 SVE2 uqrshlr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 010001010x1xxxxx001110xxxxxxxxxx n 1180 SVE2 uqrshrnb z_tszl19_bhs_0 : z_tszl19p1_hsd_5 tszl19lo_imm3_16p1 010001010x1xxxxx001111xxxxxxxxxx n 1181 SVE2 uqrshrnt z_tszl19_bhs_0 : z_tszl19_bhs_0 z_tszl19p1_hsd_5 tszl19lo_imm3_16p1 -01000100xx001001100xxxxxxxxxxxxx n 535 SVE2 uqshl z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -00000100xx000111100xxxxxxxxxxxxx n 535 SVE2 uqshl z_tszl8_bhsd_0 : p10_mrg_lo z_tszl8_bhsd_0 tszl8_imm3_5 -01000100xx001101100xxxxxxxxxxxxx n 1153 SVE2 uqshlr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +01000100xx001001100xxxxxxxxxxxxx n 535 SVE2 uqshl z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +00000100xx000111100xxxxxxxxxxxxx n 535 SVE2 uqshl z_tszl8_bhsd_0 : p10_mrg_lo.gov z_tszl8_bhsd_0 tszl8_imm3_5 +01000100xx001101100xxxxxxxxxxxxx n 1153 SVE2 uqshlr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 010001010x1xxxxx001100xxxxxxxxxx n 1182 SVE2 uqshrnb z_tszl19_bhs_0 : z_tszl19p1_hsd_5 tszl19lo_imm3_16p1 010001010x1xxxxx001101xxxxxxxxxx n 1183 SVE2 uqshrnt z_tszl19_bhs_0 : z_tszl19_bhs_0 z_tszl19p1_hsd_5 tszl19lo_imm3_16p1 -01000100xx011111100xxxxxxxxxxxxx n 1154 SVE2 uqsubr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +01000100xx011111100xxxxxxxxxxxxx n 1154 SVE2 uqsubr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 010001010x1xx000010010xxxxxxxxxx n 1143 SVE2 uqxtnb z_wtszl19_bhsd_0 : z_wtszl19p1_bhsd_5 010001010x1xx000010011xxxxxxxxxx n 1144 SVE2 uqxtnt z_wtszl19_bhsd_0 : z_wtszl19_bhsd_0 z_wtszl19p1_bhsd_5 -0100010010000000101xxxxxxxxxxxxx n 541 SVE2 urecpe z_s_0 : p10_mrg_lo z_s_5 -01000100xx010101100xxxxxxxxxxxxx n 542 SVE2 urhadd z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -01000100xx000011100xxxxxxxxxxxxx n 543 SVE2 urshl z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -01000100xx000111100xxxxxxxxxxxxx n 1155 SVE2 urshlr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 -00000100xx001101100xxxxxxxxxxxxx n 544 SVE2 urshr z_tszl8_bhsd_0 : p10_mrg_lo z_tszl8_bhsd_0 tszl8_imm3_5p1 -0100010010000001101xxxxxxxxxxxxx n 545 SVE2 ursqrte z_s_0 : p10_mrg_lo z_s_5 +0100010010000000101xxxxxxxxxxxxx n 541 SVE2 urecpe z_s_0 : p10_mrg_lo.gov z_s_5 +01000100xx010101100xxxxxxxxxxxxx n 542 SVE2 urhadd z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +01000100xx000011100xxxxxxxxxxxxx n 543 SVE2 urshl z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +01000100xx000111100xxxxxxxxxxxxx n 1155 SVE2 urshlr z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 +00000100xx001101100xxxxxxxxxxxxx n 544 SVE2 urshr z_tszl8_bhsd_0 : p10_mrg_lo.gov z_tszl8_bhsd_0 tszl8_imm3_5p1 +0100010010000001101xxxxxxxxxxxxx n 545 SVE2 ursqrte z_s_0 : p10_mrg_lo.gov z_s_5 01000101xx0xxxxx111011xxxxxxxxxx n 546 SVE2 ursra z_tszl19_bhsd_0 : z_tszl19_bhsd_0 z_tszl19_bhsd_5 tszl19_imm3_16p1 010001010x0xxxxx101010xxxxxxxxxx n 1184 SVE2 ushllb z_tszl19p1_hsd_0 : z_tszl19_bhs_5 tszl19lo_imm3_16 010001010x0xxxxx101011xxxxxxxxxx n 1185 SVE2 ushllt z_tszl19p1_hsd_0 : z_tszl19_bhs_5 tszl19lo_imm3_16 -01000100xx011101100xxxxxxxxxxxxx n 551 SVE2 usqadd z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5 +01000100xx011101100xxxxxxxxxxxxx n 551 SVE2 usqadd z_size_bhsd_0 : p10_mrg_lo.gov z_size_bhsd_0 z_size_bhsd_5 01000101xx0xxxxx111001xxxxxxxxxx n 552 SVE2 usra z_tszl19_bhsd_0 : z_tszl19_bhsd_0 z_tszl19_bhsd_5 tszl19_imm3_16p1 01000101xx0xxxxx000110xxxxxxxxxx n 1135 SVE2 usublb z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16 01000101xx0xxxxx000111xxxxxxxxxx n 1136 SVE2 usublt z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16 diff --git a/core/ir/aarch64/codec_v80.txt b/core/ir/aarch64/codec_v80.txt index 76429ea1940..9486e38295d 100644 --- a/core/ir/aarch64/codec_v80.txt +++ b/core/ir/aarch64/codec_v80.txt @@ -68,6 +68,14 @@ # If several operands handle the same 'x' bit then the automatically generated # encoder will check that consistent bit patterns are generated. +# Opndtype instances may be annotated by adding various flags after a '.'. The +# codec may then use these flags to generate extra code for that operand +# or for the instruction it is a part of. This is to allow certain properties +# to be set on the instr without having to use a custom encode/decode function +# as well as well as reducing the need for special operand encoders/decoders if +# only a flag needs to be set or similar. Multiple flags can be supported like +# p10.gov.scatter + # The enum field is managed by the codec sorter, and should be unique per # opcode. If you're adding a new entry just leave it out and run # codecsort.py --rewrite and it will assign the proper enum value. diff --git a/core/ir/aarch64/disassemble.c b/core/ir/aarch64/disassemble.c index e433968ae3a..6c5cbb5ae2c 100644 --- a/core/ir/aarch64/disassemble.c +++ b/core/ir/aarch64/disassemble.c @@ -55,6 +55,7 @@ static const char *const pred_names[] = { "le", /* DR_PRED_LE */ "al", /* DR_PRED_AL */ "nv", /* DR_PRED_NV */ + "", /* DR_PRED_GOVERNING */ }; int @@ -149,7 +150,8 @@ void print_opcode_name(instr_t *instr, const char *name, char *buf, size_t bufsz, size_t *sofar DR_PARAM_OUT) { - if (instr_get_predicate(instr) != DR_PRED_NONE) { + if (instr_get_predicate(instr) != DR_PRED_NONE && + instr_get_predicate(instr) != DR_PRED_GOVERNING) { if (instr_get_opcode(instr) == OP_bcond) { print_to_buffer(buf, bufsz, sofar, "b.%s", pred_names[instr_get_predicate(instr)]); diff --git a/core/ir/aarch64/instr_create_api.h b/core/ir/aarch64/instr_create_api.h index 516803b32f5..1c4d57a1914 100644 --- a/core/ir/aarch64/instr_create_api.h +++ b/core/ir/aarch64/instr_create_api.h @@ -5271,7 +5271,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_orr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_orr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_orr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an EOR instruction. @@ -5286,7 +5286,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_eor_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_eor, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_eor, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an AND instruction. @@ -5301,7 +5301,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_and_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_and, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_and, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a BIC instruction. @@ -5316,7 +5316,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_bic_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_bic, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_bic, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a MOVPRFX instruction. @@ -5345,7 +5345,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_movprfx_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_movprfx, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_movprfx, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a SQADD instruction. @@ -5420,7 +5420,7 @@ * \param Zm The third source vector register, Z (Scalable) */ #define INSTR_CREATE_sub_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_sub, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sub, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SUB instruction. @@ -5465,7 +5465,7 @@ * \param Zm The third source vector register, Z (Scalable) */ #define INSTR_CREATE_subr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_subr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_subr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SUBR instruction. @@ -5555,7 +5555,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_add_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_add, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_add, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a ADD instruction. @@ -5601,8 +5601,10 @@ * \param simm The signed immediate imm * \param shift The immediate shiftOp for simm */ -#define INSTR_CREATE_cpy_sve_shift_pred(dc, Zd, Pg, simm, shift) \ - instr_create_1dst_4src(dc, OP_cpy, Zd, Pg, simm, OPND_CREATE_LSL(), shift) +#define INSTR_CREATE_cpy_sve_shift_pred(dc, Zd, Pg, simm, shift) \ + INSTR_PRED( \ + instr_create_1dst_4src(dc, OP_cpy, Zd, Pg, simm, OPND_CREATE_LSL(), shift), \ + DR_PRED_GOVERNING) /** * Creates a CPY instruction. @@ -5621,7 +5623,7 @@ * S (Singleword, 32 bits), or D (Doubleword, 64 bits). */ #define INSTR_CREATE_cpy_sve_pred(dc, Zd, Pg, Rn_or_Vn) \ - instr_create_1dst_2src(dc, OP_cpy, Zd, Pg, Rn_or_Vn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_cpy, Zd, Pg, Rn_or_Vn), DR_PRED_GOVERNING) /** * Creates a PTEST instruction. @@ -5635,7 +5637,7 @@ * \param Pn The first source predicate register, P (Predicate) */ #define INSTR_CREATE_ptest_sve_pred(dc, Pg, Pn) \ - instr_create_0dst_2src(dc, OP_ptest, Pg, Pn) + INSTR_PRED(instr_create_0dst_2src(dc, OP_ptest, Pg, Pn), DR_PRED_GOVERNING) /** * Creates a MAD instruction. @@ -5650,8 +5652,9 @@ * \param Zm The second source vector register, Z (Scalable). * \param Za The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_mad_sve_pred(dc, Zdn, Pg, Zm, Za) \ - instr_create_1dst_4src(dc, OP_mad, Zdn, Zdn, Pg, Zm, Za) +#define INSTR_CREATE_mad_sve_pred(dc, Zdn, Pg, Zm, Za) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_mad, Zdn, Zdn, Pg, Zm, Za), \ + DR_PRED_GOVERNING) /** * Creates a MLA instruction. @@ -5666,8 +5669,9 @@ * \param Zn The second source vector register, Z (Scalable). * \param Zm The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_mla_sve_pred(dc, Zda, Pg, Zn, Zm) \ - instr_create_1dst_4src(dc, OP_mla, Zda, Zda, Pg, Zn, Zm) +#define INSTR_CREATE_mla_sve_pred(dc, Zda, Pg, Zn, Zm) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_mla, Zda, Zda, Pg, Zn, Zm), \ + DR_PRED_GOVERNING) /** * Creates a MLS instruction. @@ -5682,8 +5686,9 @@ * \param Zn The second source vector register, Z (Scalable). * \param Zm The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_mls_sve_pred(dc, Zda, Pg, Zn, Zm) \ - instr_create_1dst_4src(dc, OP_mls, Zda, Zda, Pg, Zn, Zm) +#define INSTR_CREATE_mls_sve_pred(dc, Zda, Pg, Zn, Zm) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_mls, Zda, Zda, Pg, Zn, Zm), \ + DR_PRED_GOVERNING) /** * Creates a MSB instruction. @@ -5698,8 +5703,9 @@ * \param Zm The second source vector register, Z (Scalable). * \param Za The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_msb_sve_pred(dc, Zdn, Pg, Zm, Za) \ - instr_create_1dst_4src(dc, OP_msb, Zdn, Zdn, Pg, Zm, Za) +#define INSTR_CREATE_msb_sve_pred(dc, Zdn, Pg, Zm, Za) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_msb, Zdn, Zdn, Pg, Zm, Za), \ + DR_PRED_GOVERNING) /** * Creates a MUL instruction. @@ -5714,7 +5720,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_mul_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_mul, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_mul, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a MUL instruction. @@ -5743,7 +5749,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_smulh_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_smulh, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_smulh, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an UMULH instruction. @@ -5758,7 +5764,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_umulh_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_umulh, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_umulh, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FEXPA instruction. @@ -5831,7 +5837,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_abs_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_abs, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_abs, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a CNOT instruction. @@ -5846,7 +5852,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_cnot_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_cnot, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_cnot, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a NEG instruction. @@ -5861,7 +5867,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_neg_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_neg, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_neg, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a SABD instruction. @@ -5876,7 +5882,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_sabd_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_sabd, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sabd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SMAX instruction. @@ -5891,7 +5897,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_smax_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_smax, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_smax, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SMAX instruction. @@ -5920,7 +5926,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_smin_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_smin, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_smin, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SMIN instruction. @@ -5949,7 +5955,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_uabd_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_uabd, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uabd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FACGE instruction. @@ -5965,7 +5971,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_facge_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_facge, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_facge, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a FACGT instruction. @@ -5981,7 +5987,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_facgt_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_facgt, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_facgt, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a SDIV instruction. @@ -5996,7 +6002,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_sdiv_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_sdiv, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sdiv, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SDIVR instruction. @@ -6011,7 +6017,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_sdivr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_sdivr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sdivr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an UDIV instruction. @@ -6026,7 +6032,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_udiv_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_udiv, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_udiv, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an UDIVR instruction. @@ -6041,7 +6047,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_udivr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_udivr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_udivr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an UMAX instruction. @@ -6056,7 +6062,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_umax_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_umax, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_umax, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an UMAX instruction. @@ -6085,7 +6091,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_umin_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_umin, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_umin, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an UMIN instruction. @@ -6114,7 +6120,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_sxtb_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_sxtb, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_sxtb, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a SXTH instruction. @@ -6129,7 +6135,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_sxth_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_sxth, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_sxth, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a SXTW instruction. @@ -6144,7 +6150,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_sxtw_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_sxtw, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_sxtw, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates an UXTB instruction. @@ -6159,7 +6165,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_uxtb_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_uxtb, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_uxtb, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates an UXTH instruction. @@ -6174,7 +6180,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_uxth_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_uxth, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_uxth, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates an UXTW instruction. @@ -6189,7 +6195,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_uxtw_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_uxtw, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_uxtw, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FCMEQ instruction. @@ -6203,8 +6209,10 @@ * \param Pg The governing predicate register, P (Predicate) * \param Zn The first source vector register, Z (Scalable) */ -#define INSTR_CREATE_fcmeq_sve_zero_pred(dc, Pd, Pg, Zn) \ - instr_create_1dst_3src(dc, OP_fcmeq, Pd, Pg, Zn, opnd_create_immed_float(0.0)) +#define INSTR_CREATE_fcmeq_sve_zero_pred(dc, Pd, Pg, Zn) \ + INSTR_PRED( \ + instr_create_1dst_3src(dc, OP_fcmeq, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \ + DR_PRED_GOVERNING) /** * Creates a FCMEQ instruction. @@ -6220,7 +6228,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_fcmeq_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_fcmeq, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmeq, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a FCMGE instruction. @@ -6234,8 +6242,10 @@ * \param Pg The governing predicate register, P (Predicate) * \param Zn The first source vector register, Z (Scalable) */ -#define INSTR_CREATE_fcmge_sve_zero_pred(dc, Pd, Pg, Zn) \ - instr_create_1dst_3src(dc, OP_fcmge, Pd, Pg, Zn, opnd_create_immed_float(0.0)) +#define INSTR_CREATE_fcmge_sve_zero_pred(dc, Pd, Pg, Zn) \ + INSTR_PRED( \ + instr_create_1dst_3src(dc, OP_fcmge, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \ + DR_PRED_GOVERNING) /** * Creates a FCMGE instruction. @@ -6251,7 +6261,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_fcmge_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_fcmge, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmge, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a FCMGT instruction. @@ -6265,8 +6275,10 @@ * \param Pg The governing predicate register, P (Predicate) * \param Zn The first source vector register, Z (Scalable) */ -#define INSTR_CREATE_fcmgt_sve_zero_pred(dc, Pd, Pg, Zn) \ - instr_create_1dst_3src(dc, OP_fcmgt, Pd, Pg, Zn, opnd_create_immed_float(0.0)) +#define INSTR_CREATE_fcmgt_sve_zero_pred(dc, Pd, Pg, Zn) \ + INSTR_PRED( \ + instr_create_1dst_3src(dc, OP_fcmgt, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \ + DR_PRED_GOVERNING) /** * Creates a FCMGT instruction. @@ -6282,7 +6294,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_fcmgt_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_fcmgt, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmgt, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a FCMLE instruction. @@ -6296,8 +6308,10 @@ * \param Pg The governing predicate register, P (Predicate) * \param Zn The first source vector register, Z (Scalable) */ -#define INSTR_CREATE_fcmle_sve_zero_pred(dc, Pd, Pg, Zn) \ - instr_create_1dst_3src(dc, OP_fcmle, Pd, Pg, Zn, opnd_create_immed_float(0.0)) +#define INSTR_CREATE_fcmle_sve_zero_pred(dc, Pd, Pg, Zn) \ + INSTR_PRED( \ + instr_create_1dst_3src(dc, OP_fcmle, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \ + DR_PRED_GOVERNING) /** * Creates a FCMLT instruction. @@ -6311,8 +6325,10 @@ * \param Pg The governing predicate register, P (Predicate) * \param Zn The first source vector register, Z (Scalable) */ -#define INSTR_CREATE_fcmlt_sve_zero_pred(dc, Pd, Pg, Zn) \ - instr_create_1dst_3src(dc, OP_fcmlt, Pd, Pg, Zn, opnd_create_immed_float(0.0)) +#define INSTR_CREATE_fcmlt_sve_zero_pred(dc, Pd, Pg, Zn) \ + INSTR_PRED( \ + instr_create_1dst_3src(dc, OP_fcmlt, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \ + DR_PRED_GOVERNING) /** * Creates a FCMNE instruction. @@ -6326,8 +6342,10 @@ * \param Pg The governing predicate register, P (Predicate) * \param Zn The first source vector register, Z (Scalable) */ -#define INSTR_CREATE_fcmne_sve_zero_pred(dc, Pd, Pg, Zn) \ - instr_create_1dst_3src(dc, OP_fcmne, Pd, Pg, Zn, opnd_create_immed_float(0.0)) +#define INSTR_CREATE_fcmne_sve_zero_pred(dc, Pd, Pg, Zn) \ + INSTR_PRED( \ + instr_create_1dst_3src(dc, OP_fcmne, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \ + DR_PRED_GOVERNING) /** * Creates a FCMNE instruction. @@ -6343,7 +6361,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_fcmne_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_fcmne, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmne, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a FCMUO instruction. @@ -6359,7 +6377,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_fcmuo_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_fcmuo, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmuo, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a FCMLE instruction. @@ -6375,7 +6393,7 @@ * \param Zn The second source vector register, Z (Scalable) */ #define INSTR_CREATE_fcmle_sve_pred(dc, Pd, Pg, Zm, Zn) \ - instr_create_1dst_3src(dc, OP_fcmle, Pd, Pg, Zm, Zn) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmle, Pd, Pg, Zm, Zn), DR_PRED_GOVERNING) /** * Creates a FCMLT instruction. @@ -6391,7 +6409,7 @@ * \param Zn The second source vector register, Z (Scalable) */ #define INSTR_CREATE_fcmlt_sve_pred(dc, Pd, Pg, Zm, Zn) \ - instr_create_1dst_3src(dc, OP_fcmlt, Pd, Pg, Zm, Zn) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmlt, Pd, Pg, Zm, Zn), DR_PRED_GOVERNING) /** * Creates a CMPEQ instruction. @@ -6407,7 +6425,7 @@ * \param simm The signed immediate imm */ #define INSTR_CREATE_cmpeq_sve_pred_simm(dc, Pd, Pg, Zn, simm) \ - instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, simm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, simm), DR_PRED_GOVERNING) /** * Creates a CMPEQ instruction. @@ -6424,7 +6442,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmpeq_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a CMPGE instruction. @@ -6440,7 +6458,7 @@ * \param simm The signed immediate imm */ #define INSTR_CREATE_cmpge_sve_pred_simm(dc, Pd, Pg, Zn, simm) \ - instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, simm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, simm), DR_PRED_GOVERNING) /** * Creates a CMPGE instruction. @@ -6457,7 +6475,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmpge_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a CMPGT instruction. @@ -6473,7 +6491,7 @@ * \param simm The signed immediate imm */ #define INSTR_CREATE_cmpgt_sve_pred_simm(dc, Pd, Pg, Zn, simm) \ - instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, simm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, simm), DR_PRED_GOVERNING) /** * Creates a CMPGT instruction. @@ -6490,7 +6508,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmpgt_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a CMPHI instruction. @@ -6506,7 +6524,7 @@ * \param imm The immediate imm */ #define INSTR_CREATE_cmphi_sve_pred_imm(dc, Pd, Pg, Zn, imm) \ - instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, imm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, imm), DR_PRED_GOVERNING) /** * Creates a CMPHI instruction. @@ -6523,7 +6541,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmphi_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a CMPHS instruction. @@ -6539,7 +6557,7 @@ * \param imm The immediate imm */ #define INSTR_CREATE_cmphs_sve_pred_imm(dc, Pd, Pg, Zn, imm) \ - instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, imm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, imm), DR_PRED_GOVERNING) /** * Creates a CMPHS instruction. @@ -6556,7 +6574,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmphs_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a CMPLE instruction. @@ -6572,7 +6590,7 @@ * \param simm The signed immediate imm */ #define INSTR_CREATE_cmple_sve_pred_simm(dc, Pd, Pg, Zn, simm) \ - instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, simm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, simm), DR_PRED_GOVERNING) /** * Creates a CMPLE instruction. @@ -6588,7 +6606,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmple_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a CMPLO instruction. @@ -6604,7 +6622,7 @@ * \param imm The immediate imm */ #define INSTR_CREATE_cmplo_sve_pred_imm(dc, Pd, Pg, Zn, imm) \ - instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, imm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, imm), DR_PRED_GOVERNING) /** * Creates a CMPLO instruction. @@ -6620,7 +6638,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmplo_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a CMPLS instruction. @@ -6636,7 +6654,7 @@ * \param imm The immediate imm */ #define INSTR_CREATE_cmpls_sve_pred_imm(dc, Pd, Pg, Zn, imm) \ - instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, imm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, imm), DR_PRED_GOVERNING) /** * Creates a CMPLS instruction. @@ -6652,7 +6670,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmpls_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a CMPLT instruction. @@ -6668,7 +6686,7 @@ * \param simm The signed immediate imm */ #define INSTR_CREATE_cmplt_sve_pred_simm(dc, Pd, Pg, Zn, simm) \ - instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, simm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, simm), DR_PRED_GOVERNING) /** * Creates a CMPLT instruction. @@ -6684,7 +6702,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmplt_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a CMPNE instruction. @@ -6700,7 +6718,7 @@ * \param simm The signed immediate imm */ #define INSTR_CREATE_cmpne_sve_pred_simm(dc, Pd, Pg, Zn, simm) \ - instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, simm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, simm), DR_PRED_GOVERNING) /** * Creates a CMPNE instruction. @@ -6717,7 +6735,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmpne_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a SETFFR instruction. @@ -6754,7 +6772,7 @@ * \param Pg The governing predicate register, P (Predicate) */ #define INSTR_CREATE_rdffr_sve_pred(dc, Pd, Pg) \ - instr_create_1dst_1src(dc, OP_rdffr, Pd, Pg) + INSTR_PRED(instr_create_1dst_1src(dc, OP_rdffr, Pd, Pg), DR_PRED_GOVERNING) /** * Creates a RDFFRS instruction. @@ -6768,7 +6786,7 @@ * \param Pg The governing predicate register, P (Predicate) */ #define INSTR_CREATE_rdffrs_sve_pred(dc, Pd, Pg) \ - instr_create_1dst_1src(dc, OP_rdffrs, Pd, Pg) + INSTR_PRED(instr_create_1dst_1src(dc, OP_rdffrs, Pd, Pg), DR_PRED_GOVERNING) /** * Creates a WRFFR instruction. @@ -6795,7 +6813,7 @@ * \param Pn The source predicate register, P (Predicate). */ #define INSTR_CREATE_cntp_sve_pred(dc, Rd, Pg, Pn) \ - instr_create_1dst_2src(dc, OP_cntp, Rd, Pg, Pn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_cntp, Rd, Pg, Pn), DR_PRED_GOVERNING) /** * Creates a DECP instruction. @@ -7093,7 +7111,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_and_sve_pred_b(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_and, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_and, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates an AND instruction. @@ -7124,7 +7142,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_ands_sve_pred(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates a BIC instruction. @@ -7140,7 +7158,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_bic_sve_pred_b(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_bic, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_bic, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates a BIC instruction. @@ -7171,7 +7189,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_bics_sve_pred(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_bics, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_bics, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates an EOR instruction. @@ -7187,7 +7205,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_eor_sve_pred_b(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_eor, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_eor, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates a NOT instruction. @@ -7234,7 +7252,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_eors_sve_pred(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_eors, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_eors, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates a NAND instruction. @@ -7250,7 +7268,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_nand_sve_pred(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_nand, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_nand, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates a NANDS instruction. @@ -7266,7 +7284,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_nands_sve_pred(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_nands, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_nands, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates a NOR instruction. @@ -7282,7 +7300,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_nor_sve_pred(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_nor, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_nor, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates a NORS instruction. @@ -7298,7 +7316,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_nors_sve_pred(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_nors, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_nors, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates a NOT instruction. @@ -7313,7 +7331,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_not_sve_pred_vec(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_not, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_not, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates an ORN instruction. @@ -7329,7 +7347,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_orn_sve_pred(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_orn, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_orn, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates an ORNS instruction. @@ -7345,7 +7363,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_orns_sve_pred(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_orns, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_orns, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates an ORR instruction. @@ -7361,7 +7379,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_orr_sve_pred_b(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_orr, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_orr, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates an ORR instruction. @@ -7392,7 +7410,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_orrs_sve_pred(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_orrs, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_orrs, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates a CLASTA instruction. @@ -7408,7 +7426,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_clasta_sve_scalar(dc, Rdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_clasta, Rdn, Pg, Rdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Rdn, Pg, Rdn, Zm), DR_PRED_GOVERNING) /** * Creates a CLASTA instruction. @@ -7424,7 +7442,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_clasta_sve_simd_fp(dc, Vdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_clasta, Vdn, Pg, Vdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Vdn, Pg, Vdn, Zm), DR_PRED_GOVERNING) /** * Creates a CLASTA instruction. @@ -7439,7 +7457,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_clasta_sve_vector(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_clasta, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a CLASTB instruction. @@ -7455,7 +7473,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_clastb_sve_scalar(dc, Rdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_clastb, Rdn, Pg, Rdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Rdn, Pg, Rdn, Zm), DR_PRED_GOVERNING) /** * Creates a CLASTB instruction. @@ -7471,7 +7489,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_clastb_sve_simd_fp(dc, Vdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_clastb, Vdn, Pg, Vdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Vdn, Pg, Vdn, Zm), DR_PRED_GOVERNING) /** * Creates a CLASTB instruction. @@ -7486,7 +7504,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_clastb_sve_vector(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_clastb, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a LASTA instruction. @@ -7502,7 +7520,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_lasta_sve_scalar(dc, Rd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_lasta, Rd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_lasta, Rd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a LASTA instruction. @@ -7518,7 +7536,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_lasta_sve_simd_fp(dc, Vd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_lasta, Vd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_lasta, Vd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a LASTB instruction. @@ -7534,7 +7552,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_lastb_sve_scalar(dc, Rd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_lastb, Rd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_lastb, Rd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a LASTB instruction. @@ -7550,7 +7568,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_lastb_sve_simd_fp(dc, Vd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_lastb, Vd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_lastb, Vd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a CNT instruction. @@ -7565,7 +7583,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_cnt_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a CNTB instruction. @@ -8450,7 +8468,7 @@ * \param Pn The source predicate register, P (Predicate). */ #define INSTR_CREATE_brka_sve_pred(dc, Pd, Pg, Pn) \ - instr_create_1dst_2src(dc, OP_brka, Pd, Pg, Pn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_brka, Pd, Pg, Pn), DR_PRED_GOVERNING) /** * Creates a BRKAS instruction. @@ -8465,7 +8483,7 @@ * \param Pn The source predicate register, P (Predicate). */ #define INSTR_CREATE_brkas_sve_pred(dc, Pd, Pg, Pn) \ - instr_create_1dst_2src(dc, OP_brkas, Pd, Pg, Pn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_brkas, Pd, Pg, Pn), DR_PRED_GOVERNING) /** * Creates a BRKB instruction. @@ -8480,7 +8498,7 @@ * \param Pn The source predicate register, P (Predicate). */ #define INSTR_CREATE_brkb_sve_pred(dc, Pd, Pg, Pn) \ - instr_create_1dst_2src(dc, OP_brkb, Pd, Pg, Pn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_brkb, Pd, Pg, Pn), DR_PRED_GOVERNING) /** * Creates a BRKBS instruction. @@ -8495,7 +8513,7 @@ * \param Pn The source predicate register, P (Predicate). */ #define INSTR_CREATE_brkbs_sve_pred(dc, Pd, Pg, Pn) \ - instr_create_1dst_2src(dc, OP_brkbs, Pd, Pg, Pn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_brkbs, Pd, Pg, Pn), DR_PRED_GOVERNING) /** * Creates a BRKN instruction. @@ -8511,7 +8529,7 @@ * \param Pn The first source predicate register, P (Predicate). */ #define INSTR_CREATE_brkn_sve_pred(dc, Pdm, Pg, Pn) \ - instr_create_1dst_3src(dc, OP_brkn, Pdm, Pg, Pn, Pdm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_brkn, Pdm, Pg, Pn, Pdm), DR_PRED_GOVERNING) /** * Creates a BRKNS instruction. @@ -8527,7 +8545,7 @@ * \param Pn The first source predicate register, P (Predicate). */ #define INSTR_CREATE_brkns_sve_pred(dc, Pdm, Pg, Pn) \ - instr_create_1dst_3src(dc, OP_brkns, Pdm, Pg, Pn, Pdm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_brkns, Pdm, Pg, Pn, Pdm), DR_PRED_GOVERNING) /** * Creates a BRKPA instruction. @@ -8543,7 +8561,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_brkpa_sve_pred(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_brkpa, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpa, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates a BRKPAS instruction. @@ -8559,7 +8577,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_brkpas_sve_pred(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_brkpas, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpas, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates a BRKPB instruction. @@ -8575,7 +8593,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_brkpb_sve_pred(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_brkpb, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpb, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates a BRKPBS instruction. @@ -8591,7 +8609,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_brkpbs_sve_pred(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_brkpbs, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpbs, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates a WHILELE instruction. @@ -8796,11 +8814,11 @@ * \endverbatim * \param dc The void * dcontext used to allocate memory for the #instr_t. * \param Zdn The second source and destination vector register, Z (Scalable). - * \param Pv The first source predicate register, P (Predicate). - * \param Zm The third source vector register, Z (Scalable). + * \param Pv The governing predicate register, P (Predicate). + * \param Zm The last source vector register, Z (Scalable). */ #define INSTR_CREATE_splice_sve_des(dc, Zdn, Pv, Zm) \ - instr_create_1dst_3src(dc, OP_splice, Zdn, Pv, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_splice, Zdn, Pv, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SPLICE instruction. @@ -8816,8 +8834,10 @@ * * The Zn2 parameter is derived from Zn. */ -#define INSTR_CREATE_splice_sve_con(dc, Zd, Pv, Zn) \ - instr_create_1dst_3src(dc, OP_splice, Zd, Pv, Zn, opnd_create_increment_reg(Zn, 1)) +#define INSTR_CREATE_splice_sve_con(dc, Zd, Pv, Zn) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_splice, Zd, Pv, Zn, \ + opnd_create_increment_reg(Zn, 1)), \ + DR_PRED_GOVERNING) /** * Creates a REV instruction. @@ -8858,7 +8878,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_revb_sve(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_revb, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_revb, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a REVH instruction. @@ -8873,7 +8893,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_revh_sve(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_revh, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_revh, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a REVW instruction. @@ -8888,7 +8908,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_revw_sve(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_revw, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_revw, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a COMPACT instruction. @@ -8903,7 +8923,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_compact_sve(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_compact, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_compact, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a PUNPKHI instruction. @@ -9220,7 +9240,7 @@ * \param Pg The governing predicate register, P (Predicate). */ #define INSTR_CREATE_pfirst_sve(dc, Pdn, Pg) \ - instr_create_1dst_2src(dc, OP_pfirst, Pdn, Pg, Pdn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_pfirst, Pdn, Pg, Pdn), DR_PRED_GOVERNING) /** * Creates a SEL instruction. @@ -9236,7 +9256,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_sel_sve_pred(dc, Pd, Pg, Pn, Pm) \ - instr_create_1dst_3src(dc, OP_sel, Pd, Pg, Pn, Pm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sel, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) /** * Creates a SEL instruction. @@ -9247,12 +9267,12 @@ * \endverbatim * \param dc The void * dcontext used to allocate memory for the #instr_t. * \param Zd The destination vector register, Z (Scalable). - * \param Pv The first source predicate register, P (Predicate). - * \param Zn The second source vector register, Z (Scalable). - * \param Zm The third source vector register, Z (Scalable). + * \param Pv The governing predicate register, P (Predicate). + * \param Zn The first source vector register, Z (Scalable). + * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_sel_sve_vector(dc, Zd, Pv, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_sel, Zd, Pv, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sel, Zd, Pv, Zn, Zm), DR_PRED_GOVERNING) /** * Creates an MOV instruction. @@ -9265,9 +9285,11 @@ * \param Pd The destination predicate register, P (Predicate). * \param Pn The first source predicate register, P (Predicate). */ -#define INSTR_CREATE_mov_sve_pred(dc, Pd, Pn) \ - instr_create_1dst_3src(dc, OP_orr, Pd, \ - opnd_create_predicate_reg(opnd_get_reg(Pn), false), Pn, Pn) +#define INSTR_CREATE_mov_sve_pred(dc, Pd, Pn) \ + INSTR_PRED( \ + instr_create_1dst_3src( \ + dc, OP_orr, Pd, opnd_create_predicate_reg(opnd_get_reg(Pn), false), Pn, Pn), \ + DR_PRED_GOVERNING) /** * Creates an MOVS instruction. @@ -9282,7 +9304,7 @@ * \param Pn The first source predicate register, P (Predicate). */ #define INSTR_CREATE_movs_sve_pred(dc, Pd, Pg, Pn) \ - instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pn) + INSTR_PRED(instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pn), DR_PRED_GOVERNING) /** * Creates a PTRUE instruction. @@ -9340,7 +9362,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_asr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an ASR instruction. @@ -9355,7 +9377,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_asr_sve_pred_wide(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an ASR instruction. @@ -9385,7 +9407,7 @@ * \param imm The immediate imm, one indexed. */ #define INSTR_CREATE_asrd_sve_pred(dc, Zdn, Pg, imm) \ - instr_create_1dst_3src(dc, OP_asrd, Zdn, Pg, Zdn, imm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_asrd, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) /** * Creates an ASRR instruction. @@ -9400,7 +9422,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_asrr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_asrr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_asrr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a CLS instruction. @@ -9415,7 +9437,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_cls_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_cls, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_cls, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a CLZ instruction. @@ -9430,7 +9452,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_clz_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_clz, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_clz, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a CNT instruction. @@ -9445,7 +9467,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_cnt_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a LSL instruction. @@ -9475,7 +9497,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_lsl_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_lsl, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_lsl, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a LSL instruction. @@ -9490,7 +9512,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_lsl_sve_pred_wide(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_lsl, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_lsl, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a LSL instruction. @@ -9520,7 +9542,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_lslr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_lslr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_lslr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a LSR instruction. @@ -9550,7 +9572,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_lsr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_lsr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_lsr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a LSR instruction. @@ -9565,7 +9587,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_lsr_sve_pred_wide(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_lsr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_lsr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a LSR instruction. @@ -9595,7 +9617,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_lsrr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_lsrr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_lsrr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a RBIT instruction. @@ -9610,7 +9632,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_rbit_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_rbit, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_rbit, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates an ANDV instruction. @@ -9627,7 +9649,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_andv_sve_pred(dc, Vd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_andv, Vd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_andv, Vd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates an EORV instruction. @@ -9644,7 +9666,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_eorv_sve_pred(dc, Vd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_eorv, Vd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_eorv, Vd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FADDA instruction. @@ -9661,7 +9683,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fadda_sve_pred(dc, Vdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fadda, Vdn, Pg, Vdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fadda, Vdn, Pg, Vdn, Zm), DR_PRED_GOVERNING) /** * Creates a FADDV instruction. @@ -9677,7 +9699,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_faddv_sve_pred(dc, Vd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_faddv, Vd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_faddv, Vd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FMAXNMV instruction. @@ -9693,7 +9715,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fmaxnmv_sve_pred(dc, Vd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_fmaxnmv, Vd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fmaxnmv, Vd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FMAXV instruction. @@ -9709,7 +9731,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fmaxv_sve_pred(dc, Vd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_fmaxv, Vd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fmaxv, Vd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FMINNMV instruction. @@ -9725,7 +9747,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fminnmv_sve_pred(dc, Vd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_fminnmv, Vd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fminnmv, Vd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FMINV instruction. @@ -9741,7 +9763,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fminv_sve_pred(dc, Vd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_fminv, Vd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fminv, Vd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates an ORV instruction. @@ -9758,7 +9780,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_orv_sve_pred(dc, Vd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_orv, Vd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_orv, Vd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a SADDV instruction. @@ -9773,7 +9795,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_saddv_sve_pred(dc, Vd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_saddv, Vd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_saddv, Vd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a SMAXV instruction. @@ -9790,7 +9812,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_smaxv_sve_pred(dc, Vd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_smaxv, Vd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_smaxv, Vd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a SMINV instruction. @@ -9807,7 +9829,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_sminv_sve_pred(dc, Vd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_sminv, Vd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_sminv, Vd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates an UADDV instruction. @@ -9822,7 +9844,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_uaddv_sve_pred(dc, Vd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_uaddv, Vd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_uaddv, Vd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates an UMAXV instruction. @@ -9839,7 +9861,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_umaxv_sve_pred(dc, Vd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_umaxv, Vd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_umaxv, Vd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates an UMINV instruction. @@ -9856,7 +9878,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_uminv_sve_pred(dc, Vd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_uminv, Vd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_uminv, Vd, Pg, Zn), DR_PRED_GOVERNING) /* * Creates a FCPY instruction. @@ -9867,7 +9889,7 @@ * \param imm The floating-point immediate value to be copied. */ #define INSTR_CREATE_fcpy_sve_pred(dc, Zd, Pg, imm) \ - instr_create_1dst_2src(dc, OP_fcpy, Zd, Pg, imm) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fcpy, Zd, Pg, imm), DR_PRED_GOVERNING) /** * Creates a FDUP instruction. @@ -9901,7 +9923,7 @@ * OPSZ_1) */ #define INSTR_CREATE_ld1rb_sve(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ld1rb, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rb, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LD1RH instruction. @@ -9921,7 +9943,7 @@ * OPSZ_2) */ #define INSTR_CREATE_ld1rh_sve(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ld1rh, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rh, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LD1RW instruction. @@ -9940,7 +9962,7 @@ * OPSZ_4) */ #define INSTR_CREATE_ld1rw_sve(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ld1rw, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rw, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LD1RD instruction. @@ -9958,7 +9980,7 @@ * OPSZ_8) */ #define INSTR_CREATE_ld1rd_sve(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ld1rd, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rd, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LD1RSB instruction. @@ -9978,7 +10000,7 @@ * OPSZ_1) */ #define INSTR_CREATE_ld1rsb_sve(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ld1rsb, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsb, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LD1RSH instruction. @@ -9997,7 +10019,7 @@ * OPSZ_2) */ #define INSTR_CREATE_ld1rsh_sve(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ld1rsh, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsh, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LD1RSW instruction. @@ -10015,7 +10037,7 @@ * OPSZ_4) */ #define INSTR_CREATE_ld1rsw_sve(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ld1rsw, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsw, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates an INDEX instruction. @@ -10057,7 +10079,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fcvt_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_fcvt, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvt, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FCVTZS instruction. @@ -10078,7 +10100,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fcvtzs_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_fcvtzs, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtzs, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FCVTZU instruction. @@ -10099,7 +10121,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fcvtzu_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_fcvtzu, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtzu, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FRINTA instruction. @@ -10114,7 +10136,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_frinta_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_frinta, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_frinta, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FRINTI instruction. @@ -10129,7 +10151,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_frinti_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_frinti, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_frinti, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FRINTM instruction. @@ -10144,7 +10166,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_frintm_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_frintm, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_frintm, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FRINTN instruction. @@ -10159,7 +10181,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_frintn_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_frintn, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_frintn, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FRINTP instruction. @@ -10174,7 +10196,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_frintp_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_frintp, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_frintp, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FRINTX instruction. @@ -10189,7 +10211,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_frintx_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_frintx, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_frintx, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FRINTZ instruction. @@ -10204,7 +10226,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_frintz_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_frintz, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_frintz, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a SCVTF instruction. @@ -10225,7 +10247,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_scvtf_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_scvtf, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_scvtf, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates an UCVTF instruction. @@ -10246,7 +10268,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_ucvtf_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_ucvtf, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ucvtf, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a CTERMEQ instruction. @@ -10291,7 +10313,7 @@ * \param Pv The first source predicate register, P (Predicate). */ #define INSTR_CREATE_pnext_sve(dc, Pdn, Pv) \ - instr_create_1dst_2src(dc, OP_pnext, Pdn, Pv, Pdn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_pnext, Pdn, Pv, Pdn), DR_PRED_GOVERNING) /** * Creates a FABD instruction. @@ -10306,7 +10328,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fabd_sve(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fabd, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fabd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FABS instruction. @@ -10321,7 +10343,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fabs_sve(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_fabs, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fabs, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FDIV instruction. @@ -10336,7 +10358,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fdiv_sve(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fdiv, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fdiv, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FDIVR instruction. @@ -10351,7 +10373,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fdivr_sve(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fdivr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fdivr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FMAD instruction. @@ -10366,8 +10388,9 @@ * \param Zm The second source vector register, Z (Scalable). * \param Za The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_fmad_sve(dc, Zdn, Pg, Zm, Za) \ - instr_create_1dst_4src(dc, OP_fmad, Zdn, Zdn, Pg, Zm, Za) +#define INSTR_CREATE_fmad_sve(dc, Zdn, Pg, Zm, Za) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fmad, Zdn, Zdn, Pg, Zm, Za), \ + DR_PRED_GOVERNING) /** * Creates a FMULX instruction. @@ -10382,7 +10405,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fmulx_sve(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fmulx, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmulx, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FNEG instruction. @@ -10397,7 +10420,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fneg_sve(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_fneg, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fneg, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FNMAD instruction. @@ -10412,8 +10435,9 @@ * \param Zm The second source vector register, Z (Scalable). * \param Za The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_fnmad_sve(dc, Zdn, Pg, Zm, Za) \ - instr_create_1dst_4src(dc, OP_fnmad, Zdn, Zdn, Pg, Zm, Za) +#define INSTR_CREATE_fnmad_sve(dc, Zdn, Pg, Zm, Za) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmad, Zdn, Zdn, Pg, Zm, Za), \ + DR_PRED_GOVERNING) /** * Creates a FNMLA instruction. @@ -10428,8 +10452,9 @@ * \param Zn The second source vector register, Z (Scalable). * \param Zm The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_fnmla_sve(dc, Zda, Pg, Zn, Zm) \ - instr_create_1dst_4src(dc, OP_fnmla, Zda, Zda, Pg, Zn, Zm) +#define INSTR_CREATE_fnmla_sve(dc, Zda, Pg, Zn, Zm) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmla, Zda, Zda, Pg, Zn, Zm), \ + DR_PRED_GOVERNING) /** * Creates a FNMLS instruction. @@ -10444,8 +10469,9 @@ * \param Zn The second source vector register, Z (Scalable). * \param Zm The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_fnmls_sve(dc, Zda, Pg, Zn, Zm) \ - instr_create_1dst_4src(dc, OP_fnmls, Zda, Zda, Pg, Zn, Zm) +#define INSTR_CREATE_fnmls_sve(dc, Zda, Pg, Zn, Zm) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmls, Zda, Zda, Pg, Zn, Zm), \ + DR_PRED_GOVERNING) /** * Creates a FNMSB instruction. @@ -10460,8 +10486,9 @@ * \param Zm The second source vector register, Z (Scalable). * \param Za The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_fnmsb_sve_pred(dc, Zdn, Pg, Zm, Za) \ - instr_create_1dst_4src(dc, OP_fnmsb, Zdn, Zdn, Pg, Zm, Za) +#define INSTR_CREATE_fnmsb_sve_pred(dc, Zdn, Pg, Zm, Za) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmsb, Zdn, Zdn, Pg, Zm, Za), \ + DR_PRED_GOVERNING) /** * Creates a FRECPE instruction. @@ -10504,7 +10531,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_frecpx_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_frecpx, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_frecpx, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FRSQRTE instruction. @@ -10548,7 +10575,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fscale_sve(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fscale, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fscale, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FSQRT instruction. @@ -10563,7 +10590,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fsqrt_sve(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_fsqrt, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fsqrt, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FADD instruction. @@ -10578,7 +10605,7 @@ * \param imm Floating point constant, either 0.5 or 1.0. */ #define INSTR_CREATE_fadd_sve(dc, Zdn, Pg, imm) \ - instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, imm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) /** * Creates a FADD instruction. @@ -10593,7 +10620,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fadd_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FADD instruction. @@ -10623,7 +10650,7 @@ * \param imm Floating point constant, either 0.5 or 1.0. */ #define INSTR_CREATE_fsub_sve(dc, Zdn, Pg, imm) \ - instr_create_1dst_3src(dc, OP_fsub, Zdn, Pg, Zdn, imm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fsub, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) /** * Creates a FSUB instruction. @@ -10638,7 +10665,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fsub_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fsub, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fsub, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FSUB instruction. @@ -10668,7 +10695,7 @@ * \param imm Floating point constant, either 0.5 or 1.0. */ #define INSTR_CREATE_fsubr_sve(dc, Zdn, Pg, imm) \ - instr_create_1dst_3src(dc, OP_fsubr, Zdn, Pg, Zdn, imm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fsubr, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) /** * Creates a FSUBR instruction. @@ -10683,7 +10710,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fsubr_sve_vector(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fsubr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fsubr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FMAX instruction. @@ -10698,7 +10725,7 @@ * \param imm Floating point constant, either 0.0 or 1.0. */ #define INSTR_CREATE_fmax_sve(dc, Zdn, Pg, imm) \ - instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, imm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) /** * Creates a FMAX instruction. @@ -10713,7 +10740,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fmax_sve_vector(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FMAXNM instruction. @@ -10727,8 +10754,9 @@ * \param Pg The governing predicate register, P (Predicate). * \param imm Floating point constant, either 0.0 or 1.0. */ -#define INSTR_CREATE_fmaxnm_sve(dc, Zdn, Pg, imm) \ - instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, imm) +#define INSTR_CREATE_fmaxnm_sve(dc, Zdn, Pg, imm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, imm), \ + DR_PRED_GOVERNING) /** * Creates a FMAXNM instruction. @@ -10743,7 +10771,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fmaxnm_sve_vector(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FMIN instruction. @@ -10758,7 +10786,7 @@ * \param imm Floating point constant, either 0.0 or 1.0. */ #define INSTR_CREATE_fmin_sve(dc, Zdn, Pg, imm) \ - instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, imm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) /** * Creates a FMIN instruction. @@ -10773,7 +10801,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fmin_sve_vector(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FMINNM instruction. @@ -10787,8 +10815,9 @@ * \param Pg The governing predicate register, P (Predicate). * \param imm Floating point constant, either 0.0 or 1.0. */ -#define INSTR_CREATE_fminnm_sve(dc, Zdn, Pg, imm) \ - instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, imm) +#define INSTR_CREATE_fminnm_sve(dc, Zdn, Pg, imm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, imm), \ + DR_PRED_GOVERNING) /** * Creates a FMINNM instruction. @@ -10803,7 +10832,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fminnm_sve_vector(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FMLA instruction. @@ -10818,8 +10847,9 @@ * \param Zn The first source vector register, Z (Scalable). * \param Zm The second source vector register, Z (Scalable). */ -#define INSTR_CREATE_fmla_sve_vector(dc, Zda, Pg, Zn, Zm) \ - instr_create_1dst_4src(dc, OP_fmla, Zda, Zda, Pg, Zn, Zm) +#define INSTR_CREATE_fmla_sve_vector(dc, Zda, Pg, Zn, Zm) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fmla, Zda, Zda, Pg, Zn, Zm), \ + DR_PRED_GOVERNING) /** * Creates a FMLA instruction. @@ -10852,8 +10882,9 @@ * \param Zn The first source vector register, Z (Scalable). * \param Zm The second source vector register, Z (Scalable). */ -#define INSTR_CREATE_fmls_sve_vector(dc, Zda, Pg, Zn, Zm) \ - instr_create_1dst_4src(dc, OP_fmls, Zda, Zda, Pg, Zn, Zm) +#define INSTR_CREATE_fmls_sve_vector(dc, Zda, Pg, Zn, Zm) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fmls, Zda, Zda, Pg, Zn, Zm), \ + DR_PRED_GOVERNING) /** * Creates a FMLS instruction. @@ -10886,8 +10917,9 @@ * \param Zm The second source vector register, Z (Scalable). * \param Za The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_fmsb_sve(dc, Zdn, Pg, Zm, Za) \ - instr_create_1dst_4src(dc, OP_fmsb, Zdn, Zdn, Pg, Zm, Za) +#define INSTR_CREATE_fmsb_sve(dc, Zdn, Pg, Zm, Za) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fmsb, Zdn, Zdn, Pg, Zm, Za), \ + DR_PRED_GOVERNING) /** * Creates a FMUL instruction. @@ -10902,7 +10934,7 @@ * \param imm Floating point constant, either 0.5 or 2.0. */ #define INSTR_CREATE_fmul_sve(dc, Zdn, Pg, imm) \ - instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, imm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) /** * Creates a FMUL instruction. @@ -10917,7 +10949,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fmul_sve_pred_vector(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FMUL instruction. @@ -11034,7 +11066,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 32), 0) */ #define INSTR_CREATE_ldff1b_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldff1b, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1b, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LDFF1D instruction. @@ -11073,7 +11105,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 16), 0) */ #define INSTR_CREATE_ldff1d_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldff1d, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1d, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LDFF1H instruction. @@ -11126,7 +11158,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 16), 0) */ #define INSTR_CREATE_ldff1h_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldff1h, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1h, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LDFF1SB instruction. @@ -11166,7 +11198,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 32), 0) */ #define INSTR_CREATE_ldff1sb_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldff1sb, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sb, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LDFF1SH instruction. @@ -11218,7 +11250,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 16), 0) */ #define INSTR_CREATE_ldff1sh_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldff1sh, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sh, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LDFF1SW instruction. @@ -11265,7 +11297,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 8), 0) */ #define INSTR_CREATE_ldff1sw_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldff1sw, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sw, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LDFF1W instruction. @@ -11293,7 +11325,7 @@ * DR_EXTEND_UXTX, 0, imm5, 0, opnd_size_from_bytes(dr_get_sve_vl() / 16), 0) */ #define INSTR_CREATE_ldff1w_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldff1w, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1w, Zt, Rn, Pg), DR_PRED_GOVERNING) /** @@ -11309,8 +11341,9 @@ * \param Zm The second source vector register, Z (Scalable). * \param rot The immediate rot, must be 90 or 270. */ -#define INSTR_CREATE_fcadd_sve_pred(dc, Zdn, Pg, Zm, rot) \ - instr_create_1dst_4src(dc, OP_fcadd, Zdn, Pg, Zdn, Zm, rot) +#define INSTR_CREATE_fcadd_sve_pred(dc, Zdn, Pg, Zm, rot) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fcadd, Zdn, Pg, Zdn, Zm, rot), \ + DR_PRED_GOVERNING) /** * Creates a FCMLA instruction. @@ -11326,8 +11359,9 @@ * \param Zm The third source vector register, Z (Scalable). * \param rot The immediate rot, must be 0, 90, 180, or 270. */ -#define INSTR_CREATE_fcmla_sve_vector(dc, Zda, Pg, Zn, Zm, rot) \ - instr_create_1dst_5src(dc, OP_fcmla, Zda, Zda, Pg, Zn, Zm, rot) +#define INSTR_CREATE_fcmla_sve_vector(dc, Zda, Pg, Zn, Zm, rot) \ + INSTR_PRED(instr_create_1dst_5src(dc, OP_fcmla, Zda, Zda, Pg, Zn, Zm, rot), \ + DR_PRED_GOVERNING) /** * Creates a FCMLA instruction. @@ -11403,7 +11437,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 32), 0) */ #define INSTR_CREATE_ld1b_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ld1b, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1b, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LD1ROB instruction. @@ -11421,7 +11455,7 @@ * DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1) */ #define INSTR_CREATE_ld1rob_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ld1rob, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rob, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LD1RQB instruction. @@ -11444,7 +11478,7 @@ * Xn, Xm, DR_EXTEND_UXTX, false, 0, 0, OPSZ_16, 0) */ #define INSTR_CREATE_ld1rqb_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ld1rqb, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqb, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LD1RQH instruction. @@ -11467,7 +11501,7 @@ * Xn, Xm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_16, 1) */ #define INSTR_CREATE_ld1rqh_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ld1rqh, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqh, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LD1RQW instruction. @@ -11490,7 +11524,7 @@ * Xn, Xm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_16, 2) */ #define INSTR_CREATE_ld1rqw_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ld1rqw, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqw, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LD1RQD instruction. @@ -11513,7 +11547,7 @@ * Xn, Xm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_16, 3) */ #define INSTR_CREATE_ld1rqd_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ld1rqd, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqd, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LD1SB instruction. @@ -11566,7 +11600,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 32), 0) */ #define INSTR_CREATE_ld1sb_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ld1sb, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sb, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LDNT1B instruction. @@ -11593,7 +11627,7 @@ * DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1) */ #define INSTR_CREATE_ldnt1b_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldnt1b, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1b, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a ST1B instruction. @@ -11636,7 +11670,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 32), 0) */ #define INSTR_CREATE_st1b_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_st1b, Rn, Zt, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_st1b, Rn, Zt, Pg), DR_PRED_GOVERNING) /** * Creates a STNT1B instruction. @@ -11673,7 +11707,7 @@ * 0) */ #define INSTR_CREATE_stnt1b_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_stnt1b, Rn, Zt, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1b, Rn, Zt, Pg), DR_PRED_GOVERNING) /** * Creates a BFCVT instruction. @@ -11688,7 +11722,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_bfcvt_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_bfcvt, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_bfcvt, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a BFDOT instruction. @@ -11930,7 +11964,7 @@ * DR_EXTEND_UXTX, false, 0, 0, OPSZ_0, 0) */ #define INSTR_CREATE_prfb_sve_pred(dc, prfop, Pg, Rn) \ - instr_create_0dst_3src(dc, OP_prfb, prfop, Pg, Rn) + INSTR_PRED(instr_create_0dst_3src(dc, OP_prfb, prfop, Pg, Rn), DR_PRED_GOVERNING) /** * Creates a PRFD instruction. @@ -11972,7 +12006,7 @@ * DR_EXTEND_UXTX, true, 0, 0, OPSZ_0, 3) */ #define INSTR_CREATE_prfd_sve_pred(dc, prfop, Pg, Rn) \ - instr_create_0dst_3src(dc, OP_prfd, prfop, Pg, Rn) + INSTR_PRED(instr_create_0dst_3src(dc, OP_prfd, prfop, Pg, Rn), DR_PRED_GOVERNING) /** * Creates a PRFH instruction. @@ -12014,7 +12048,7 @@ * DR_EXTEND_UXTX, true, 0, 0, OPSZ_0, 1) */ #define INSTR_CREATE_prfh_sve_pred(dc, prfop, Pg, Rn) \ - instr_create_0dst_3src(dc, OP_prfh, prfop, Pg, Rn) + INSTR_PRED(instr_create_0dst_3src(dc, OP_prfh, prfop, Pg, Rn), DR_PRED_GOVERNING) /** * Creates a PRFW instruction. @@ -12056,7 +12090,7 @@ * DR_EXTEND_UXTX, true, 0, 0, OPSZ_0, 2) */ #define INSTR_CREATE_prfw_sve_pred(dc, prfop, Pg, Rn) \ - instr_create_0dst_3src(dc, OP_prfw, prfop, Pg, Rn) + INSTR_PRED(instr_create_0dst_3src(dc, OP_prfw, prfop, Pg, Rn), DR_PRED_GOVERNING) /** * Creates an ADR instruction. @@ -12102,8 +12136,10 @@ * * The Zt2 parameter is derived from Zt. */ -#define INSTR_CREATE_ld2b_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_2dst_2src(dc, OP_ld2b, Zt, opnd_create_increment_reg(Zt, 1), Rn, Pg) +#define INSTR_CREATE_ld2b_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_2dst_2src(dc, OP_ld2b, Zt, opnd_create_increment_reg(Zt, 1), \ + Rn, Pg), \ + DR_PRED_GOVERNING) /** * Creates a LD3B instruction. @@ -12127,9 +12163,10 @@ * * The Zt2 and Zt3 parameters are derived from Zt. */ -#define INSTR_CREATE_ld3b_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_3dst_2src(dc, OP_ld3b, Zt, opnd_create_increment_reg(Zt, 1), \ - opnd_create_increment_reg(Zt, 2), Rn, Pg) +#define INSTR_CREATE_ld3b_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_3dst_2src(dc, OP_ld3b, Zt, opnd_create_increment_reg(Zt, 1), \ + opnd_create_increment_reg(Zt, 2), Rn, Pg), \ + DR_PRED_GOVERNING) /** * Creates a LD4B instruction. @@ -12153,10 +12190,11 @@ * * The Zt2, Zt3 and Zt4 parameters are derived from Zt. */ -#define INSTR_CREATE_ld4b_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_4dst_2src(dc, OP_ld4b, Zt, opnd_create_increment_reg(Zt, 1), \ - opnd_create_increment_reg(Zt, 2), \ - opnd_create_increment_reg(Zt, 3), Rn, Pg) +#define INSTR_CREATE_ld4b_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_4dst_2src(dc, OP_ld4b, Zt, opnd_create_increment_reg(Zt, 1), \ + opnd_create_increment_reg(Zt, 2), \ + opnd_create_increment_reg(Zt, 3), Rn, Pg), \ + DR_PRED_GOVERNING) /** * Creates a ST2B instruction. @@ -12180,8 +12218,10 @@ * * The Zt2 parameter is derived from Zt. */ -#define INSTR_CREATE_st2b_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_3src(dc, OP_st2b, Rn, Zt, opnd_create_increment_reg(Zt, 1), Pg) +#define INSTR_CREATE_st2b_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_st2b, Rn, Zt, \ + opnd_create_increment_reg(Zt, 1), Pg), \ + DR_PRED_GOVERNING) /** * Creates a ST3B instruction. @@ -12205,9 +12245,11 @@ * * The Zt2 and Zt3 parameters are derived from Zt. */ -#define INSTR_CREATE_st3b_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_4src(dc, OP_st3b, Rn, Zt, opnd_create_increment_reg(Zt, 1), \ - opnd_create_increment_reg(Zt, 2), Pg) +#define INSTR_CREATE_st3b_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_st3b, Rn, Zt, \ + opnd_create_increment_reg(Zt, 1), \ + opnd_create_increment_reg(Zt, 2), Pg), \ + DR_PRED_GOVERNING) /** * Creates a ST4B instruction. @@ -12231,10 +12273,12 @@ * * The Zt2, Zt3 and Zt4 parameters are derived from Zt. */ -#define INSTR_CREATE_st4b_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_5src(dc, OP_st4b, Rn, Zt, opnd_create_increment_reg(Zt, 1), \ - opnd_create_increment_reg(Zt, 2), \ - opnd_create_increment_reg(Zt, 3), Pg) +#define INSTR_CREATE_st4b_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_1dst_5src(dc, OP_st4b, Rn, Zt, \ + opnd_create_increment_reg(Zt, 1), \ + opnd_create_increment_reg(Zt, 2), \ + opnd_create_increment_reg(Zt, 3), Pg), \ + DR_PRED_GOVERNING) /** * Creates a LD1H instruction. @@ -12300,7 +12344,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 32)) */ #define INSTR_CREATE_ld1h_sve_pred(dc, Zt, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_ld1h, Zt, Zn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1h, Zt, Zn, Pg), DR_PRED_GOVERNING) /** * Creates a LD1SH instruction. @@ -12361,7 +12405,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 32)) */ #define INSTR_CREATE_ld1sh_sve_pred(dc, Zt, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_ld1sh, Zt, Zn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sh, Zt, Zn, Pg), DR_PRED_GOVERNING) /** * Creates a LD1W instruction. @@ -12421,8 +12465,10 @@ * opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, * opnd_size_from_bytes(dr_get_sve_vector_length() / 16)) */ -#define INSTR_CREATE_ld1w_sve_pred(dc, Zt, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_ld1w, Zt, Zn, Pg) +#define INSTR_CREATE_ld1w_sve_pred(dc, Zt, Pg, Zn) \ + INSTR_PRED( \ + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1w, Zt, Zn, Pg), DR_PRED_GOVERNING), \ + DR_PRED_GOVERNING) /** * Creates a LD1D instruction. @@ -12465,7 +12511,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 8)) */ #define INSTR_CREATE_ld1d_sve_pred(dc, Zt, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_ld1d, Zt, Zn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1d, Zt, Zn, Pg), DR_PRED_GOVERNING) /** * Creates a LD1SW instruction. @@ -12493,7 +12539,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 16)) */ #define INSTR_CREATE_ld1sw_sve_pred(dc, Zt, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_ld1sw, Zt, Zn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sw, Zt, Zn, Pg), DR_PRED_GOVERNING) /** * Creates a ST1H instruction. @@ -12549,7 +12595,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / opnd_size_to_bytes(Ts))) */ #define INSTR_CREATE_st1h_sve_pred(dc, Zt, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_st1h, Zn, Zt, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_st1h, Zn, Zt, Pg), DR_PRED_GOVERNING) /** * Creates a ST1W instruction. @@ -12606,7 +12652,7 @@ * opnd_size_to_bytes(Ts)))) */ #define INSTR_CREATE_st1w_sve_pred(dc, Zt, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_st1w, Zn, Zt, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_st1w, Zn, Zt, Pg), DR_PRED_GOVERNING) /** * Creates a ST1D instruction. @@ -12649,7 +12695,7 @@ * opnd_size_to_bytes(Ts)))) */ #define INSTR_CREATE_st1d_sve_pred(dc, Zt, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_st1d, Zn, Zt, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_st1d, Zn, Zt, Pg), DR_PRED_GOVERNING) /** * Creates a LD2D instruction. @@ -12673,8 +12719,10 @@ * * The Zt2 parameter is derived from Zt. */ -#define INSTR_CREATE_ld2d_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_2dst_2src(dc, OP_ld2d, Zt, opnd_create_increment_reg(Zt, 1), Rn, Pg) +#define INSTR_CREATE_ld2d_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_2dst_2src(dc, OP_ld2d, Zt, opnd_create_increment_reg(Zt, 1), \ + Rn, Pg), \ + DR_PRED_GOVERNING) /** * Creates a LD2H instruction. @@ -12698,8 +12746,10 @@ * * The Zt2 parameter is derived from Zt. */ -#define INSTR_CREATE_ld2h_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_2dst_2src(dc, OP_ld2h, Zt, opnd_create_increment_reg(Zt, 1), Rn, Pg) +#define INSTR_CREATE_ld2h_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_2dst_2src(dc, OP_ld2h, Zt, opnd_create_increment_reg(Zt, 1), \ + Rn, Pg), \ + DR_PRED_GOVERNING) /** * Creates a LD2W instruction. @@ -12722,8 +12772,10 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 4)) * opnd_size_from_bytes(2 * (dr_get_sve_vector_length() / 8))) */ -#define INSTR_CREATE_ld2w_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_2dst_2src(dc, OP_ld2w, Zt, opnd_create_increment_reg(Zt, 1), Rn, Pg) +#define INSTR_CREATE_ld2w_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_2dst_2src(dc, OP_ld2w, Zt, opnd_create_increment_reg(Zt, 1), \ + Rn, Pg), \ + DR_PRED_GOVERNING) /** * Creates a LD3D instruction. @@ -12747,9 +12799,10 @@ * * The Zt2 and Zt3 parameters are derived from Zt. */ -#define INSTR_CREATE_ld3d_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_3dst_2src(dc, OP_ld3d, Zt, opnd_create_increment_reg(Zt, 1), \ - opnd_create_increment_reg(Zt, 2), Rn, Pg) +#define INSTR_CREATE_ld3d_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_3dst_2src(dc, OP_ld3d, Zt, opnd_create_increment_reg(Zt, 1), \ + opnd_create_increment_reg(Zt, 2), Rn, Pg), \ + DR_PRED_GOVERNING) /** * Creates a LD3H instruction. @@ -12773,9 +12826,10 @@ * * The Zt2 and Zt3 parameters are derived from Zt. */ -#define INSTR_CREATE_ld3h_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_3dst_2src(dc, OP_ld3h, Zt, opnd_create_increment_reg(Zt, 1), \ - opnd_create_increment_reg(Zt, 2), Rn, Pg) +#define INSTR_CREATE_ld3h_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_3dst_2src(dc, OP_ld3h, Zt, opnd_create_increment_reg(Zt, 1), \ + opnd_create_increment_reg(Zt, 2), Rn, Pg), \ + DR_PRED_GOVERNING) /** * Creates a LD3W instruction. @@ -12799,9 +12853,10 @@ * * The Zt2 and Zt3 parameters are derived from Zt. */ -#define INSTR_CREATE_ld3w_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_3dst_2src(dc, OP_ld3w, Zt, opnd_create_increment_reg(Zt, 1), \ - opnd_create_increment_reg(Zt, 2), Rn, Pg) +#define INSTR_CREATE_ld3w_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_3dst_2src(dc, OP_ld3w, Zt, opnd_create_increment_reg(Zt, 1), \ + opnd_create_increment_reg(Zt, 2), Rn, Pg), \ + DR_PRED_GOVERNING) /** * Creates a LD4D instruction. @@ -12825,10 +12880,11 @@ * * The Zt2, Zt3 and Zt4 parameters are derived from Zt. */ -#define INSTR_CREATE_ld4d_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_4dst_2src(dc, OP_ld4d, Zt, opnd_create_increment_reg(Zt, 1), \ - opnd_create_increment_reg(Zt, 2), \ - opnd_create_increment_reg(Zt, 3), Rn, Pg) +#define INSTR_CREATE_ld4d_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_4dst_2src(dc, OP_ld4d, Zt, opnd_create_increment_reg(Zt, 1), \ + opnd_create_increment_reg(Zt, 2), \ + opnd_create_increment_reg(Zt, 3), Rn, Pg), \ + DR_PRED_GOVERNING) /** * Creates a LD4H instruction. @@ -12852,10 +12908,11 @@ * * The Zt2, Zt3 and Zt4 parameters are derived from Zt. */ -#define INSTR_CREATE_ld4h_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_4dst_2src(dc, OP_ld4h, Zt, opnd_create_increment_reg(Zt, 1), \ - opnd_create_increment_reg(Zt, 2), \ - opnd_create_increment_reg(Zt, 3), Rn, Pg) +#define INSTR_CREATE_ld4h_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_4dst_2src(dc, OP_ld4h, Zt, opnd_create_increment_reg(Zt, 1), \ + opnd_create_increment_reg(Zt, 2), \ + opnd_create_increment_reg(Zt, 3), Rn, Pg), \ + DR_PRED_GOVERNING) /** * Creates a LD4W instruction. @@ -12879,10 +12936,11 @@ * * The Zt2, Zt3 and Zt4 parameters are derived from Zt. */ -#define INSTR_CREATE_ld4w_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_4dst_2src(dc, OP_ld4w, Zt, opnd_create_increment_reg(Zt, 1), \ - opnd_create_increment_reg(Zt, 2), \ - opnd_create_increment_reg(Zt, 3), Rn, Pg) +#define INSTR_CREATE_ld4w_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_4dst_2src(dc, OP_ld4w, Zt, opnd_create_increment_reg(Zt, 1), \ + opnd_create_increment_reg(Zt, 2), \ + opnd_create_increment_reg(Zt, 3), Rn, Pg), \ + DR_PRED_GOVERNING) /** * Creates a LDNT1D instruction. @@ -12911,7 +12969,7 @@ * opnd_size_from_bytes(proc_get_vector_length_bytes()), 0) */ #define INSTR_CREATE_ldnt1d_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldnt1d, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1d, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LDNT1H instruction. @@ -12946,7 +13004,7 @@ * opnd_size_from_bytes(proc_get_vector_length_bytes() / 2), 0) */ #define INSTR_CREATE_ldnt1h_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldnt1h, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1h, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LDNT1W instruction. @@ -12979,7 +13037,7 @@ * 0, opnd_size_from_bytes(proc_get_vector_length_bytes()), 0) */ #define INSTR_CREATE_ldnt1w_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldnt1w, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1w, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a ST2D instruction. @@ -13003,8 +13061,10 @@ * * The Zt2 parameter is derived from Zt. */ -#define INSTR_CREATE_st2d_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_3src(dc, OP_st2d, Rn, Zt, opnd_create_increment_reg(Zt, 1), Pg) +#define INSTR_CREATE_st2d_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_st2d, Rn, Zt, \ + opnd_create_increment_reg(Zt, 1), Pg), \ + DR_PRED_GOVERNING) /** * Creates a ST2H instruction. @@ -13028,8 +13088,10 @@ * * The Zt2 parameter is derived from Zt. */ -#define INSTR_CREATE_st2h_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_3src(dc, OP_st2h, Rn, Zt, opnd_create_increment_reg(Zt, 1), Pg) +#define INSTR_CREATE_st2h_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_st2h, Rn, Zt, \ + opnd_create_increment_reg(Zt, 1), Pg), \ + DR_PRED_GOVERNING) /** * Creates a ST2W instruction. @@ -13053,8 +13115,10 @@ * * The Zt2 parameter is derived from Zt. */ -#define INSTR_CREATE_st2w_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_3src(dc, OP_st2w, Rn, Zt, opnd_create_increment_reg(Zt, 1), Pg) +#define INSTR_CREATE_st2w_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_st2w, Rn, Zt, \ + opnd_create_increment_reg(Zt, 1), Pg), \ + DR_PRED_GOVERNING) /** * Creates a ST3D instruction. @@ -13078,9 +13142,11 @@ * * The Zt2 and Zt3 parameters are derived from Zt. */ -#define INSTR_CREATE_st3d_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_4src(dc, OP_st3d, Rn, Zt, opnd_create_increment_reg(Zt, 1), \ - opnd_create_increment_reg(Zt, 2), Pg) +#define INSTR_CREATE_st3d_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_st3d, Rn, Zt, \ + opnd_create_increment_reg(Zt, 1), \ + opnd_create_increment_reg(Zt, 2), Pg), \ + DR_PRED_GOVERNING) /** * Creates a ST3H instruction. @@ -13104,9 +13170,11 @@ * * The Zt2 and Zt3 parameters are derived from Zt. */ -#define INSTR_CREATE_st3h_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_4src(dc, OP_st3h, Rn, Zt, opnd_create_increment_reg(Zt, 1), \ - opnd_create_increment_reg(Zt, 2), Pg) +#define INSTR_CREATE_st3h_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_st3h, Rn, Zt, \ + opnd_create_increment_reg(Zt, 1), \ + opnd_create_increment_reg(Zt, 2), Pg), \ + DR_PRED_GOVERNING) /** * Creates a ST3W instruction. @@ -13130,9 +13198,11 @@ * * The Zt2 and Zt3 parameters are derived from Zt. */ -#define INSTR_CREATE_st3w_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_4src(dc, OP_st3w, Rn, Zt, opnd_create_increment_reg(Zt, 1), \ - opnd_create_increment_reg(Zt, 2), Pg) +#define INSTR_CREATE_st3w_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_st3w, Rn, Zt, \ + opnd_create_increment_reg(Zt, 1), \ + opnd_create_increment_reg(Zt, 2), Pg), \ + DR_PRED_GOVERNING) /** * Creates a ST4D instruction. @@ -13156,10 +13226,12 @@ * * The Zt2, Zt3 and Zt4 parameters are derived from Zt. */ -#define INSTR_CREATE_st4d_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_5src(dc, OP_st4d, Rn, Zt, opnd_create_increment_reg(Zt, 1), \ - opnd_create_increment_reg(Zt, 2), \ - opnd_create_increment_reg(Zt, 3), Pg) +#define INSTR_CREATE_st4d_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_1dst_5src(dc, OP_st4d, Rn, Zt, \ + opnd_create_increment_reg(Zt, 1), \ + opnd_create_increment_reg(Zt, 2), \ + opnd_create_increment_reg(Zt, 3), Pg), \ + DR_PRED_GOVERNING) /** * Creates a ST4H instruction. @@ -13183,10 +13255,12 @@ * * The Zt2, Zt3 and Zt4 parameters are derived from Zt. */ -#define INSTR_CREATE_st4h_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_5src(dc, OP_st4h, Rn, Zt, opnd_create_increment_reg(Zt, 1), \ - opnd_create_increment_reg(Zt, 2), \ - opnd_create_increment_reg(Zt, 3), Pg) +#define INSTR_CREATE_st4h_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_1dst_5src(dc, OP_st4h, Rn, Zt, \ + opnd_create_increment_reg(Zt, 1), \ + opnd_create_increment_reg(Zt, 2), \ + opnd_create_increment_reg(Zt, 3), Pg), \ + DR_PRED_GOVERNING) /** * Creates a ST4W instruction. @@ -13210,10 +13284,12 @@ * * The Zt2, Zt3 and Zt4 parameters are derived from Zt. */ -#define INSTR_CREATE_st4w_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_5src(dc, OP_st4w, Rn, Zt, opnd_create_increment_reg(Zt, 1), \ - opnd_create_increment_reg(Zt, 2), \ - opnd_create_increment_reg(Zt, 3), Pg) +#define INSTR_CREATE_st4w_sve_pred(dc, Zt, Pg, Rn) \ + INSTR_PRED(instr_create_1dst_5src(dc, OP_st4w, Rn, Zt, \ + opnd_create_increment_reg(Zt, 1), \ + opnd_create_increment_reg(Zt, 2), \ + opnd_create_increment_reg(Zt, 3), Pg), \ + DR_PRED_GOVERNING) /** * Creates a STNT1D instruction. @@ -13243,7 +13319,7 @@ * opnd_size_from_bytes(proc_get_vector_length_bytes()), 0) */ #define INSTR_CREATE_stnt1d_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_stnt1d, Rn, Zt, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1d, Rn, Zt, Pg), DR_PRED_GOVERNING) /** * Creates a STNT1H instruction. @@ -13277,7 +13353,7 @@ * opnd_size_from_bytes(proc_get_vector_length_bytes() / 2), 0) */ #define INSTR_CREATE_stnt1h_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_stnt1h, Rn, Zt, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1h, Rn, Zt, Pg), DR_PRED_GOVERNING) /** * Creates a STNT1W instruction. @@ -13311,7 +13387,7 @@ * opnd_size_from_bytes(proc_get_vector_length_bytes()), 0) */ #define INSTR_CREATE_stnt1w_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_stnt1w, Rn, Zt, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1w, Rn, Zt, Pg), DR_PRED_GOVERNING) /** * Creates a LDNF1B instruction. @@ -13342,7 +13418,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 64)) */ #define INSTR_CREATE_ldnf1b_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldnf1b, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1b, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LDNF1D instruction. @@ -13360,7 +13436,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 8)) */ #define INSTR_CREATE_ldnf1d_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldnf1d, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1d, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LDNF1H instruction. @@ -13387,7 +13463,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 32)) */ #define INSTR_CREATE_ldnf1h_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldnf1h, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1h, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LDNF1SB instruction. @@ -13414,7 +13490,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 64)) */ #define INSTR_CREATE_ldnf1sb_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldnf1sb, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sb, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LDNF1SH instruction. @@ -13437,7 +13513,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 32)) */ #define INSTR_CREATE_ldnf1sh_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldnf1sh, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sh, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LDNF1SW instruction. @@ -13455,7 +13531,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 16)) */ #define INSTR_CREATE_ldnf1sw_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldnf1sw, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sw, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LDNF1W instruction. @@ -13478,7 +13554,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 16)) */ #define INSTR_CREATE_ldnf1w_sve_pred(dc, Zt, Pg, Rn) \ - instr_create_1dst_2src(dc, OP_ldnf1w, Zt, Rn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1w, Zt, Rn, Pg), DR_PRED_GOVERNING) /** * Creates a LDAPUR instruction. @@ -14414,7 +14490,7 @@ * \param Zn The second source vector register, Z (Scalable). */ #define INSTR_CREATE_bfcvtnt_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_3src(dc, OP_bfcvtnt, Zd, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_3src(dc, OP_bfcvtnt, Zd, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates an AESD instruction. @@ -16287,7 +16363,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_addp_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_addp, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_addp, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FADDP instruction. @@ -16303,7 +16379,7 @@ * \param Zm The second source vector register. Can be Z.h, Z.s or Z.d. */ #define INSTR_CREATE_faddp_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_faddp, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_faddp, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FMAXNMP instruction. @@ -16318,8 +16394,9 @@ * \param Pg The governing predicate register, P (Predicate). * \param Zm The second source vector register. Can be Z.h, Z.s or Z.d. */ -#define INSTR_CREATE_fmaxnmp_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fmaxnmp, Zdn, Pg, Zdn, Zm) +#define INSTR_CREATE_fmaxnmp_sve_pred(dc, Zdn, Pg, Zm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnmp, Zdn, Pg, Zdn, Zm), \ + DR_PRED_GOVERNING) /** * Creates a FMAXP instruction. @@ -16335,7 +16412,7 @@ * \param Zm The second source vector register. Can be Z.h, Z.s or Z.d. */ #define INSTR_CREATE_fmaxp_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fmaxp, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxp, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FMINNMP instruction. @@ -16350,8 +16427,9 @@ * \param Pg The governing predicate register, P (Predicate). * \param Zm The second source vector register. Can be Z.h, Z.s or Z.d. */ -#define INSTR_CREATE_fminnmp_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fminnmp, Zdn, Pg, Zdn, Zm) +#define INSTR_CREATE_fminnmp_sve_pred(dc, Zdn, Pg, Zm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnmp, Zdn, Pg, Zdn, Zm), \ + DR_PRED_GOVERNING) /** * Creates a FMINP instruction. @@ -16367,7 +16445,7 @@ * \param Zm The second source vector register. Can be Z.h, Z.s or Z.d. */ #define INSTR_CREATE_fminp_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_fminp, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fminp, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a HISTCNT instruction. @@ -16383,7 +16461,7 @@ * \param Zm The second source vector register. Can be Z.s or Z.d. */ #define INSTR_CREATE_histcnt_sve_pred(dc, Zd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_histcnt, Zd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_histcnt, Zd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a SHADD instruction. @@ -16399,7 +16477,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_shadd_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_shadd, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_shadd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SHSUB instruction. @@ -16415,7 +16493,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_shsub_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_shsub, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_shsub, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SHSUBR instruction. @@ -16431,7 +16509,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_shsubr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_shsubr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_shsubr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SMAXP instruction. @@ -16447,7 +16525,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_smaxp_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_smaxp, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_smaxp, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SMINP instruction. @@ -16463,7 +16541,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_sminp_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_sminp, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sminp, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SQRSHL instruction. @@ -16479,7 +16557,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_sqrshl_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_sqrshl, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sqrshl, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SQRSHLR instruction. @@ -16494,8 +16572,9 @@ * \param Pg The governing predicate register, P (Predicate). * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ -#define INSTR_CREATE_sqrshlr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_sqrshlr, Zdn, Pg, Zdn, Zm) +#define INSTR_CREATE_sqrshlr_sve_pred(dc, Zdn, Pg, Zm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_sqrshlr, Zdn, Pg, Zdn, Zm), \ + DR_PRED_GOVERNING) /** * Creates a SQSHL instruction. @@ -16512,8 +16591,9 @@ * \param Zm_imm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d * or an immediate */ -#define INSTR_CREATE_sqshl_sve_pred(dc, Zdn, Pg, Zm_imm) \ - instr_create_1dst_3src(dc, OP_sqshl, Zdn, Pg, Zdn, Zm_imm) +#define INSTR_CREATE_sqshl_sve_pred(dc, Zdn, Pg, Zm_imm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshl, Zdn, Pg, Zdn, Zm_imm), \ + DR_PRED_GOVERNING) /** * Creates a SQSHLR instruction. @@ -16529,7 +16609,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_sqshlr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_sqshlr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshlr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SQSUBR instruction. @@ -16545,7 +16625,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_sqsubr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_sqsubr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sqsubr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SRHADD instruction. @@ -16561,7 +16641,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_srhadd_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_srhadd, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_srhadd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SRSHL instruction. @@ -16577,7 +16657,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_srshl_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_srshl, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_srshl, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SRSHLR instruction. @@ -16593,7 +16673,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_srshlr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_srshlr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_srshlr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a SUQADD instruction. @@ -16609,7 +16689,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_suqadd_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_suqadd, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_suqadd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an UHADD instruction. @@ -16625,7 +16705,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_uhadd_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_uhadd, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uhadd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an UHSUB instruction. @@ -16641,7 +16721,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_uhsub_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_uhsub, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uhsub, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an UHSUBR instruction. @@ -16657,7 +16737,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_uhsubr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_uhsubr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uhsubr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an UMAXP instruction. @@ -16673,7 +16753,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_umaxp_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_umaxp, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_umaxp, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an UMINP instruction. @@ -16689,7 +16769,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_uminp_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_uminp, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uminp, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an UQRSHL instruction. @@ -16705,7 +16785,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_uqrshl_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_uqrshl, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uqrshl, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an UQRSHLR instruction. @@ -16720,8 +16800,9 @@ * \param Pg The governing predicate register, P (Predicate). * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ -#define INSTR_CREATE_uqrshlr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_uqrshlr, Zdn, Pg, Zdn, Zm) +#define INSTR_CREATE_uqrshlr_sve_pred(dc, Zdn, Pg, Zm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_uqrshlr, Zdn, Pg, Zdn, Zm), \ + DR_PRED_GOVERNING) /** * Creates an UQSHL instruction. @@ -16738,8 +16819,9 @@ * \param Zm_imm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d * or can be an immediate. */ -#define INSTR_CREATE_uqshl_sve_pred(dc, Zdn, Pg, Zm_imm) \ - instr_create_1dst_3src(dc, OP_uqshl, Zdn, Pg, Zdn, Zm_imm) +#define INSTR_CREATE_uqshl_sve_pred(dc, Zdn, Pg, Zm_imm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_uqshl, Zdn, Pg, Zdn, Zm_imm), \ + DR_PRED_GOVERNING) /** * Creates an UQSHLR instruction. @@ -16755,7 +16837,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_uqshlr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_uqshlr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uqshlr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an UQSUBR instruction. @@ -16771,7 +16853,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_uqsubr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_uqsubr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uqsubr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an URHADD instruction. @@ -16787,7 +16869,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_urhadd_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_urhadd, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_urhadd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an URSHL instruction. @@ -16803,7 +16885,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_urshl_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_urshl, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_urshl, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an URSHLR instruction. @@ -16819,7 +16901,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_urshlr_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_urshlr, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_urshlr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates an USQADD instruction. @@ -16835,7 +16917,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_usqadd_sve_pred(dc, Zdn, Pg, Zm) \ - instr_create_1dst_3src(dc, OP_usqadd, Zdn, Pg, Zdn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_usqadd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) /** * Creates a FCVTLT instruction. @@ -16851,7 +16933,7 @@ * \param Zn The source vector register. Can be Z.h or Z.s. */ #define INSTR_CREATE_fcvtlt_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_fcvtlt, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtlt, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FCVTNT instruction. @@ -16867,7 +16949,7 @@ * \param Zn The second source vector register. Can be Z.d or Z.s. */ #define INSTR_CREATE_fcvtnt_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_3src(dc, OP_fcvtnt, Zd, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcvtnt, Zd, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FCVTX instruction. @@ -16882,7 +16964,7 @@ * \param Zn The source vector register, Z.d. */ #define INSTR_CREATE_fcvtx_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_fcvtx, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtx, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FCVTXNT instruction. @@ -16897,7 +16979,7 @@ * \param Zn The second source vector register, Z.d. */ #define INSTR_CREATE_fcvtxnt_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_3src(dc, OP_fcvtxnt, Zd, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcvtxnt, Zd, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a FLOGB instruction. @@ -16912,7 +16994,7 @@ * \param Zn The source vector register. Can be Z.h, Z.s or Z.d. */ #define INSTR_CREATE_flogb_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_flogb, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_flogb, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a SADALP instruction. @@ -16928,7 +17010,7 @@ * \param Zn The second source vector register. Can be Z.b, Z.h or Z.s. */ #define INSTR_CREATE_sadalp_sve_pred(dc, Zda, Pg, Zn) \ - instr_create_1dst_3src(dc, OP_sadalp, Zda, Zda, Pg, Zn) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sadalp, Zda, Zda, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a SQABS instruction. @@ -16943,7 +17025,7 @@ * \param Zn The source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_sqabs_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_sqabs, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_sqabs, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a SQNEG instruction. @@ -16958,7 +17040,7 @@ * \param Zn The source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_sqneg_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_sqneg, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_sqneg, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates an UADALP instruction. @@ -16974,7 +17056,7 @@ * \param Zn The second source vector register. Can be Z.b, Z.h or Z.s. */ #define INSTR_CREATE_uadalp_sve_pred(dc, Zda, Pg, Zn) \ - instr_create_1dst_3src(dc, OP_uadalp, Zda, Zda, Pg, Zn) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uadalp, Zda, Zda, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a CADD instruction. @@ -17211,8 +17293,9 @@ * \param Pg The governing predicate register, P (Predicate). * \param imm The immediate imm. */ -#define INSTR_CREATE_sqshlu_sve_pred(dc, Zdn, Pg, imm) \ - instr_create_1dst_3src(dc, OP_sqshlu, Zdn, Pg, Zdn, imm) +#define INSTR_CREATE_sqshlu_sve_pred(dc, Zdn, Pg, imm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshlu, Zdn, Pg, Zdn, imm), \ + DR_PRED_GOVERNING) /** * Creates a SQSHRNB instruction. @@ -17306,7 +17389,7 @@ * \param imm The immediate imm1. */ #define INSTR_CREATE_srshr_sve_pred(dc, Zdn, Pg, imm) \ - instr_create_1dst_3src(dc, OP_srshr, Zdn, Pg, Zdn, imm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_srshr, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) /** * Creates a SRSRA instruction. @@ -17446,7 +17529,7 @@ * \param imm The immediate imm1. */ #define INSTR_CREATE_urshr_sve_pred(dc, Zdn, Pg, imm) \ - instr_create_1dst_3src(dc, OP_urshr, Zdn, Pg, Zdn, imm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_urshr, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) /** * Creates an URSRA instruction. @@ -17543,7 +17626,7 @@ * OPSZ_8, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_4, 0) */ #define INSTR_CREATE_ldnt1sb_sve_pred(dc, Zt, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_ldnt1sb, Zt, Zn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sb, Zt, Zn, Pg), DR_PRED_GOVERNING) /** * Creates a LDNT1SH instruction. @@ -17562,7 +17645,7 @@ * OPSZ_8, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_8, 0) */ #define INSTR_CREATE_ldnt1sh_sve_pred(dc, Zt, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_ldnt1sh, Zt, Zn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sh, Zt, Zn, Pg), DR_PRED_GOVERNING) /** * Creates a LDNT1SW instruction. @@ -17580,7 +17663,7 @@ * OPSZ_8, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_16, 0) */ #define INSTR_CREATE_ldnt1sw_sve_pred(dc, Zt, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_ldnt1sw, Zt, Zn, Pg) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sw, Zt, Zn, Pg), DR_PRED_GOVERNING) /** * Creates an UZP1 instruction. @@ -17666,7 +17749,7 @@ * \param Zm The second source vector register. Can be Z.b or Z.h. */ #define INSTR_CREATE_match_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_match, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_match, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates a NMATCH instruction. @@ -17682,7 +17765,7 @@ * \param Zm The second source vector register. Can be Z.b or Z.h. */ #define INSTR_CREATE_nmatch_sve_pred(dc, Pd, Pg, Zn, Zm) \ - instr_create_1dst_3src(dc, OP_nmatch, Pd, Pg, Zn, Zm) + INSTR_PRED(instr_create_1dst_3src(dc, OP_nmatch, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) /** * Creates an URECPE instruction. @@ -17697,7 +17780,7 @@ * \param Zn The source vector register, Z.s. */ #define INSTR_CREATE_urecpe_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_urecpe, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_urecpe, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates an URSQRTE instruction. @@ -17712,7 +17795,7 @@ * \param Zn The source vector register, Z.s. */ #define INSTR_CREATE_ursqrte_sve_pred(dc, Zd, Pg, Zn) \ - instr_create_1dst_2src(dc, OP_ursqrte, Zd, Pg, Zn) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ursqrte, Zd, Pg, Zn), DR_PRED_GOVERNING) /** * Creates a WHILEGE instruction. diff --git a/core/ir/instr.h b/core/ir/instr.h index e27bca47918..aa0f13832f9 100644 --- a/core/ir/instr.h +++ b/core/ir/instr.h @@ -516,6 +516,20 @@ instr_t * instr_set_translation_mangling_epilogue(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr); +#ifdef AARCH64 +/* Sets the DR_PRED_GOVERNING flag on the instruction to indicate that +this instruction is predicated and execution depends on the value of a +predicate register */ +void +instr_set_has_register_predication(instr_t *instr); + +/* Checks if DR_PRED_GOVERNING is set on the instruction, which indicates +it has a governing predicate register. +*/ +bool +instr_has_register_predication(instr_t *instr); +#endif + app_pc instr_compute_address_priv(instr_t *instr, priv_mcontext_t *mc); diff --git a/core/ir/instr_api.h b/core/ir/instr_api.h index 9fc140d7a36..9391eb3ed27 100644 --- a/core/ir/instr_api.h +++ b/core/ir/instr_api.h @@ -139,6 +139,9 @@ typedef enum _dr_pred_type_t { DR_PRED_AL, /**< ARM condition: 1110 Always (unconditional) */ # ifdef AARCH64 DR_PRED_NV, /**< ARM condition: 1111 Never, meaning always */ + DR_PRED_GOVERNING, /** Used for AArch64 SVE instructions with governing predicate + * registers + */ # endif # ifdef ARM DR_PRED_OP, /**< ARM condition: 1111 Part of opcode */ diff --git a/core/ir/instr_inline_api.h b/core/ir/instr_inline_api.h index 4284e901e53..8c9840bdce1 100644 --- a/core/ir/instr_inline_api.h +++ b/core/ir/instr_inline_api.h @@ -175,6 +175,13 @@ opnd_is_predicate_zero(opnd_t op) return opnd_is_predicate_reg(op) && ((op.aux.flags & DR_OPND_IS_ZERO_PREDICATE) != 0); } +INSTR_INLINE +bool +opnd_is_governing(opnd_t op) +{ + return opnd_is_predicate_reg(op) && ((op.aux.flags & DR_OPND_IS_GOVERNING) != 0); +} + # if defined(X64) || defined(ARM) # ifdef X86 # define OPND_IS_REL_ADDR(op) ((op).kind == REL_ADDR_kind) diff --git a/core/ir/instr_shared.c b/core/ir/instr_shared.c index aa0a25f0c5d..6e98a5047a0 100644 --- a/core/ir/instr_shared.c +++ b/core/ir/instr_shared.c @@ -2577,6 +2577,20 @@ instr_set_translation_mangling_epilogue(dcontext_t *dcontext, instrlist_t *ilist return instr; } +#ifdef AARCH64 +void +instr_set_has_register_predication(instr_t *instr) +{ + instr_set_predicate(instr, DR_PRED_GOVERNING); +} + +bool +instr_has_register_predication(instr_t *instr) +{ + return instr_get_predicate(instr) == DR_PRED_GOVERNING; +} +#endif + /* Emulates instruction to find the address of the index-th memory operand. * Either or both OUT variables can be NULL. */ diff --git a/core/ir/opnd_api.h b/core/ir/opnd_api.h index af79fb1d562..fa45ad33897 100644 --- a/core/ir/opnd_api.h +++ b/core/ir/opnd_api.h @@ -1011,9 +1011,9 @@ enum { DR_REG_SPSR_UND, /**< The "spsr_und" register. */ DR_REG_SPSR_FIQ, /**< The "spsr_fiq" register. */ # else - DR_REG_CPSR, /**< The "cpsr" register. */ - DR_REG_SPSR, /**< The "spsr" register. */ - DR_REG_FPSCR, /**< The "fpscr" register. */ + DR_REG_CPSR, /**< The "cpsr" register. */ + DR_REG_SPSR, /**< The "spsr" register. */ + DR_REG_FPSCR, /**< The "fpscr" register. */ # endif /* AArch32 Thread Registers */ @@ -1083,13 +1083,13 @@ enum { DR_REG_SP = DR_REG_XSP, /**< The stack pointer register. */ DR_REG_LR = DR_REG_X30, /**< The link register. */ # else - DR_REG_SP = DR_REG_R13, /**< The stack pointer register. */ - DR_REG_LR = DR_REG_R14, /**< The link register. */ - DR_REG_PC = DR_REG_R15, /**< The program counter register. */ + DR_REG_SP = DR_REG_R13, /**< The stack pointer register. */ + DR_REG_LR = DR_REG_R14, /**< The link register. */ + DR_REG_PC = DR_REG_R15, /**< The program counter register. */ # endif - DR_REG_SL = DR_REG_R10, /**< Alias for the r10 register. */ - DR_REG_FP = DR_REG_R11, /**< Alias for the r11 register. */ - DR_REG_IP = DR_REG_R12, /**< Alias for the r12 register. */ + DR_REG_SL = DR_REG_R10, /**< Alias for the r10 register. */ + DR_REG_FP = DR_REG_R11, /**< Alias for the r11 register. */ + DR_REG_IP = DR_REG_R12, /**< Alias for the r12 register. */ # ifndef AARCH64 /** Alias for cpsr register (thus this is the full cpsr, not just the apsr bits). */ DR_REG_APSR = DR_REG_CPSR, @@ -1101,8 +1101,8 @@ enum { /** Thread Pointer/ID Register, Read-Only, EL0. */ DR_REG_TPIDRRO_EL0 = DR_REG_TPIDRURO, /* ARMv7 Thread Registers */ - DR_REG_CP15_C13_2 = DR_REG_TPIDRURW, /**< User Read/Write Thread ID Register */ - DR_REG_CP15_C13_3 = DR_REG_TPIDRURO, /**< User Read-Only Thread ID Register */ + DR_REG_CP15_C13_2 = DR_REG_TPIDRURW, /**< User Read/Write Thread ID Register */ + DR_REG_CP15_C13_3 = DR_REG_TPIDRURO, /**< User Read-Only Thread ID Register */ # ifdef AARCH64 DR_REG_LAST_VALID_ENUM = DR_REG_CNTVCT_EL0, /**< Last valid register enum */ @@ -1128,7 +1128,7 @@ enum { DR_NUM_GPR_REGS = DR_REG_STOP_GPR - DR_REG_START_GPR + 1, /**< Count of GPR regs. */ # ifdef AARCH64 - DR_NUM_SIMD_VECTOR_REGS = DR_REG_Z31 - DR_REG_Z0 + 1, /**< Count of SIMD regs. */ + DR_NUM_SIMD_VECTOR_REGS = DR_REG_Z31 - DR_REG_Z0 + 1, /**< Count of SIMD regs. */ # else /* XXX: maybe we want more distinct names that provide counts for 64-bit D or 32-bit * S registers. @@ -1773,7 +1773,7 @@ typedef enum _dr_opnd_flags_t { */ DR_OPND_IS_VECTOR = 0x100, /** - * Predicate registers can either be merging, zero or neither. If one of these + * SVE predicate registers can either be merging, zero or neither. If one of these * are set then they are either a merge or zero otherwise aren't either. */ DR_OPND_IS_MERGE_PREDICATE = 0x200, @@ -1794,6 +1794,11 @@ typedef enum _dr_opnd_flags_t { * based on another register */ DR_OPND_IMPLICIT = 0x2000, + /** + * The register is a SVE governing predicate register: it is used to select + * which elements of a vector are actually read or written to in AArch64 SVE + */ + DR_OPND_IS_GOVERNING = 0x4000, } dr_opnd_flags_t; #ifdef DR_FAST_IR @@ -2569,22 +2574,28 @@ opnd_is_element_vector_reg(opnd_t opnd); DR_API INSTR_INLINE -/** Returns true iff \p opnd is a predicate register. */ +/** Returns true iff \p opnd is an SVE predicate register. */ bool opnd_is_predicate_reg(opnd_t opnd); DR_API INSTR_INLINE -/** Returns true iff \p opnd is a merging predicate register. */ +/** Returns true iff \p opnd is a n SVEmerging predicate register. */ bool opnd_is_predicate_merge(opnd_t opnd); DR_API INSTR_INLINE -/** Returns true iff \p opnd is a zeroing predicate register. */ +/** Returns true iff \p opnd is an SVE zeroing predicate register. */ bool opnd_is_predicate_zero(opnd_t opnd); +DR_API +INSTR_INLINE +/** Returns true iff \p opnd is an SVE governing predicate register. */ +bool +opnd_is_governing(opnd_t opnd); + DR_API /** * Returns true iff \p opnd uses vector indexing via a VSIB byte. This From 17adb5b8baf6370e4d86ba08a9c433332d230699 Mon Sep 17 00:00:00 2001 From: Joshua Warburton Date: Tue, 2 Jan 2024 15:45:41 +0000 Subject: [PATCH 2/3] Resolve Assad's comments Change-Id: I3f6e16f057b2fa56d4d480a6c48b3b4734635b2e --- core/ir/aarch64/instr_create_api.h | 2 +- core/ir/instr.h | 5 +++-- core/ir/opnd_api.h | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/core/ir/aarch64/instr_create_api.h b/core/ir/aarch64/instr_create_api.h index 1c4d57a1914..a43947e7b2c 100644 --- a/core/ir/aarch64/instr_create_api.h +++ b/core/ir/aarch64/instr_create_api.h @@ -8829,7 +8829,7 @@ \endverbatim * \param dc The void * dcontext used to allocate memory for the #instr_t. * \param Zd The destination vector register. Can be Z.b, Z.h, Z.s or Z.d. - * \param Pv The first source predicate register, P (Predicate). + * \param Pv The governing predicate register, P (Predicate). * \param Zn The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. * * The Zn2 parameter is derived from Zn. diff --git a/core/ir/instr.h b/core/ir/instr.h index aa0f13832f9..b33116dd505 100644 --- a/core/ir/instr.h +++ b/core/ir/instr.h @@ -518,8 +518,9 @@ instr_set_translation_mangling_epilogue(dcontext_t *dcontext, instrlist_t *ilist #ifdef AARCH64 /* Sets the DR_PRED_GOVERNING flag on the instruction to indicate that -this instruction is predicated and execution depends on the value of a -predicate register */ + * this instruction is predicated and execution depends on the value of a + * predicate register + */ void instr_set_has_register_predication(instr_t *instr); diff --git a/core/ir/opnd_api.h b/core/ir/opnd_api.h index fa45ad33897..b62a5807440 100644 --- a/core/ir/opnd_api.h +++ b/core/ir/opnd_api.h @@ -2580,7 +2580,7 @@ opnd_is_predicate_reg(opnd_t opnd); DR_API INSTR_INLINE -/** Returns true iff \p opnd is a n SVEmerging predicate register. */ +/** Returns true iff \p opnd is a n SVE merging predicate register. */ bool opnd_is_predicate_merge(opnd_t opnd); From 6228306efbcd8e0894f05f1582fe0f27534f0994 Mon Sep 17 00:00:00 2001 From: Joshua Warburton Date: Fri, 5 Jan 2024 13:52:49 +0000 Subject: [PATCH 3/3] Use PRED_MASKED instead of PRED_GOVERNING Change-Id: I784c985847ecb900f680dd12c1561dc1bc2ea428 --- core/ir/aarch64/disassemble.c | 4 +- core/ir/aarch64/instr_create_api.h | 727 ++++++++++++++--------------- core/ir/instr.h | 4 +- core/ir/instr_api.h | 30 +- core/ir/instr_shared.c | 4 +- 5 files changed, 374 insertions(+), 395 deletions(-) diff --git a/core/ir/aarch64/disassemble.c b/core/ir/aarch64/disassemble.c index 6c5cbb5ae2c..63efbb9bcb5 100644 --- a/core/ir/aarch64/disassemble.c +++ b/core/ir/aarch64/disassemble.c @@ -55,7 +55,7 @@ static const char *const pred_names[] = { "le", /* DR_PRED_LE */ "al", /* DR_PRED_AL */ "nv", /* DR_PRED_NV */ - "", /* DR_PRED_GOVERNING */ + "", /* DR_PRED_MASKED */ }; int @@ -151,7 +151,7 @@ print_opcode_name(instr_t *instr, const char *name, char *buf, size_t bufsz, size_t *sofar DR_PARAM_OUT) { if (instr_get_predicate(instr) != DR_PRED_NONE && - instr_get_predicate(instr) != DR_PRED_GOVERNING) { + instr_get_predicate(instr) != DR_PRED_MASKED) { if (instr_get_opcode(instr) == OP_bcond) { print_to_buffer(buf, bufsz, sofar, "b.%s", pred_names[instr_get_predicate(instr)]); diff --git a/core/ir/aarch64/instr_create_api.h b/core/ir/aarch64/instr_create_api.h index a43947e7b2c..36114c1a056 100644 --- a/core/ir/aarch64/instr_create_api.h +++ b/core/ir/aarch64/instr_create_api.h @@ -5271,7 +5271,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_orr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_orr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_orr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an EOR instruction. @@ -5286,7 +5286,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_eor_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_eor, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_eor, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an AND instruction. @@ -5301,7 +5301,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_and_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_and, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_and, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a BIC instruction. @@ -5316,7 +5316,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_bic_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_bic, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_bic, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a MOVPRFX instruction. @@ -5345,7 +5345,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_movprfx_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_movprfx, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_movprfx, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a SQADD instruction. @@ -5420,7 +5420,7 @@ * \param Zm The third source vector register, Z (Scalable) */ #define INSTR_CREATE_sub_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_sub, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sub, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SUB instruction. @@ -5465,7 +5465,7 @@ * \param Zm The third source vector register, Z (Scalable) */ #define INSTR_CREATE_subr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_subr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_subr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SUBR instruction. @@ -5555,7 +5555,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_add_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_add, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_add, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a ADD instruction. @@ -5604,7 +5604,7 @@ #define INSTR_CREATE_cpy_sve_shift_pred(dc, Zd, Pg, simm, shift) \ INSTR_PRED( \ instr_create_1dst_4src(dc, OP_cpy, Zd, Pg, simm, OPND_CREATE_LSL(), shift), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a CPY instruction. @@ -5623,7 +5623,7 @@ * S (Singleword, 32 bits), or D (Doubleword, 64 bits). */ #define INSTR_CREATE_cpy_sve_pred(dc, Zd, Pg, Rn_or_Vn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_cpy, Zd, Pg, Rn_or_Vn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_cpy, Zd, Pg, Rn_or_Vn), DR_PRED_MASKED) /** * Creates a PTEST instruction. @@ -5637,7 +5637,7 @@ * \param Pn The first source predicate register, P (Predicate) */ #define INSTR_CREATE_ptest_sve_pred(dc, Pg, Pn) \ - INSTR_PRED(instr_create_0dst_2src(dc, OP_ptest, Pg, Pn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_0dst_2src(dc, OP_ptest, Pg, Pn), DR_PRED_MASKED) /** * Creates a MAD instruction. @@ -5652,9 +5652,8 @@ * \param Zm The second source vector register, Z (Scalable). * \param Za The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_mad_sve_pred(dc, Zdn, Pg, Zm, Za) \ - INSTR_PRED(instr_create_1dst_4src(dc, OP_mad, Zdn, Zdn, Pg, Zm, Za), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_mad_sve_pred(dc, Zdn, Pg, Zm, Za) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_mad, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) /** * Creates a MLA instruction. @@ -5669,9 +5668,8 @@ * \param Zn The second source vector register, Z (Scalable). * \param Zm The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_mla_sve_pred(dc, Zda, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_4src(dc, OP_mla, Zda, Zda, Pg, Zn, Zm), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_mla_sve_pred(dc, Zda, Pg, Zn, Zm) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_mla, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a MLS instruction. @@ -5686,9 +5684,8 @@ * \param Zn The second source vector register, Z (Scalable). * \param Zm The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_mls_sve_pred(dc, Zda, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_4src(dc, OP_mls, Zda, Zda, Pg, Zn, Zm), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_mls_sve_pred(dc, Zda, Pg, Zn, Zm) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_mls, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a MSB instruction. @@ -5703,9 +5700,8 @@ * \param Zm The second source vector register, Z (Scalable). * \param Za The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_msb_sve_pred(dc, Zdn, Pg, Zm, Za) \ - INSTR_PRED(instr_create_1dst_4src(dc, OP_msb, Zdn, Zdn, Pg, Zm, Za), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_msb_sve_pred(dc, Zdn, Pg, Zm, Za) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_msb, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) /** * Creates a MUL instruction. @@ -5720,7 +5716,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_mul_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_mul, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_mul, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a MUL instruction. @@ -5749,7 +5745,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_smulh_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_smulh, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_smulh, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an UMULH instruction. @@ -5764,7 +5760,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_umulh_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_umulh, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_umulh, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FEXPA instruction. @@ -5837,7 +5833,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_abs_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_abs, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_abs, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a CNOT instruction. @@ -5852,7 +5848,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_cnot_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_cnot, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_cnot, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a NEG instruction. @@ -5867,7 +5863,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_neg_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_neg, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_neg, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a SABD instruction. @@ -5882,7 +5878,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_sabd_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_sabd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sabd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SMAX instruction. @@ -5897,7 +5893,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_smax_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_smax, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_smax, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SMAX instruction. @@ -5926,7 +5922,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_smin_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_smin, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_smin, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SMIN instruction. @@ -5955,7 +5951,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_uabd_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_uabd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uabd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FACGE instruction. @@ -5971,7 +5967,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_facge_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_facge, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_facge, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a FACGT instruction. @@ -5987,7 +5983,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_facgt_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_facgt, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_facgt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a SDIV instruction. @@ -6002,7 +5998,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_sdiv_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_sdiv, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sdiv, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SDIVR instruction. @@ -6017,7 +6013,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_sdivr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_sdivr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sdivr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an UDIV instruction. @@ -6032,7 +6028,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_udiv_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_udiv, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_udiv, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an UDIVR instruction. @@ -6047,7 +6043,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_udivr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_udivr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_udivr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an UMAX instruction. @@ -6062,7 +6058,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_umax_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_umax, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_umax, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an UMAX instruction. @@ -6091,7 +6087,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_umin_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_umin, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_umin, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an UMIN instruction. @@ -6120,7 +6116,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_sxtb_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_sxtb, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_sxtb, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a SXTH instruction. @@ -6135,7 +6131,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_sxth_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_sxth, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_sxth, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a SXTW instruction. @@ -6150,7 +6146,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_sxtw_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_sxtw, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_sxtw, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates an UXTB instruction. @@ -6165,7 +6161,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_uxtb_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_uxtb, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_uxtb, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates an UXTH instruction. @@ -6180,7 +6176,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_uxth_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_uxth, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_uxth, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates an UXTW instruction. @@ -6195,7 +6191,7 @@ * \param Zn The source vector register, Z (Scalable) */ #define INSTR_CREATE_uxtw_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_uxtw, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_uxtw, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FCMEQ instruction. @@ -6212,7 +6208,7 @@ #define INSTR_CREATE_fcmeq_sve_zero_pred(dc, Pd, Pg, Zn) \ INSTR_PRED( \ instr_create_1dst_3src(dc, OP_fcmeq, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a FCMEQ instruction. @@ -6228,7 +6224,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_fcmeq_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmeq, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmeq, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a FCMGE instruction. @@ -6245,7 +6241,7 @@ #define INSTR_CREATE_fcmge_sve_zero_pred(dc, Pd, Pg, Zn) \ INSTR_PRED( \ instr_create_1dst_3src(dc, OP_fcmge, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a FCMGE instruction. @@ -6261,7 +6257,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_fcmge_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmge, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmge, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a FCMGT instruction. @@ -6278,7 +6274,7 @@ #define INSTR_CREATE_fcmgt_sve_zero_pred(dc, Pd, Pg, Zn) \ INSTR_PRED( \ instr_create_1dst_3src(dc, OP_fcmgt, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a FCMGT instruction. @@ -6294,7 +6290,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_fcmgt_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmgt, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmgt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a FCMLE instruction. @@ -6311,7 +6307,7 @@ #define INSTR_CREATE_fcmle_sve_zero_pred(dc, Pd, Pg, Zn) \ INSTR_PRED( \ instr_create_1dst_3src(dc, OP_fcmle, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a FCMLT instruction. @@ -6328,7 +6324,7 @@ #define INSTR_CREATE_fcmlt_sve_zero_pred(dc, Pd, Pg, Zn) \ INSTR_PRED( \ instr_create_1dst_3src(dc, OP_fcmlt, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a FCMNE instruction. @@ -6345,7 +6341,7 @@ #define INSTR_CREATE_fcmne_sve_zero_pred(dc, Pd, Pg, Zn) \ INSTR_PRED( \ instr_create_1dst_3src(dc, OP_fcmne, Pd, Pg, Zn, opnd_create_immed_float(0.0)), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a FCMNE instruction. @@ -6361,7 +6357,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_fcmne_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmne, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmne, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a FCMUO instruction. @@ -6377,7 +6373,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_fcmuo_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmuo, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmuo, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a FCMLE instruction. @@ -6393,7 +6389,7 @@ * \param Zn The second source vector register, Z (Scalable) */ #define INSTR_CREATE_fcmle_sve_pred(dc, Pd, Pg, Zm, Zn) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmle, Pd, Pg, Zm, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmle, Pd, Pg, Zm, Zn), DR_PRED_MASKED) /** * Creates a FCMLT instruction. @@ -6409,7 +6405,7 @@ * \param Zn The second source vector register, Z (Scalable) */ #define INSTR_CREATE_fcmlt_sve_pred(dc, Pd, Pg, Zm, Zn) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmlt, Pd, Pg, Zm, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcmlt, Pd, Pg, Zm, Zn), DR_PRED_MASKED) /** * Creates a CMPEQ instruction. @@ -6425,7 +6421,7 @@ * \param simm The signed immediate imm */ #define INSTR_CREATE_cmpeq_sve_pred_simm(dc, Pd, Pg, Zn, simm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, simm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, simm), DR_PRED_MASKED) /** * Creates a CMPEQ instruction. @@ -6442,7 +6438,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmpeq_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpeq, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a CMPGE instruction. @@ -6458,7 +6454,7 @@ * \param simm The signed immediate imm */ #define INSTR_CREATE_cmpge_sve_pred_simm(dc, Pd, Pg, Zn, simm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, simm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, simm), DR_PRED_MASKED) /** * Creates a CMPGE instruction. @@ -6475,7 +6471,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmpge_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpge, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a CMPGT instruction. @@ -6491,7 +6487,7 @@ * \param simm The signed immediate imm */ #define INSTR_CREATE_cmpgt_sve_pred_simm(dc, Pd, Pg, Zn, simm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, simm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, simm), DR_PRED_MASKED) /** * Creates a CMPGT instruction. @@ -6508,7 +6504,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmpgt_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpgt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a CMPHI instruction. @@ -6524,7 +6520,7 @@ * \param imm The immediate imm */ #define INSTR_CREATE_cmphi_sve_pred_imm(dc, Pd, Pg, Zn, imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, imm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, imm), DR_PRED_MASKED) /** * Creates a CMPHI instruction. @@ -6541,7 +6537,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmphi_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphi, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a CMPHS instruction. @@ -6557,7 +6553,7 @@ * \param imm The immediate imm */ #define INSTR_CREATE_cmphs_sve_pred_imm(dc, Pd, Pg, Zn, imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, imm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, imm), DR_PRED_MASKED) /** * Creates a CMPHS instruction. @@ -6574,7 +6570,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmphs_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmphs, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a CMPLE instruction. @@ -6590,7 +6586,7 @@ * \param simm The signed immediate imm */ #define INSTR_CREATE_cmple_sve_pred_simm(dc, Pd, Pg, Zn, simm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, simm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, simm), DR_PRED_MASKED) /** * Creates a CMPLE instruction. @@ -6606,7 +6602,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmple_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmple, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a CMPLO instruction. @@ -6622,7 +6618,7 @@ * \param imm The immediate imm */ #define INSTR_CREATE_cmplo_sve_pred_imm(dc, Pd, Pg, Zn, imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, imm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, imm), DR_PRED_MASKED) /** * Creates a CMPLO instruction. @@ -6638,7 +6634,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmplo_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplo, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a CMPLS instruction. @@ -6654,7 +6650,7 @@ * \param imm The immediate imm */ #define INSTR_CREATE_cmpls_sve_pred_imm(dc, Pd, Pg, Zn, imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, imm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, imm), DR_PRED_MASKED) /** * Creates a CMPLS instruction. @@ -6670,7 +6666,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmpls_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpls, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a CMPLT instruction. @@ -6686,7 +6682,7 @@ * \param simm The signed immediate imm */ #define INSTR_CREATE_cmplt_sve_pred_simm(dc, Pd, Pg, Zn, simm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, simm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, simm), DR_PRED_MASKED) /** * Creates a CMPLT instruction. @@ -6702,7 +6698,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmplt_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmplt, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a CMPNE instruction. @@ -6718,7 +6714,7 @@ * \param simm The signed immediate imm */ #define INSTR_CREATE_cmpne_sve_pred_simm(dc, Pd, Pg, Zn, simm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, simm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, simm), DR_PRED_MASKED) /** * Creates a CMPNE instruction. @@ -6735,7 +6731,7 @@ * \param Zm The second source vector register, Z (Scalable) */ #define INSTR_CREATE_cmpne_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_cmpne, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a SETFFR instruction. @@ -6772,7 +6768,7 @@ * \param Pg The governing predicate register, P (Predicate) */ #define INSTR_CREATE_rdffr_sve_pred(dc, Pd, Pg) \ - INSTR_PRED(instr_create_1dst_1src(dc, OP_rdffr, Pd, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_1src(dc, OP_rdffr, Pd, Pg), DR_PRED_MASKED) /** * Creates a RDFFRS instruction. @@ -6786,7 +6782,7 @@ * \param Pg The governing predicate register, P (Predicate) */ #define INSTR_CREATE_rdffrs_sve_pred(dc, Pd, Pg) \ - INSTR_PRED(instr_create_1dst_1src(dc, OP_rdffrs, Pd, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_1src(dc, OP_rdffrs, Pd, Pg), DR_PRED_MASKED) /** * Creates a WRFFR instruction. @@ -6813,7 +6809,7 @@ * \param Pn The source predicate register, P (Predicate). */ #define INSTR_CREATE_cntp_sve_pred(dc, Rd, Pg, Pn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_cntp, Rd, Pg, Pn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_cntp, Rd, Pg, Pn), DR_PRED_MASKED) /** * Creates a DECP instruction. @@ -7111,7 +7107,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_and_sve_pred_b(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_and, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_and, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates an AND instruction. @@ -7142,7 +7138,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_ands_sve_pred(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates a BIC instruction. @@ -7158,7 +7154,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_bic_sve_pred_b(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_bic, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_bic, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates a BIC instruction. @@ -7189,7 +7185,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_bics_sve_pred(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_bics, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_bics, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates an EOR instruction. @@ -7205,7 +7201,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_eor_sve_pred_b(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_eor, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_eor, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates a NOT instruction. @@ -7252,7 +7248,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_eors_sve_pred(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_eors, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_eors, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates a NAND instruction. @@ -7268,7 +7264,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_nand_sve_pred(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_nand, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_nand, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates a NANDS instruction. @@ -7284,7 +7280,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_nands_sve_pred(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_nands, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_nands, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates a NOR instruction. @@ -7300,7 +7296,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_nor_sve_pred(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_nor, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_nor, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates a NORS instruction. @@ -7316,7 +7312,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_nors_sve_pred(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_nors, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_nors, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates a NOT instruction. @@ -7331,7 +7327,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_not_sve_pred_vec(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_not, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_not, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates an ORN instruction. @@ -7347,7 +7343,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_orn_sve_pred(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_orn, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_orn, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates an ORNS instruction. @@ -7363,7 +7359,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_orns_sve_pred(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_orns, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_orns, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates an ORR instruction. @@ -7379,7 +7375,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_orr_sve_pred_b(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_orr, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_orr, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates an ORR instruction. @@ -7410,7 +7406,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_orrs_sve_pred(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_orrs, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_orrs, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates a CLASTA instruction. @@ -7426,7 +7422,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_clasta_sve_scalar(dc, Rdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Rdn, Pg, Rdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Rdn, Pg, Rdn, Zm), DR_PRED_MASKED) /** * Creates a CLASTA instruction. @@ -7442,7 +7438,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_clasta_sve_simd_fp(dc, Vdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Vdn, Pg, Vdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Vdn, Pg, Vdn, Zm), DR_PRED_MASKED) /** * Creates a CLASTA instruction. @@ -7457,7 +7453,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_clasta_sve_vector(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_clasta, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a CLASTB instruction. @@ -7473,7 +7469,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_clastb_sve_scalar(dc, Rdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Rdn, Pg, Rdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Rdn, Pg, Rdn, Zm), DR_PRED_MASKED) /** * Creates a CLASTB instruction. @@ -7489,7 +7485,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_clastb_sve_simd_fp(dc, Vdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Vdn, Pg, Vdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Vdn, Pg, Vdn, Zm), DR_PRED_MASKED) /** * Creates a CLASTB instruction. @@ -7504,7 +7500,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_clastb_sve_vector(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_clastb, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a LASTA instruction. @@ -7520,7 +7516,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_lasta_sve_scalar(dc, Rd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_lasta, Rd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_lasta, Rd, Pg, Zn), DR_PRED_MASKED) /** * Creates a LASTA instruction. @@ -7536,7 +7532,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_lasta_sve_simd_fp(dc, Vd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_lasta, Vd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_lasta, Vd, Pg, Zn), DR_PRED_MASKED) /** * Creates a LASTB instruction. @@ -7552,7 +7548,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_lastb_sve_scalar(dc, Rd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_lastb, Rd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_lastb, Rd, Pg, Zn), DR_PRED_MASKED) /** * Creates a LASTB instruction. @@ -7568,7 +7564,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_lastb_sve_simd_fp(dc, Vd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_lastb, Vd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_lastb, Vd, Pg, Zn), DR_PRED_MASKED) /** * Creates a CNT instruction. @@ -7583,7 +7579,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_cnt_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a CNTB instruction. @@ -8468,7 +8464,7 @@ * \param Pn The source predicate register, P (Predicate). */ #define INSTR_CREATE_brka_sve_pred(dc, Pd, Pg, Pn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_brka, Pd, Pg, Pn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_brka, Pd, Pg, Pn), DR_PRED_MASKED) /** * Creates a BRKAS instruction. @@ -8483,7 +8479,7 @@ * \param Pn The source predicate register, P (Predicate). */ #define INSTR_CREATE_brkas_sve_pred(dc, Pd, Pg, Pn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_brkas, Pd, Pg, Pn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_brkas, Pd, Pg, Pn), DR_PRED_MASKED) /** * Creates a BRKB instruction. @@ -8498,7 +8494,7 @@ * \param Pn The source predicate register, P (Predicate). */ #define INSTR_CREATE_brkb_sve_pred(dc, Pd, Pg, Pn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_brkb, Pd, Pg, Pn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_brkb, Pd, Pg, Pn), DR_PRED_MASKED) /** * Creates a BRKBS instruction. @@ -8513,7 +8509,7 @@ * \param Pn The source predicate register, P (Predicate). */ #define INSTR_CREATE_brkbs_sve_pred(dc, Pd, Pg, Pn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_brkbs, Pd, Pg, Pn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_brkbs, Pd, Pg, Pn), DR_PRED_MASKED) /** * Creates a BRKN instruction. @@ -8529,7 +8525,7 @@ * \param Pn The first source predicate register, P (Predicate). */ #define INSTR_CREATE_brkn_sve_pred(dc, Pdm, Pg, Pn) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_brkn, Pdm, Pg, Pn, Pdm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_brkn, Pdm, Pg, Pn, Pdm), DR_PRED_MASKED) /** * Creates a BRKNS instruction. @@ -8545,7 +8541,7 @@ * \param Pn The first source predicate register, P (Predicate). */ #define INSTR_CREATE_brkns_sve_pred(dc, Pdm, Pg, Pn) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_brkns, Pdm, Pg, Pn, Pdm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_brkns, Pdm, Pg, Pn, Pdm), DR_PRED_MASKED) /** * Creates a BRKPA instruction. @@ -8561,7 +8557,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_brkpa_sve_pred(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpa, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpa, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates a BRKPAS instruction. @@ -8577,7 +8573,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_brkpas_sve_pred(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpas, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpas, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates a BRKPB instruction. @@ -8593,7 +8589,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_brkpb_sve_pred(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpb, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpb, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates a BRKPBS instruction. @@ -8609,7 +8605,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_brkpbs_sve_pred(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpbs, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_brkpbs, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates a WHILELE instruction. @@ -8818,7 +8814,7 @@ * \param Zm The last source vector register, Z (Scalable). */ #define INSTR_CREATE_splice_sve_des(dc, Zdn, Pv, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_splice, Zdn, Pv, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_splice, Zdn, Pv, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SPLICE instruction. @@ -8837,7 +8833,7 @@ #define INSTR_CREATE_splice_sve_con(dc, Zd, Pv, Zn) \ INSTR_PRED(instr_create_1dst_3src(dc, OP_splice, Zd, Pv, Zn, \ opnd_create_increment_reg(Zn, 1)), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a REV instruction. @@ -8878,7 +8874,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_revb_sve(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_revb, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_revb, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a REVH instruction. @@ -8893,7 +8889,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_revh_sve(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_revh, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_revh, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a REVW instruction. @@ -8908,7 +8904,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_revw_sve(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_revw, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_revw, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a COMPACT instruction. @@ -8923,7 +8919,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_compact_sve(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_compact, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_compact, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a PUNPKHI instruction. @@ -9240,7 +9236,7 @@ * \param Pg The governing predicate register, P (Predicate). */ #define INSTR_CREATE_pfirst_sve(dc, Pdn, Pg) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_pfirst, Pdn, Pg, Pdn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_pfirst, Pdn, Pg, Pdn), DR_PRED_MASKED) /** * Creates a SEL instruction. @@ -9256,7 +9252,7 @@ * \param Pm The second source predicate register, P (Predicate). */ #define INSTR_CREATE_sel_sve_pred(dc, Pd, Pg, Pn, Pm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_sel, Pd, Pg, Pn, Pm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sel, Pd, Pg, Pn, Pm), DR_PRED_MASKED) /** * Creates a SEL instruction. @@ -9272,7 +9268,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_sel_sve_vector(dc, Zd, Pv, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_sel, Zd, Pv, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sel, Zd, Pv, Zn, Zm), DR_PRED_MASKED) /** * Creates an MOV instruction. @@ -9289,7 +9285,7 @@ INSTR_PRED( \ instr_create_1dst_3src( \ dc, OP_orr, Pd, opnd_create_predicate_reg(opnd_get_reg(Pn), false), Pn, Pn), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates an MOVS instruction. @@ -9304,7 +9300,7 @@ * \param Pn The first source predicate register, P (Predicate). */ #define INSTR_CREATE_movs_sve_pred(dc, Pd, Pg, Pn) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pn), DR_PRED_MASKED) /** * Creates a PTRUE instruction. @@ -9362,7 +9358,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_asr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an ASR instruction. @@ -9377,7 +9373,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_asr_sve_pred_wide(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_asr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an ASR instruction. @@ -9407,7 +9403,7 @@ * \param imm The immediate imm, one indexed. */ #define INSTR_CREATE_asrd_sve_pred(dc, Zdn, Pg, imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_asrd, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_asrd, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) /** * Creates an ASRR instruction. @@ -9422,7 +9418,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_asrr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_asrr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_asrr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a CLS instruction. @@ -9437,7 +9433,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_cls_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_cls, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_cls, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a CLZ instruction. @@ -9452,7 +9448,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_clz_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_clz, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_clz, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a CNT instruction. @@ -9467,7 +9463,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_cnt_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_cnt, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a LSL instruction. @@ -9497,7 +9493,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_lsl_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_lsl, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_lsl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a LSL instruction. @@ -9512,7 +9508,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_lsl_sve_pred_wide(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_lsl, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_lsl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a LSL instruction. @@ -9542,7 +9538,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_lslr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_lslr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_lslr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a LSR instruction. @@ -9572,7 +9568,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_lsr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_lsr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_lsr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a LSR instruction. @@ -9587,7 +9583,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_lsr_sve_pred_wide(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_lsr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_lsr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a LSR instruction. @@ -9617,7 +9613,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_lsrr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_lsrr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_lsrr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a RBIT instruction. @@ -9632,7 +9628,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_rbit_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_rbit, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_rbit, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates an ANDV instruction. @@ -9649,7 +9645,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_andv_sve_pred(dc, Vd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_andv, Vd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_andv, Vd, Pg, Zn), DR_PRED_MASKED) /** * Creates an EORV instruction. @@ -9666,7 +9662,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_eorv_sve_pred(dc, Vd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_eorv, Vd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_eorv, Vd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FADDA instruction. @@ -9683,7 +9679,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fadda_sve_pred(dc, Vdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fadda, Vdn, Pg, Vdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fadda, Vdn, Pg, Vdn, Zm), DR_PRED_MASKED) /** * Creates a FADDV instruction. @@ -9699,7 +9695,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_faddv_sve_pred(dc, Vd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_faddv, Vd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_faddv, Vd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FMAXNMV instruction. @@ -9715,7 +9711,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fmaxnmv_sve_pred(dc, Vd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_fmaxnmv, Vd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fmaxnmv, Vd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FMAXV instruction. @@ -9731,7 +9727,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fmaxv_sve_pred(dc, Vd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_fmaxv, Vd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fmaxv, Vd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FMINNMV instruction. @@ -9747,7 +9743,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fminnmv_sve_pred(dc, Vd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_fminnmv, Vd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fminnmv, Vd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FMINV instruction. @@ -9763,7 +9759,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fminv_sve_pred(dc, Vd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_fminv, Vd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fminv, Vd, Pg, Zn), DR_PRED_MASKED) /** * Creates an ORV instruction. @@ -9780,7 +9776,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_orv_sve_pred(dc, Vd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_orv, Vd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_orv, Vd, Pg, Zn), DR_PRED_MASKED) /** * Creates a SADDV instruction. @@ -9795,7 +9791,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_saddv_sve_pred(dc, Vd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_saddv, Vd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_saddv, Vd, Pg, Zn), DR_PRED_MASKED) /** * Creates a SMAXV instruction. @@ -9812,7 +9808,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_smaxv_sve_pred(dc, Vd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_smaxv, Vd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_smaxv, Vd, Pg, Zn), DR_PRED_MASKED) /** * Creates a SMINV instruction. @@ -9829,7 +9825,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_sminv_sve_pred(dc, Vd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_sminv, Vd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_sminv, Vd, Pg, Zn), DR_PRED_MASKED) /** * Creates an UADDV instruction. @@ -9844,7 +9840,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_uaddv_sve_pred(dc, Vd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_uaddv, Vd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_uaddv, Vd, Pg, Zn), DR_PRED_MASKED) /** * Creates an UMAXV instruction. @@ -9861,7 +9857,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_umaxv_sve_pred(dc, Vd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_umaxv, Vd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_umaxv, Vd, Pg, Zn), DR_PRED_MASKED) /** * Creates an UMINV instruction. @@ -9878,7 +9874,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_uminv_sve_pred(dc, Vd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_uminv, Vd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_uminv, Vd, Pg, Zn), DR_PRED_MASKED) /* * Creates a FCPY instruction. @@ -9889,7 +9885,7 @@ * \param imm The floating-point immediate value to be copied. */ #define INSTR_CREATE_fcpy_sve_pred(dc, Zd, Pg, imm) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_fcpy, Zd, Pg, imm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fcpy, Zd, Pg, imm), DR_PRED_MASKED) /** * Creates a FDUP instruction. @@ -9923,7 +9919,7 @@ * OPSZ_1) */ #define INSTR_CREATE_ld1rb_sve(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rb, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rb, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LD1RH instruction. @@ -9943,7 +9939,7 @@ * OPSZ_2) */ #define INSTR_CREATE_ld1rh_sve(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rh, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rh, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LD1RW instruction. @@ -9962,7 +9958,7 @@ * OPSZ_4) */ #define INSTR_CREATE_ld1rw_sve(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rw, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rw, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LD1RD instruction. @@ -9980,7 +9976,7 @@ * OPSZ_8) */ #define INSTR_CREATE_ld1rd_sve(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rd, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rd, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LD1RSB instruction. @@ -10000,7 +9996,7 @@ * OPSZ_1) */ #define INSTR_CREATE_ld1rsb_sve(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsb, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsb, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LD1RSH instruction. @@ -10019,7 +10015,7 @@ * OPSZ_2) */ #define INSTR_CREATE_ld1rsh_sve(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsh, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsh, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LD1RSW instruction. @@ -10037,7 +10033,7 @@ * OPSZ_4) */ #define INSTR_CREATE_ld1rsw_sve(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsw, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rsw, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates an INDEX instruction. @@ -10079,7 +10075,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fcvt_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvt, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvt, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FCVTZS instruction. @@ -10100,7 +10096,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fcvtzs_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtzs, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtzs, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FCVTZU instruction. @@ -10121,7 +10117,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fcvtzu_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtzu, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtzu, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FRINTA instruction. @@ -10136,7 +10132,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_frinta_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_frinta, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_frinta, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FRINTI instruction. @@ -10151,7 +10147,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_frinti_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_frinti, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_frinti, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FRINTM instruction. @@ -10166,7 +10162,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_frintm_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_frintm, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_frintm, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FRINTN instruction. @@ -10181,7 +10177,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_frintn_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_frintn, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_frintn, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FRINTP instruction. @@ -10196,7 +10192,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_frintp_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_frintp, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_frintp, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FRINTX instruction. @@ -10211,7 +10207,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_frintx_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_frintx, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_frintx, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FRINTZ instruction. @@ -10226,7 +10222,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_frintz_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_frintz, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_frintz, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a SCVTF instruction. @@ -10247,7 +10243,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_scvtf_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_scvtf, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_scvtf, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates an UCVTF instruction. @@ -10268,7 +10264,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_ucvtf_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ucvtf, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ucvtf, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a CTERMEQ instruction. @@ -10313,7 +10309,7 @@ * \param Pv The first source predicate register, P (Predicate). */ #define INSTR_CREATE_pnext_sve(dc, Pdn, Pv) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_pnext, Pdn, Pv, Pdn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_pnext, Pdn, Pv, Pdn), DR_PRED_MASKED) /** * Creates a FABD instruction. @@ -10328,7 +10324,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fabd_sve(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fabd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fabd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FABS instruction. @@ -10343,7 +10339,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fabs_sve(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_fabs, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fabs, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FDIV instruction. @@ -10358,7 +10354,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fdiv_sve(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fdiv, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fdiv, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FDIVR instruction. @@ -10373,7 +10369,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fdivr_sve(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fdivr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fdivr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FMAD instruction. @@ -10388,9 +10384,8 @@ * \param Zm The second source vector register, Z (Scalable). * \param Za The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_fmad_sve(dc, Zdn, Pg, Zm, Za) \ - INSTR_PRED(instr_create_1dst_4src(dc, OP_fmad, Zdn, Zdn, Pg, Zm, Za), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_fmad_sve(dc, Zdn, Pg, Zm, Za) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fmad, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) /** * Creates a FMULX instruction. @@ -10405,7 +10400,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fmulx_sve(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fmulx, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmulx, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FNEG instruction. @@ -10420,7 +10415,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fneg_sve(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_fneg, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fneg, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FNMAD instruction. @@ -10435,9 +10430,8 @@ * \param Zm The second source vector register, Z (Scalable). * \param Za The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_fnmad_sve(dc, Zdn, Pg, Zm, Za) \ - INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmad, Zdn, Zdn, Pg, Zm, Za), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_fnmad_sve(dc, Zdn, Pg, Zm, Za) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmad, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) /** * Creates a FNMLA instruction. @@ -10452,9 +10446,8 @@ * \param Zn The second source vector register, Z (Scalable). * \param Zm The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_fnmla_sve(dc, Zda, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmla, Zda, Zda, Pg, Zn, Zm), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_fnmla_sve(dc, Zda, Pg, Zn, Zm) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmla, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a FNMLS instruction. @@ -10469,9 +10462,8 @@ * \param Zn The second source vector register, Z (Scalable). * \param Zm The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_fnmls_sve(dc, Zda, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmls, Zda, Zda, Pg, Zn, Zm), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_fnmls_sve(dc, Zda, Pg, Zn, Zm) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmls, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a FNMSB instruction. @@ -10486,9 +10478,8 @@ * \param Zm The second source vector register, Z (Scalable). * \param Za The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_fnmsb_sve_pred(dc, Zdn, Pg, Zm, Za) \ - INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmsb, Zdn, Zdn, Pg, Zm, Za), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_fnmsb_sve_pred(dc, Zdn, Pg, Zm, Za) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fnmsb, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) /** * Creates a FRECPE instruction. @@ -10531,7 +10522,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_frecpx_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_frecpx, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_frecpx, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FRSQRTE instruction. @@ -10575,7 +10566,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fscale_sve(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fscale, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fscale, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FSQRT instruction. @@ -10590,7 +10581,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_fsqrt_sve(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_fsqrt, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fsqrt, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FADD instruction. @@ -10605,7 +10596,7 @@ * \param imm Floating point constant, either 0.5 or 1.0. */ #define INSTR_CREATE_fadd_sve(dc, Zdn, Pg, imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) /** * Creates a FADD instruction. @@ -10620,7 +10611,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fadd_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FADD instruction. @@ -10650,7 +10641,7 @@ * \param imm Floating point constant, either 0.5 or 1.0. */ #define INSTR_CREATE_fsub_sve(dc, Zdn, Pg, imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fsub, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fsub, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) /** * Creates a FSUB instruction. @@ -10665,7 +10656,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fsub_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fsub, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fsub, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FSUB instruction. @@ -10695,7 +10686,7 @@ * \param imm Floating point constant, either 0.5 or 1.0. */ #define INSTR_CREATE_fsubr_sve(dc, Zdn, Pg, imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fsubr, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fsubr, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) /** * Creates a FSUBR instruction. @@ -10710,7 +10701,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fsubr_sve_vector(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fsubr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FMAX instruction. @@ -10725,7 +10716,7 @@ * \param imm Floating point constant, either 0.0 or 1.0. */ #define INSTR_CREATE_fmax_sve(dc, Zdn, Pg, imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) /** * Creates a FMAX instruction. @@ -10740,7 +10731,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fmax_sve_vector(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmax, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FMAXNM instruction. @@ -10754,9 +10745,8 @@ * \param Pg The governing predicate register, P (Predicate). * \param imm Floating point constant, either 0.0 or 1.0. */ -#define INSTR_CREATE_fmaxnm_sve(dc, Zdn, Pg, imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, imm), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_fmaxnm_sve(dc, Zdn, Pg, imm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) /** * Creates a FMAXNM instruction. @@ -10771,7 +10761,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fmaxnm_sve_vector(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnm, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FMIN instruction. @@ -10786,7 +10776,7 @@ * \param imm Floating point constant, either 0.0 or 1.0. */ #define INSTR_CREATE_fmin_sve(dc, Zdn, Pg, imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) /** * Creates a FMIN instruction. @@ -10801,7 +10791,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fmin_sve_vector(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmin, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FMINNM instruction. @@ -10815,9 +10805,8 @@ * \param Pg The governing predicate register, P (Predicate). * \param imm Floating point constant, either 0.0 or 1.0. */ -#define INSTR_CREATE_fminnm_sve(dc, Zdn, Pg, imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, imm), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_fminnm_sve(dc, Zdn, Pg, imm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) /** * Creates a FMINNM instruction. @@ -10832,7 +10821,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fminnm_sve_vector(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnm, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FMLA instruction. @@ -10847,9 +10836,8 @@ * \param Zn The first source vector register, Z (Scalable). * \param Zm The second source vector register, Z (Scalable). */ -#define INSTR_CREATE_fmla_sve_vector(dc, Zda, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_4src(dc, OP_fmla, Zda, Zda, Pg, Zn, Zm), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_fmla_sve_vector(dc, Zda, Pg, Zn, Zm) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fmla, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a FMLA instruction. @@ -10882,9 +10870,8 @@ * \param Zn The first source vector register, Z (Scalable). * \param Zm The second source vector register, Z (Scalable). */ -#define INSTR_CREATE_fmls_sve_vector(dc, Zda, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_4src(dc, OP_fmls, Zda, Zda, Pg, Zn, Zm), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_fmls_sve_vector(dc, Zda, Pg, Zn, Zm) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fmls, Zda, Zda, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a FMLS instruction. @@ -10917,9 +10904,8 @@ * \param Zm The second source vector register, Z (Scalable). * \param Za The third source vector register, Z (Scalable). */ -#define INSTR_CREATE_fmsb_sve(dc, Zdn, Pg, Zm, Za) \ - INSTR_PRED(instr_create_1dst_4src(dc, OP_fmsb, Zdn, Zdn, Pg, Zm, Za), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_fmsb_sve(dc, Zdn, Pg, Zm, Za) \ + INSTR_PRED(instr_create_1dst_4src(dc, OP_fmsb, Zdn, Zdn, Pg, Zm, Za), DR_PRED_MASKED) /** * Creates a FMUL instruction. @@ -10934,7 +10920,7 @@ * \param imm Floating point constant, either 0.5 or 2.0. */ #define INSTR_CREATE_fmul_sve(dc, Zdn, Pg, imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) /** * Creates a FMUL instruction. @@ -10949,7 +10935,7 @@ * \param Zm The second source vector register, Z (Scalable). */ #define INSTR_CREATE_fmul_sve_pred_vector(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmul, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FMUL instruction. @@ -11066,7 +11052,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 32), 0) */ #define INSTR_CREATE_ldff1b_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1b, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1b, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LDFF1D instruction. @@ -11105,7 +11091,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 16), 0) */ #define INSTR_CREATE_ldff1d_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1d, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1d, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LDFF1H instruction. @@ -11158,7 +11144,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 16), 0) */ #define INSTR_CREATE_ldff1h_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1h, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1h, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LDFF1SB instruction. @@ -11198,7 +11184,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 32), 0) */ #define INSTR_CREATE_ldff1sb_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sb, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sb, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LDFF1SH instruction. @@ -11250,7 +11236,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 16), 0) */ #define INSTR_CREATE_ldff1sh_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sh, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sh, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LDFF1SW instruction. @@ -11297,7 +11283,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 8), 0) */ #define INSTR_CREATE_ldff1sw_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sw, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1sw, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LDFF1W instruction. @@ -11325,7 +11311,7 @@ * DR_EXTEND_UXTX, 0, imm5, 0, opnd_size_from_bytes(dr_get_sve_vl() / 16), 0) */ #define INSTR_CREATE_ldff1w_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1w, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldff1w, Zt, Rn, Pg), DR_PRED_MASKED) /** @@ -11343,7 +11329,7 @@ */ #define INSTR_CREATE_fcadd_sve_pred(dc, Zdn, Pg, Zm, rot) \ INSTR_PRED(instr_create_1dst_4src(dc, OP_fcadd, Zdn, Pg, Zdn, Zm, rot), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a FCMLA instruction. @@ -11361,7 +11347,7 @@ */ #define INSTR_CREATE_fcmla_sve_vector(dc, Zda, Pg, Zn, Zm, rot) \ INSTR_PRED(instr_create_1dst_5src(dc, OP_fcmla, Zda, Zda, Pg, Zn, Zm, rot), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a FCMLA instruction. @@ -11437,7 +11423,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 32), 0) */ #define INSTR_CREATE_ld1b_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1b, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1b, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LD1ROB instruction. @@ -11455,7 +11441,7 @@ * DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1) */ #define INSTR_CREATE_ld1rob_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rob, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rob, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LD1RQB instruction. @@ -11478,7 +11464,7 @@ * Xn, Xm, DR_EXTEND_UXTX, false, 0, 0, OPSZ_16, 0) */ #define INSTR_CREATE_ld1rqb_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqb, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqb, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LD1RQH instruction. @@ -11501,7 +11487,7 @@ * Xn, Xm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_16, 1) */ #define INSTR_CREATE_ld1rqh_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqh, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqh, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LD1RQW instruction. @@ -11524,7 +11510,7 @@ * Xn, Xm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_16, 2) */ #define INSTR_CREATE_ld1rqw_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqw, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqw, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LD1RQD instruction. @@ -11547,7 +11533,7 @@ * Xn, Xm, DR_EXTEND_UXTX, true, 0, 0, OPSZ_16, 3) */ #define INSTR_CREATE_ld1rqd_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqd, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1rqd, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LD1SB instruction. @@ -11600,7 +11586,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 32), 0) */ #define INSTR_CREATE_ld1sb_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sb, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sb, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LDNT1B instruction. @@ -11627,7 +11613,7 @@ * DR_EXTEND_UXTX, 0, 0, 0, OPSZ_1) */ #define INSTR_CREATE_ldnt1b_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1b, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1b, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a ST1B instruction. @@ -11670,7 +11656,7 @@ * 0, 0, opnd_size_from_bytes(dr_get_sve_vector_length() / 32), 0) */ #define INSTR_CREATE_st1b_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_st1b, Rn, Zt, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_st1b, Rn, Zt, Pg), DR_PRED_MASKED) /** * Creates a STNT1B instruction. @@ -11707,7 +11693,7 @@ * 0) */ #define INSTR_CREATE_stnt1b_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1b, Rn, Zt, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1b, Rn, Zt, Pg), DR_PRED_MASKED) /** * Creates a BFCVT instruction. @@ -11722,7 +11708,7 @@ * \param Zn The source vector register, Z (Scalable). */ #define INSTR_CREATE_bfcvt_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_bfcvt, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_bfcvt, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a BFDOT instruction. @@ -11964,7 +11950,7 @@ * DR_EXTEND_UXTX, false, 0, 0, OPSZ_0, 0) */ #define INSTR_CREATE_prfb_sve_pred(dc, prfop, Pg, Rn) \ - INSTR_PRED(instr_create_0dst_3src(dc, OP_prfb, prfop, Pg, Rn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_0dst_3src(dc, OP_prfb, prfop, Pg, Rn), DR_PRED_MASKED) /** * Creates a PRFD instruction. @@ -12006,7 +11992,7 @@ * DR_EXTEND_UXTX, true, 0, 0, OPSZ_0, 3) */ #define INSTR_CREATE_prfd_sve_pred(dc, prfop, Pg, Rn) \ - INSTR_PRED(instr_create_0dst_3src(dc, OP_prfd, prfop, Pg, Rn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_0dst_3src(dc, OP_prfd, prfop, Pg, Rn), DR_PRED_MASKED) /** * Creates a PRFH instruction. @@ -12048,7 +12034,7 @@ * DR_EXTEND_UXTX, true, 0, 0, OPSZ_0, 1) */ #define INSTR_CREATE_prfh_sve_pred(dc, prfop, Pg, Rn) \ - INSTR_PRED(instr_create_0dst_3src(dc, OP_prfh, prfop, Pg, Rn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_0dst_3src(dc, OP_prfh, prfop, Pg, Rn), DR_PRED_MASKED) /** * Creates a PRFW instruction. @@ -12090,7 +12076,7 @@ * DR_EXTEND_UXTX, true, 0, 0, OPSZ_0, 2) */ #define INSTR_CREATE_prfw_sve_pred(dc, prfop, Pg, Rn) \ - INSTR_PRED(instr_create_0dst_3src(dc, OP_prfw, prfop, Pg, Rn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_0dst_3src(dc, OP_prfw, prfop, Pg, Rn), DR_PRED_MASKED) /** * Creates an ADR instruction. @@ -12139,7 +12125,7 @@ #define INSTR_CREATE_ld2b_sve_pred(dc, Zt, Pg, Rn) \ INSTR_PRED(instr_create_2dst_2src(dc, OP_ld2b, Zt, opnd_create_increment_reg(Zt, 1), \ Rn, Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a LD3B instruction. @@ -12166,7 +12152,7 @@ #define INSTR_CREATE_ld3b_sve_pred(dc, Zt, Pg, Rn) \ INSTR_PRED(instr_create_3dst_2src(dc, OP_ld3b, Zt, opnd_create_increment_reg(Zt, 1), \ opnd_create_increment_reg(Zt, 2), Rn, Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a LD4B instruction. @@ -12194,7 +12180,7 @@ INSTR_PRED(instr_create_4dst_2src(dc, OP_ld4b, Zt, opnd_create_increment_reg(Zt, 1), \ opnd_create_increment_reg(Zt, 2), \ opnd_create_increment_reg(Zt, 3), Rn, Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a ST2B instruction. @@ -12221,7 +12207,7 @@ #define INSTR_CREATE_st2b_sve_pred(dc, Zt, Pg, Rn) \ INSTR_PRED(instr_create_1dst_3src(dc, OP_st2b, Rn, Zt, \ opnd_create_increment_reg(Zt, 1), Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a ST3B instruction. @@ -12249,7 +12235,7 @@ INSTR_PRED(instr_create_1dst_4src(dc, OP_st3b, Rn, Zt, \ opnd_create_increment_reg(Zt, 1), \ opnd_create_increment_reg(Zt, 2), Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a ST4B instruction. @@ -12278,7 +12264,7 @@ opnd_create_increment_reg(Zt, 1), \ opnd_create_increment_reg(Zt, 2), \ opnd_create_increment_reg(Zt, 3), Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a LD1H instruction. @@ -12344,7 +12330,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 32)) */ #define INSTR_CREATE_ld1h_sve_pred(dc, Zt, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1h, Zt, Zn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1h, Zt, Zn, Pg), DR_PRED_MASKED) /** * Creates a LD1SH instruction. @@ -12405,7 +12391,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 32)) */ #define INSTR_CREATE_ld1sh_sve_pred(dc, Zt, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sh, Zt, Zn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sh, Zt, Zn, Pg), DR_PRED_MASKED) /** * Creates a LD1W instruction. @@ -12465,10 +12451,10 @@ * opnd_create_base_disp(Rn, DR_REG_NULL, 0, imm, * opnd_size_from_bytes(dr_get_sve_vector_length() / 16)) */ -#define INSTR_CREATE_ld1w_sve_pred(dc, Zt, Pg, Zn) \ - INSTR_PRED( \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1w, Zt, Zn, Pg), DR_PRED_GOVERNING), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_ld1w_sve_pred(dc, Zt, Pg, Zn) \ + INSTR_PRED( \ + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1w, Zt, Zn, Pg), DR_PRED_MASKED), \ + DR_PRED_MASKED) /** * Creates a LD1D instruction. @@ -12511,7 +12497,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 8)) */ #define INSTR_CREATE_ld1d_sve_pred(dc, Zt, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1d, Zt, Zn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1d, Zt, Zn, Pg), DR_PRED_MASKED) /** * Creates a LD1SW instruction. @@ -12539,7 +12525,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 16)) */ #define INSTR_CREATE_ld1sw_sve_pred(dc, Zt, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sw, Zt, Zn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ld1sw, Zt, Zn, Pg), DR_PRED_MASKED) /** * Creates a ST1H instruction. @@ -12595,7 +12581,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / opnd_size_to_bytes(Ts))) */ #define INSTR_CREATE_st1h_sve_pred(dc, Zt, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_st1h, Zn, Zt, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_st1h, Zn, Zt, Pg), DR_PRED_MASKED) /** * Creates a ST1W instruction. @@ -12652,7 +12638,7 @@ * opnd_size_to_bytes(Ts)))) */ #define INSTR_CREATE_st1w_sve_pred(dc, Zt, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_st1w, Zn, Zt, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_st1w, Zn, Zt, Pg), DR_PRED_MASKED) /** * Creates a ST1D instruction. @@ -12695,7 +12681,7 @@ * opnd_size_to_bytes(Ts)))) */ #define INSTR_CREATE_st1d_sve_pred(dc, Zt, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_st1d, Zn, Zt, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_st1d, Zn, Zt, Pg), DR_PRED_MASKED) /** * Creates a LD2D instruction. @@ -12722,7 +12708,7 @@ #define INSTR_CREATE_ld2d_sve_pred(dc, Zt, Pg, Rn) \ INSTR_PRED(instr_create_2dst_2src(dc, OP_ld2d, Zt, opnd_create_increment_reg(Zt, 1), \ Rn, Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a LD2H instruction. @@ -12749,7 +12735,7 @@ #define INSTR_CREATE_ld2h_sve_pred(dc, Zt, Pg, Rn) \ INSTR_PRED(instr_create_2dst_2src(dc, OP_ld2h, Zt, opnd_create_increment_reg(Zt, 1), \ Rn, Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a LD2W instruction. @@ -12775,7 +12761,7 @@ #define INSTR_CREATE_ld2w_sve_pred(dc, Zt, Pg, Rn) \ INSTR_PRED(instr_create_2dst_2src(dc, OP_ld2w, Zt, opnd_create_increment_reg(Zt, 1), \ Rn, Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a LD3D instruction. @@ -12802,7 +12788,7 @@ #define INSTR_CREATE_ld3d_sve_pred(dc, Zt, Pg, Rn) \ INSTR_PRED(instr_create_3dst_2src(dc, OP_ld3d, Zt, opnd_create_increment_reg(Zt, 1), \ opnd_create_increment_reg(Zt, 2), Rn, Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a LD3H instruction. @@ -12829,7 +12815,7 @@ #define INSTR_CREATE_ld3h_sve_pred(dc, Zt, Pg, Rn) \ INSTR_PRED(instr_create_3dst_2src(dc, OP_ld3h, Zt, opnd_create_increment_reg(Zt, 1), \ opnd_create_increment_reg(Zt, 2), Rn, Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a LD3W instruction. @@ -12856,7 +12842,7 @@ #define INSTR_CREATE_ld3w_sve_pred(dc, Zt, Pg, Rn) \ INSTR_PRED(instr_create_3dst_2src(dc, OP_ld3w, Zt, opnd_create_increment_reg(Zt, 1), \ opnd_create_increment_reg(Zt, 2), Rn, Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a LD4D instruction. @@ -12884,7 +12870,7 @@ INSTR_PRED(instr_create_4dst_2src(dc, OP_ld4d, Zt, opnd_create_increment_reg(Zt, 1), \ opnd_create_increment_reg(Zt, 2), \ opnd_create_increment_reg(Zt, 3), Rn, Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a LD4H instruction. @@ -12912,7 +12898,7 @@ INSTR_PRED(instr_create_4dst_2src(dc, OP_ld4h, Zt, opnd_create_increment_reg(Zt, 1), \ opnd_create_increment_reg(Zt, 2), \ opnd_create_increment_reg(Zt, 3), Rn, Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a LD4W instruction. @@ -12940,7 +12926,7 @@ INSTR_PRED(instr_create_4dst_2src(dc, OP_ld4w, Zt, opnd_create_increment_reg(Zt, 1), \ opnd_create_increment_reg(Zt, 2), \ opnd_create_increment_reg(Zt, 3), Rn, Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a LDNT1D instruction. @@ -12969,7 +12955,7 @@ * opnd_size_from_bytes(proc_get_vector_length_bytes()), 0) */ #define INSTR_CREATE_ldnt1d_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1d, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1d, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LDNT1H instruction. @@ -13004,7 +12990,7 @@ * opnd_size_from_bytes(proc_get_vector_length_bytes() / 2), 0) */ #define INSTR_CREATE_ldnt1h_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1h, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1h, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LDNT1W instruction. @@ -13037,7 +13023,7 @@ * 0, opnd_size_from_bytes(proc_get_vector_length_bytes()), 0) */ #define INSTR_CREATE_ldnt1w_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1w, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1w, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a ST2D instruction. @@ -13064,7 +13050,7 @@ #define INSTR_CREATE_st2d_sve_pred(dc, Zt, Pg, Rn) \ INSTR_PRED(instr_create_1dst_3src(dc, OP_st2d, Rn, Zt, \ opnd_create_increment_reg(Zt, 1), Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a ST2H instruction. @@ -13091,7 +13077,7 @@ #define INSTR_CREATE_st2h_sve_pred(dc, Zt, Pg, Rn) \ INSTR_PRED(instr_create_1dst_3src(dc, OP_st2h, Rn, Zt, \ opnd_create_increment_reg(Zt, 1), Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a ST2W instruction. @@ -13118,7 +13104,7 @@ #define INSTR_CREATE_st2w_sve_pred(dc, Zt, Pg, Rn) \ INSTR_PRED(instr_create_1dst_3src(dc, OP_st2w, Rn, Zt, \ opnd_create_increment_reg(Zt, 1), Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a ST3D instruction. @@ -13146,7 +13132,7 @@ INSTR_PRED(instr_create_1dst_4src(dc, OP_st3d, Rn, Zt, \ opnd_create_increment_reg(Zt, 1), \ opnd_create_increment_reg(Zt, 2), Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a ST3H instruction. @@ -13174,7 +13160,7 @@ INSTR_PRED(instr_create_1dst_4src(dc, OP_st3h, Rn, Zt, \ opnd_create_increment_reg(Zt, 1), \ opnd_create_increment_reg(Zt, 2), Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a ST3W instruction. @@ -13202,7 +13188,7 @@ INSTR_PRED(instr_create_1dst_4src(dc, OP_st3w, Rn, Zt, \ opnd_create_increment_reg(Zt, 1), \ opnd_create_increment_reg(Zt, 2), Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a ST4D instruction. @@ -13231,7 +13217,7 @@ opnd_create_increment_reg(Zt, 1), \ opnd_create_increment_reg(Zt, 2), \ opnd_create_increment_reg(Zt, 3), Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a ST4H instruction. @@ -13260,7 +13246,7 @@ opnd_create_increment_reg(Zt, 1), \ opnd_create_increment_reg(Zt, 2), \ opnd_create_increment_reg(Zt, 3), Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a ST4W instruction. @@ -13289,7 +13275,7 @@ opnd_create_increment_reg(Zt, 1), \ opnd_create_increment_reg(Zt, 2), \ opnd_create_increment_reg(Zt, 3), Pg), \ - DR_PRED_GOVERNING) + DR_PRED_MASKED) /** * Creates a STNT1D instruction. @@ -13319,7 +13305,7 @@ * opnd_size_from_bytes(proc_get_vector_length_bytes()), 0) */ #define INSTR_CREATE_stnt1d_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1d, Rn, Zt, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1d, Rn, Zt, Pg), DR_PRED_MASKED) /** * Creates a STNT1H instruction. @@ -13353,7 +13339,7 @@ * opnd_size_from_bytes(proc_get_vector_length_bytes() / 2), 0) */ #define INSTR_CREATE_stnt1h_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1h, Rn, Zt, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1h, Rn, Zt, Pg), DR_PRED_MASKED) /** * Creates a STNT1W instruction. @@ -13387,7 +13373,7 @@ * opnd_size_from_bytes(proc_get_vector_length_bytes()), 0) */ #define INSTR_CREATE_stnt1w_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1w, Rn, Zt, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_stnt1w, Rn, Zt, Pg), DR_PRED_MASKED) /** * Creates a LDNF1B instruction. @@ -13418,7 +13404,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 64)) */ #define INSTR_CREATE_ldnf1b_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1b, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1b, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LDNF1D instruction. @@ -13436,7 +13422,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 8)) */ #define INSTR_CREATE_ldnf1d_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1d, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1d, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LDNF1H instruction. @@ -13463,7 +13449,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 32)) */ #define INSTR_CREATE_ldnf1h_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1h, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1h, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LDNF1SB instruction. @@ -13490,7 +13476,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 64)) */ #define INSTR_CREATE_ldnf1sb_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sb, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sb, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LDNF1SH instruction. @@ -13513,7 +13499,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 32)) */ #define INSTR_CREATE_ldnf1sh_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sh, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sh, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LDNF1SW instruction. @@ -13531,7 +13517,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 16)) */ #define INSTR_CREATE_ldnf1sw_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sw, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1sw, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LDNF1W instruction. @@ -13554,7 +13540,7 @@ * opnd_size_from_bytes(dr_get_sve_vector_length() / 16)) */ #define INSTR_CREATE_ldnf1w_sve_pred(dc, Zt, Pg, Rn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1w, Zt, Rn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnf1w, Zt, Rn, Pg), DR_PRED_MASKED) /** * Creates a LDAPUR instruction. @@ -14490,7 +14476,7 @@ * \param Zn The second source vector register, Z (Scalable). */ #define INSTR_CREATE_bfcvtnt_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_bfcvtnt, Zd, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_bfcvtnt, Zd, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates an AESD instruction. @@ -16363,7 +16349,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_addp_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_addp, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_addp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FADDP instruction. @@ -16379,7 +16365,7 @@ * \param Zm The second source vector register. Can be Z.h, Z.s or Z.d. */ #define INSTR_CREATE_faddp_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_faddp, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_faddp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FMAXNMP instruction. @@ -16394,9 +16380,8 @@ * \param Pg The governing predicate register, P (Predicate). * \param Zm The second source vector register. Can be Z.h, Z.s or Z.d. */ -#define INSTR_CREATE_fmaxnmp_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnmp, Zdn, Pg, Zdn, Zm), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_fmaxnmp_sve_pred(dc, Zdn, Pg, Zm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxnmp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FMAXP instruction. @@ -16412,7 +16397,7 @@ * \param Zm The second source vector register. Can be Z.h, Z.s or Z.d. */ #define INSTR_CREATE_fmaxp_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxp, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fmaxp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FMINNMP instruction. @@ -16427,9 +16412,8 @@ * \param Pg The governing predicate register, P (Predicate). * \param Zm The second source vector register. Can be Z.h, Z.s or Z.d. */ -#define INSTR_CREATE_fminnmp_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnmp, Zdn, Pg, Zdn, Zm), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_fminnmp_sve_pred(dc, Zdn, Pg, Zm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_fminnmp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FMINP instruction. @@ -16445,7 +16429,7 @@ * \param Zm The second source vector register. Can be Z.h, Z.s or Z.d. */ #define INSTR_CREATE_fminp_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fminp, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fminp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a HISTCNT instruction. @@ -16461,7 +16445,7 @@ * \param Zm The second source vector register. Can be Z.s or Z.d. */ #define INSTR_CREATE_histcnt_sve_pred(dc, Zd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_histcnt, Zd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_histcnt, Zd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a SHADD instruction. @@ -16477,7 +16461,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_shadd_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_shadd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_shadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SHSUB instruction. @@ -16493,7 +16477,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_shsub_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_shsub, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_shsub, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SHSUBR instruction. @@ -16509,7 +16493,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_shsubr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_shsubr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_shsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SMAXP instruction. @@ -16525,7 +16509,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_smaxp_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_smaxp, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_smaxp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SMINP instruction. @@ -16541,7 +16525,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_sminp_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_sminp, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sminp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SQRSHL instruction. @@ -16557,7 +16541,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_sqrshl_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_sqrshl, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sqrshl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SQRSHLR instruction. @@ -16572,9 +16556,8 @@ * \param Pg The governing predicate register, P (Predicate). * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ -#define INSTR_CREATE_sqrshlr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_sqrshlr, Zdn, Pg, Zdn, Zm), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_sqrshlr_sve_pred(dc, Zdn, Pg, Zm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_sqrshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SQSHL instruction. @@ -16591,9 +16574,8 @@ * \param Zm_imm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d * or an immediate */ -#define INSTR_CREATE_sqshl_sve_pred(dc, Zdn, Pg, Zm_imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshl, Zdn, Pg, Zdn, Zm_imm), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_sqshl_sve_pred(dc, Zdn, Pg, Zm_imm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshl, Zdn, Pg, Zdn, Zm_imm), DR_PRED_MASKED) /** * Creates a SQSHLR instruction. @@ -16609,7 +16591,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_sqshlr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshlr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SQSUBR instruction. @@ -16625,7 +16607,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_sqsubr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_sqsubr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sqsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SRHADD instruction. @@ -16641,7 +16623,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_srhadd_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_srhadd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_srhadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SRSHL instruction. @@ -16657,7 +16639,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_srshl_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_srshl, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_srshl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SRSHLR instruction. @@ -16673,7 +16655,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_srshlr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_srshlr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_srshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a SUQADD instruction. @@ -16689,7 +16671,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_suqadd_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_suqadd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_suqadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an UHADD instruction. @@ -16705,7 +16687,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_uhadd_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_uhadd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uhadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an UHSUB instruction. @@ -16721,7 +16703,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_uhsub_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_uhsub, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uhsub, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an UHSUBR instruction. @@ -16737,7 +16719,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_uhsubr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_uhsubr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uhsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an UMAXP instruction. @@ -16753,7 +16735,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_umaxp_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_umaxp, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_umaxp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an UMINP instruction. @@ -16769,7 +16751,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_uminp_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_uminp, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uminp, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an UQRSHL instruction. @@ -16785,7 +16767,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_uqrshl_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_uqrshl, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uqrshl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an UQRSHLR instruction. @@ -16800,9 +16782,8 @@ * \param Pg The governing predicate register, P (Predicate). * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ -#define INSTR_CREATE_uqrshlr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_uqrshlr, Zdn, Pg, Zdn, Zm), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_uqrshlr_sve_pred(dc, Zdn, Pg, Zm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_uqrshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an UQSHL instruction. @@ -16819,9 +16800,8 @@ * \param Zm_imm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d * or can be an immediate. */ -#define INSTR_CREATE_uqshl_sve_pred(dc, Zdn, Pg, Zm_imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_uqshl, Zdn, Pg, Zdn, Zm_imm), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_uqshl_sve_pred(dc, Zdn, Pg, Zm_imm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_uqshl, Zdn, Pg, Zdn, Zm_imm), DR_PRED_MASKED) /** * Creates an UQSHLR instruction. @@ -16837,7 +16817,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_uqshlr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_uqshlr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uqshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an UQSUBR instruction. @@ -16853,7 +16833,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_uqsubr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_uqsubr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uqsubr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an URHADD instruction. @@ -16869,7 +16849,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_urhadd_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_urhadd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_urhadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an URSHL instruction. @@ -16885,7 +16865,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_urshl_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_urshl, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_urshl, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an URSHLR instruction. @@ -16901,7 +16881,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_urshlr_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_urshlr, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_urshlr, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates an USQADD instruction. @@ -16917,7 +16897,7 @@ * \param Zm The second source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_usqadd_sve_pred(dc, Zdn, Pg, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_usqadd, Zdn, Pg, Zdn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_usqadd, Zdn, Pg, Zdn, Zm), DR_PRED_MASKED) /** * Creates a FCVTLT instruction. @@ -16933,7 +16913,7 @@ * \param Zn The source vector register. Can be Z.h or Z.s. */ #define INSTR_CREATE_fcvtlt_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtlt, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtlt, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FCVTNT instruction. @@ -16949,7 +16929,7 @@ * \param Zn The second source vector register. Can be Z.d or Z.s. */ #define INSTR_CREATE_fcvtnt_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fcvtnt, Zd, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcvtnt, Zd, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FCVTX instruction. @@ -16964,7 +16944,7 @@ * \param Zn The source vector register, Z.d. */ #define INSTR_CREATE_fcvtx_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtx, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_fcvtx, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FCVTXNT instruction. @@ -16979,7 +16959,7 @@ * \param Zn The second source vector register, Z.d. */ #define INSTR_CREATE_fcvtxnt_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_fcvtxnt, Zd, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_fcvtxnt, Zd, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a FLOGB instruction. @@ -16994,7 +16974,7 @@ * \param Zn The source vector register. Can be Z.h, Z.s or Z.d. */ #define INSTR_CREATE_flogb_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_flogb, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_flogb, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a SADALP instruction. @@ -17010,7 +16990,7 @@ * \param Zn The second source vector register. Can be Z.b, Z.h or Z.s. */ #define INSTR_CREATE_sadalp_sve_pred(dc, Zda, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_sadalp, Zda, Zda, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_sadalp, Zda, Zda, Pg, Zn), DR_PRED_MASKED) /** * Creates a SQABS instruction. @@ -17025,7 +17005,7 @@ * \param Zn The source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_sqabs_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_sqabs, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_sqabs, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a SQNEG instruction. @@ -17040,7 +17020,7 @@ * \param Zn The source vector register. Can be Z.b, Z.h, Z.s or Z.d. */ #define INSTR_CREATE_sqneg_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_sqneg, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_sqneg, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates an UADALP instruction. @@ -17056,7 +17036,7 @@ * \param Zn The second source vector register. Can be Z.b, Z.h or Z.s. */ #define INSTR_CREATE_uadalp_sve_pred(dc, Zda, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_uadalp, Zda, Zda, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_uadalp, Zda, Zda, Pg, Zn), DR_PRED_MASKED) /** * Creates a CADD instruction. @@ -17293,9 +17273,8 @@ * \param Pg The governing predicate register, P (Predicate). * \param imm The immediate imm. */ -#define INSTR_CREATE_sqshlu_sve_pred(dc, Zdn, Pg, imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshlu, Zdn, Pg, Zdn, imm), \ - DR_PRED_GOVERNING) +#define INSTR_CREATE_sqshlu_sve_pred(dc, Zdn, Pg, imm) \ + INSTR_PRED(instr_create_1dst_3src(dc, OP_sqshlu, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) /** * Creates a SQSHRNB instruction. @@ -17389,7 +17368,7 @@ * \param imm The immediate imm1. */ #define INSTR_CREATE_srshr_sve_pred(dc, Zdn, Pg, imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_srshr, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_srshr, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) /** * Creates a SRSRA instruction. @@ -17529,7 +17508,7 @@ * \param imm The immediate imm1. */ #define INSTR_CREATE_urshr_sve_pred(dc, Zdn, Pg, imm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_urshr, Zdn, Pg, Zdn, imm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_urshr, Zdn, Pg, Zdn, imm), DR_PRED_MASKED) /** * Creates an URSRA instruction. @@ -17626,7 +17605,7 @@ * OPSZ_8, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_4, 0) */ #define INSTR_CREATE_ldnt1sb_sve_pred(dc, Zt, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sb, Zt, Zn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sb, Zt, Zn, Pg), DR_PRED_MASKED) /** * Creates a LDNT1SH instruction. @@ -17645,7 +17624,7 @@ * OPSZ_8, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_8, 0) */ #define INSTR_CREATE_ldnt1sh_sve_pred(dc, Zt, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sh, Zt, Zn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sh, Zt, Zn, Pg), DR_PRED_MASKED) /** * Creates a LDNT1SW instruction. @@ -17663,7 +17642,7 @@ * OPSZ_8, DR_EXTEND_UXTX, 0, 0, 0, OPSZ_16, 0) */ #define INSTR_CREATE_ldnt1sw_sve_pred(dc, Zt, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sw, Zt, Zn, Pg), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ldnt1sw, Zt, Zn, Pg), DR_PRED_MASKED) /** * Creates an UZP1 instruction. @@ -17749,7 +17728,7 @@ * \param Zm The second source vector register. Can be Z.b or Z.h. */ #define INSTR_CREATE_match_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_match, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_match, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates a NMATCH instruction. @@ -17765,7 +17744,7 @@ * \param Zm The second source vector register. Can be Z.b or Z.h. */ #define INSTR_CREATE_nmatch_sve_pred(dc, Pd, Pg, Zn, Zm) \ - INSTR_PRED(instr_create_1dst_3src(dc, OP_nmatch, Pd, Pg, Zn, Zm), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_3src(dc, OP_nmatch, Pd, Pg, Zn, Zm), DR_PRED_MASKED) /** * Creates an URECPE instruction. @@ -17780,7 +17759,7 @@ * \param Zn The source vector register, Z.s. */ #define INSTR_CREATE_urecpe_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_urecpe, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_urecpe, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates an URSQRTE instruction. @@ -17795,7 +17774,7 @@ * \param Zn The source vector register, Z.s. */ #define INSTR_CREATE_ursqrte_sve_pred(dc, Zd, Pg, Zn) \ - INSTR_PRED(instr_create_1dst_2src(dc, OP_ursqrte, Zd, Pg, Zn), DR_PRED_GOVERNING) + INSTR_PRED(instr_create_1dst_2src(dc, OP_ursqrte, Zd, Pg, Zn), DR_PRED_MASKED) /** * Creates a WHILEGE instruction. diff --git a/core/ir/instr.h b/core/ir/instr.h index b33116dd505..b26e83017cb 100644 --- a/core/ir/instr.h +++ b/core/ir/instr.h @@ -517,14 +517,14 @@ instr_set_translation_mangling_epilogue(dcontext_t *dcontext, instrlist_t *ilist instr_t *instr); #ifdef AARCH64 -/* Sets the DR_PRED_GOVERNING flag on the instruction to indicate that +/* Sets the DR_PRED_MASKED flag on the instruction to indicate that * this instruction is predicated and execution depends on the value of a * predicate register */ void instr_set_has_register_predication(instr_t *instr); -/* Checks if DR_PRED_GOVERNING is set on the instruction, which indicates +/* Checks if DR_PRED_MASKED is set on the instruction, which indicates it has a governing predicate register. */ bool diff --git a/core/ir/instr_api.h b/core/ir/instr_api.h index 9391eb3ed27..e5175b7b1b6 100644 --- a/core/ir/instr_api.h +++ b/core/ir/instr_api.h @@ -138,10 +138,10 @@ typedef enum _dr_pred_type_t { DR_PRED_LE, /**< ARM condition: 1101 Signed <= (Z == 1 or N != V) */ DR_PRED_AL, /**< ARM condition: 1110 Always (unconditional) */ # ifdef AARCH64 - DR_PRED_NV, /**< ARM condition: 1111 Never, meaning always */ - DR_PRED_GOVERNING, /** Used for AArch64 SVE instructions with governing predicate - * registers - */ + DR_PRED_NV, /**< ARM condition: 1111 Never, meaning always */ + DR_PRED_MASKED, /** Used for AArch64 SVE instructions with governing predicate + * registers + */ # endif # ifdef ARM DR_PRED_OP, /**< ARM condition: 1111 Part of opcode */ @@ -2542,17 +2542,17 @@ instr_is_reg_spill_or_restore(void *drcontext, instr_t *instr, bool *tls DR_PARA /* we only care about these 11 flags, and mostly only about the first 6 * we consider an undefined effect on a flag to be a write */ -# define EFLAGS_READ_CF 0x00000001 /**< Reads CF (Carry Flag). */ -# define EFLAGS_READ_PF 0x00000002 /**< Reads PF (Parity Flag). */ -# define EFLAGS_READ_AF 0x00000004 /**< Reads AF (Auxiliary Carry Flag). */ -# define EFLAGS_READ_ZF 0x00000008 /**< Reads ZF (Zero Flag). */ -# define EFLAGS_READ_SF 0x00000010 /**< Reads SF (Sign Flag). */ -# define EFLAGS_READ_TF 0x00000020 /**< Reads TF (Trap Flag). */ -# define EFLAGS_READ_IF 0x00000040 /**< Reads IF (Interrupt Enable Flag). */ -# define EFLAGS_READ_DF 0x00000080 /**< Reads DF (Direction Flag). */ -# define EFLAGS_READ_OF 0x00000100 /**< Reads OF (Overflow Flag). */ -# define EFLAGS_READ_NT 0x00000200 /**< Reads NT (Nested Task). */ -# define EFLAGS_READ_RF 0x00000400 /**< Reads RF (Resume Flag). */ +# define EFLAGS_READ_CF 0x00000001 /**< Reads CF (Carry Flag). */ +# define EFLAGS_READ_PF 0x00000002 /**< Reads PF (Parity Flag). */ +# define EFLAGS_READ_AF 0x00000004 /**< Reads AF (Auxiliary Carry Flag). */ +# define EFLAGS_READ_ZF 0x00000008 /**< Reads ZF (Zero Flag). */ +# define EFLAGS_READ_SF 0x00000010 /**< Reads SF (Sign Flag). */ +# define EFLAGS_READ_TF 0x00000020 /**< Reads TF (Trap Flag). */ +# define EFLAGS_READ_IF 0x00000040 /**< Reads IF (Interrupt Enable Flag). */ +# define EFLAGS_READ_DF 0x00000080 /**< Reads DF (Direction Flag). */ +# define EFLAGS_READ_OF 0x00000100 /**< Reads OF (Overflow Flag). */ +# define EFLAGS_READ_NT 0x00000200 /**< Reads NT (Nested Task). */ +# define EFLAGS_READ_RF 0x00000400 /**< Reads RF (Resume Flag). */ # define EFLAGS_WRITE_CF 0x00000800 /**< Writes CF (Carry Flag). */ # define EFLAGS_WRITE_PF 0x00001000 /**< Writes PF (Parity Flag). */ diff --git a/core/ir/instr_shared.c b/core/ir/instr_shared.c index 6e98a5047a0..32cf9841f96 100644 --- a/core/ir/instr_shared.c +++ b/core/ir/instr_shared.c @@ -2581,13 +2581,13 @@ instr_set_translation_mangling_epilogue(dcontext_t *dcontext, instrlist_t *ilist void instr_set_has_register_predication(instr_t *instr) { - instr_set_predicate(instr, DR_PRED_GOVERNING); + instr_set_predicate(instr, DR_PRED_MASKED); } bool instr_has_register_predication(instr_t *instr) { - return instr_get_predicate(instr) == DR_PRED_GOVERNING; + return instr_get_predicate(instr) == DR_PRED_MASKED; } #endif