*** These labs are a work-in-progress. See NOTES doc for full list of repo status.
This lab course consists of 6 labs and a final project. The labs go through the ASIC design flow, from RTL through GDS. These labs are now available in two process technologies, the ASAP7 7nm Predictive PDK (a non-implementable finFET technology developed for educational purposes) and the Skywater 130nm PDK (a real open-source 130nm CMOS process developed by Google and Skywater foundries).
- Lab 1: Getting Around the Compute Environment
- Lab 2: Simulation
- Lab 3: Logic Synthesis
- Lab 4: Floorplanning, Placement, Power, and CTS
- Lab 5: Parallelization and Routing
- Lab 6: SRAM Integration, DRC, LVS
This project guides students through writing their own CPU core and cache, and pushing this design through the ASIC flow to achieve a physical design.
- Project Overview : Introduction, Project setup and Grading
- Checkpoint 1 : ALU design and Pipeline diagram
- Checkpoint 2 : Fully functioning core
- Checkpoint 3 : Cache
- Checkpoint 4 : Synthesis, PAR & Power
Alternate versions of the ASAP7 labs above use the Skywater 130nm PDK instead. Lab 6 is omitted because (1) the Sky130 SRAMs are currently not mature enough to be used for educational purposes, and (2) for DRC/LVS, the Sky130 Calibre decks are still under NDA, and while the open-source decks are available (for use with Magic and Netgen), our ASIC design flow does not currently support these open-source EDA tools. To learn about SRAMs, DRC, and LVS, please follow the ASAP7 version of Lab 6 above.