synthesis error

[anudeepdharavathu]

Synthesis tool: Synopsys design compiler Version U-2022.12 for linux64
Command used: dcnxt_shell -f run_script_openpiton.tcl
Notes: I am trying to synthesize an eFPGA (IO width of 256 bits) but it doesn't proceed beyond the default design mapping phase.
I am attaching the synthesis settings and script below.
run_script_openpiton.txt

Any help is appreciated.

[ruck314]

@anudeepdharavathu Back in 2022 we ran into a similar issue when we synthesised the eFPGA using Synopsys DC compiler. We determined that the synthesis tool was hanging due to the "combinatorial loops" that's detected in the matrix switches and the tool trying to make timing on an "impossible" timing path.

We were able to resolve the tool "hanging" issue by disabling the timing path with combinatorial loops using the following TCL command:

set_disable_timing [get_pins -hierarchical *switch_matrix/*BEG*]

This particular timing constraint was applied after the elaborate command and before the compile_ultra command. Hopeful adding this timing constraint will resolve your issue.