From f79ce2aee3db4dfebc6d1782f986976e40516166 Mon Sep 17 00:00:00 2001 From: Edw590 <40151365+Edw590@users.noreply.github.com> Date: Fri, 30 Aug 2024 14:38:05 +0100 Subject: [PATCH 1/3] Create iob_rom_2p --- .../hardware/simulation/src/iob_rom_2p_tb.v | 103 ++++++++++++++++++ .../rom/iob_rom_2p/hardware/src/iob_rom_2p.v | 39 +++++++ .../memories/rom/iob_rom_2p/iob_rom_2p.py | 15 +++ 3 files changed, 157 insertions(+) create mode 100644 lib/hardware/memories/rom/iob_rom_2p/hardware/simulation/src/iob_rom_2p_tb.v create mode 100644 lib/hardware/memories/rom/iob_rom_2p/hardware/src/iob_rom_2p.v create mode 100644 lib/hardware/memories/rom/iob_rom_2p/iob_rom_2p.py diff --git a/lib/hardware/memories/rom/iob_rom_2p/hardware/simulation/src/iob_rom_2p_tb.v b/lib/hardware/memories/rom/iob_rom_2p/hardware/simulation/src/iob_rom_2p_tb.v new file mode 100644 index 000000000..b2c935d76 --- /dev/null +++ b/lib/hardware/memories/rom/iob_rom_2p/hardware/simulation/src/iob_rom_2p_tb.v @@ -0,0 +1,103 @@ +`timescale 1ns / 1ps +`define ADDR_W 10 +`define DATA_W 32 + +module iob_rom_2p_tb; + + // Inputs + reg clk; + + // Read 1 signals + reg r1_en; + reg [`ADDR_W-1:0] r1_addr; + + + // Read 2 signals + reg r2_en; + reg [`ADDR_W-1:0] r2_addr; + + wire [`DATA_W-1:0] r_data; + + integer i, seq_ini; + integer fd; + + parameter clk_per = 10; // clk period = 10 timeticks + + initial begin + + // Initialize Inputs + clk = 1; + r1_en = 0; + r2_en = 0; + r1_addr = 0; + r2_addr = 0; + + // optional VCD +`ifdef VCD + $dumpfile("uut.vcd"); + $dumpvars(); +`endif + + // Number from which to start the incremental sequence to initialize the ROM + seq_ini = 32; + for (i = 0; i < 2 ** `ADDR_W; i = i + 1) begin + uut.iob_rom_sp_inst.rom[i] = i + seq_ini; + end + + // Read all the locations of ROM with r1_en = 0 + r1_en = 0; + @(posedge clk) #1; + + for (i = 0; i < 2 ** `ADDR_W; i = i + 1) begin + r1_addr = i; + @(posedge clk) #1; + if (r_data != 0) begin + $display("ERROR: with r1_en = 0, at position %0d, r_data should be 0 but is %d", i, + r_data); + $fatal(1); + end + end + + r2_en = 1; + @(posedge clk) #1; + + // Read all the locations of ROM with r2_en = 1 + for (i = 0; i < 2 ** `ADDR_W; i = i + 1) begin + r2_addr = i; + @(posedge clk) #1; + if (r_data != i + seq_ini) begin + $display("ERROR: on position %0d, r_data is %d where it should be %0d", i, r_data, + i + seq_ini); + $fatal(1); + end + end + + r2_en = 0; + + #(5 * clk_per); + $display("%c[1;34m", 27); + $display("Test completed successfully."); + $display("%c[0m", 27); + fd = $fopen("test.log", "w"); + $fdisplay(fd, "Test passed!"); + $fclose(fd); + $finish(); + end + + // Instantiate the Unit Under Test (UUT) + iob_rom_2p #( + .DATA_W(`DATA_W), + .ADDR_W(`ADDR_W) + ) uut ( + .clk_i (clk), + .r1_en_i (r1_en), + .r1_addr_i(r1_addr), + .r2_en_i (r2_en), + .r2_addr_i(r2_addr), + .r_data_o (r_data) + ); + + // Clock + always #(clk_per / 2) clk = ~clk; + +endmodule diff --git a/lib/hardware/memories/rom/iob_rom_2p/hardware/src/iob_rom_2p.v b/lib/hardware/memories/rom/iob_rom_2p/hardware/src/iob_rom_2p.v new file mode 100644 index 000000000..96109fd9d --- /dev/null +++ b/lib/hardware/memories/rom/iob_rom_2p/hardware/src/iob_rom_2p.v @@ -0,0 +1,39 @@ +`timescale 1ns / 1ps + +module iob_rom_2p #( + parameter HEXFILE = "none", + parameter DATA_W = 0, + parameter ADDR_W = 0 +) ( + input clk_i, + + //read port 1 + input r1_en_i, + input [ADDR_W-1:0] r1_addr_i, + + //read port 2 + input r2_en_i, + input [ADDR_W-1:0] r2_addr_i, + + output [DATA_W-1:0] r_data_o +); + + wire en_int; + wire [ADDR_W-1:0] addr_int; + + // Internal Single Port ROM + iob_rom_sp #( + .HEXFILE(HEXFILE), + .DATA_W(DATA_W), + .ADDR_W(ADDR_W) + ) iob_rom_sp_inst ( + .clk_i (clk_i), + .r_en_i (en_int), + .addr_i (addr_int), + .r_data_o(r_data_o) + ); + + assign en_int = r1_en_i | r2_en_i; + assign addr_int = r1_en_i ? r1_addr_i : r2_addr_i; + +endmodule diff --git a/lib/hardware/memories/rom/iob_rom_2p/iob_rom_2p.py b/lib/hardware/memories/rom/iob_rom_2p/iob_rom_2p.py new file mode 100644 index 000000000..5b49ad8fe --- /dev/null +++ b/lib/hardware/memories/rom/iob_rom_2p/iob_rom_2p.py @@ -0,0 +1,15 @@ +def setup(py_params_dict): + attributes_dict = { + "original_name": "iob_rom_2p", + "name": "iob_rom_2p", + "version": "0.1", + "generate_hw": False, + "blocks": [ + { + "core_name": "iob_rom_sp", + "instance_name": "iob_rom_sp_inst", + }, + ], + } + + return attributes_dict From 044593fe3a98a22e7b1fd8a7e9b4040f7a4aacd3 Mon Sep 17 00:00:00 2001 From: Edw590 <40151365+Edw590@users.noreply.github.com> Date: Sat, 31 Aug 2024 15:53:24 +0100 Subject: [PATCH 2/3] Add ready signals to iob_rom_2p --- .../hardware/simulation/src/iob_rom_2p_tb.v | 22 +++++++++++++------ .../rom/iob_rom_2p/hardware/src/iob_rom_2p.v | 4 ++++ 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/lib/hardware/memories/rom/iob_rom_2p/hardware/simulation/src/iob_rom_2p_tb.v b/lib/hardware/memories/rom/iob_rom_2p/hardware/simulation/src/iob_rom_2p_tb.v index b2c935d76..f64db2cff 100644 --- a/lib/hardware/memories/rom/iob_rom_2p/hardware/simulation/src/iob_rom_2p_tb.v +++ b/lib/hardware/memories/rom/iob_rom_2p/hardware/simulation/src/iob_rom_2p_tb.v @@ -10,11 +10,13 @@ module iob_rom_2p_tb; // Read 1 signals reg r1_en; reg [`ADDR_W-1:0] r1_addr; + wire r1_ready; // Read 2 signals reg r2_en; reg [`ADDR_W-1:0] r2_addr; + wire r2_ready; wire [`DATA_W-1:0] r_data; @@ -44,7 +46,7 @@ module iob_rom_2p_tb; uut.iob_rom_sp_inst.rom[i] = i + seq_ini; end - // Read all the locations of ROM with r1_en = 0 + // Attempt to read all the locations of ROM with r1_en = 0 r1_en = 0; @(posedge clk) #1; @@ -64,6 +66,10 @@ module iob_rom_2p_tb; // Read all the locations of ROM with r2_en = 1 for (i = 0; i < 2 ** `ADDR_W; i = i + 1) begin r2_addr = i; + // wait for r2_ready + while (!r2_ready) begin + @(posedge clk) #1; + end @(posedge clk) #1; if (r_data != i + seq_ini) begin $display("ERROR: on position %0d, r_data is %d where it should be %0d", i, r_data, @@ -89,12 +95,14 @@ module iob_rom_2p_tb; .DATA_W(`DATA_W), .ADDR_W(`ADDR_W) ) uut ( - .clk_i (clk), - .r1_en_i (r1_en), - .r1_addr_i(r1_addr), - .r2_en_i (r2_en), - .r2_addr_i(r2_addr), - .r_data_o (r_data) + .clk_i (clk), + .r1_en_i (r1_en), + .r1_addr_i (r1_addr), + .r1_ready_o(r1_ready), + .r2_en_i (r2_en), + .r2_addr_i (r2_addr), + .r2_ready_o(r2_ready), + .r_data_o (r_data) ); // Clock diff --git a/lib/hardware/memories/rom/iob_rom_2p/hardware/src/iob_rom_2p.v b/lib/hardware/memories/rom/iob_rom_2p/hardware/src/iob_rom_2p.v index 96109fd9d..2e8facdc0 100644 --- a/lib/hardware/memories/rom/iob_rom_2p/hardware/src/iob_rom_2p.v +++ b/lib/hardware/memories/rom/iob_rom_2p/hardware/src/iob_rom_2p.v @@ -10,10 +10,12 @@ module iob_rom_2p #( //read port 1 input r1_en_i, input [ADDR_W-1:0] r1_addr_i, + output r1_ready_o, //read port 2 input r2_en_i, input [ADDR_W-1:0] r2_addr_i, + output r2_ready_o, output [DATA_W-1:0] r_data_o ); @@ -35,5 +37,7 @@ module iob_rom_2p #( assign en_int = r1_en_i | r2_en_i; assign addr_int = r1_en_i ? r1_addr_i : r2_addr_i; + assign r1_ready_o = r1_en_i; + assign r2_ready_o = r1_en_i ? 0 : r2_en_i; endmodule From 9988c11b46793c7ebf3b53eccd7aaccb40ca7fe3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Mon, 9 Sep 2024 16:52:10 +0100 Subject: [PATCH 3/3] refactor(rom): Apply suggestion from https://github.com/IObundle/iob-soc/pull/938 --- .../rom/iob_rom_2p/hardware/src/iob_rom_2p.v | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/lib/hardware/memories/rom/iob_rom_2p/hardware/src/iob_rom_2p.v b/lib/hardware/memories/rom/iob_rom_2p/hardware/src/iob_rom_2p.v index 2e8facdc0..bd0287002 100644 --- a/lib/hardware/memories/rom/iob_rom_2p/hardware/src/iob_rom_2p.v +++ b/lib/hardware/memories/rom/iob_rom_2p/hardware/src/iob_rom_2p.v @@ -1,9 +1,9 @@ `timescale 1ns / 1ps module iob_rom_2p #( - parameter HEXFILE = "none", - parameter DATA_W = 0, - parameter ADDR_W = 0 + parameter HEXFILE = "none", + parameter DATA_W = 0, + parameter ADDR_W = 0 ) ( input clk_i, @@ -20,14 +20,14 @@ module iob_rom_2p #( output [DATA_W-1:0] r_data_o ); - wire en_int; + wire en_int; wire [ADDR_W-1:0] addr_int; // Internal Single Port ROM iob_rom_sp #( .HEXFILE(HEXFILE), - .DATA_W(DATA_W), - .ADDR_W(ADDR_W) + .DATA_W (DATA_W), + .ADDR_W (ADDR_W) ) iob_rom_sp_inst ( .clk_i (clk_i), .r_en_i (en_int), @@ -35,9 +35,9 @@ module iob_rom_2p #( .r_data_o(r_data_o) ); - assign en_int = r1_en_i | r2_en_i; - assign addr_int = r1_en_i ? r1_addr_i : r2_addr_i; - assign r1_ready_o = r1_en_i; - assign r2_ready_o = r1_en_i ? 0 : r2_en_i; + assign en_int = r1_en_i | r2_en_i; + assign addr_int = r1_en_i ? r1_addr_i : r2_addr_i; + assign r1_ready_o = 1'b1; + assign r2_ready_o = ~r1_en_i; endmodule