diff --git a/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py b/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py index 853abf3df..1354fb0e1 100644 --- a/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py +++ b/hardware/fpga/quartus/cyclonev_gt_dk/cyclonev_gt_dk.py @@ -45,7 +45,7 @@ def setup(py_params_dict): # attributes_dict["ports"] = [ { - "name": "clk_rst", + "name": "clk_rst_i", "descr": "Clock and reset", "signals": [ {"name": "clk", "direction": "input", "width": "1"}, @@ -85,7 +85,7 @@ def setup(py_params_dict): ], }, { - "name": "rzqin", + "name": "rzqin_i", "descr": "", "signals": [ {"name": "rzqin", "direction": "input", "width": "1"}, @@ -255,9 +255,9 @@ def setup(py_params_dict): "AXI_DATA_W": "AXI_DATA_W", }, "connect": { - "clk_en_rst": "clk_en_rst", - "rs232": "rs232_int", - "axi": "axi", + "clk_en_rst_s": "clk_en_rst", + "rs232_m": "rs232_int", + "axi_m": "axi", }, "dest_dir": "hardware/common_src", "iob_soc_params": params, @@ -267,7 +267,7 @@ def setup(py_params_dict): "instance_name": "rst_sync", "instance_description": "Reset synchronizer", "connect": { - "clk_rst": "reset_sync_clk_rst", + "clk_rst_s": "reset_sync_clk_rst", "arst_o": "reset_sync_arst_out", }, }, @@ -286,10 +286,10 @@ def setup(py_params_dict): "AXI_DATA_W": "AXI_DATA_W", }, "connect": { - "clk_rst": "ddr3_ctr_clk_rst", + "clk_rst_i": "ddr3_ctr_clk_rst", "general": "ddr3_ctr_general", "ddr3": "ddr3", - "s0_axi": "axi", + "s0_axi_s": "axi", }, }, ] @@ -306,10 +306,10 @@ def setup(py_params_dict): "AXI_DATA_W": "AXI_DATA_W", }, "connect": { - "clk": "clk", - "rst": "reset_sync_arst_out", - "s0_axi": "axi", - "m0_axi": "memory_axi", + "clk_i": "clk", + "rst_i": "reset_sync_arst_out", + "s0_axi_s": "axi", + "m0_axi_m": "memory_axi", }, "num_slaves": 1, "num_masters": 1, @@ -325,9 +325,9 @@ def setup(py_params_dict): "READ_ON_WRITE": "0", }, "connect": { - "clk": "clk", - "rst": "reset_sync_arst_out", - "axi": "memory_axi", + "clk_i": "clk", + "rst_i": "reset_sync_arst_out", + "axi_s": "memory_axi", }, }, ] diff --git a/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py b/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py index a27eaa026..20e7e83f6 100644 --- a/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py +++ b/hardware/fpga/vivado/aes_ku040_db_g/aes_ku040_db_g.py @@ -49,7 +49,7 @@ def setup(py_params_dict): # attributes_dict["ports"] = [ { - "name": "clk_rst", + "name": "clk_rst_i", "descr": "Clock and reset", "signals": [ {"name": "c0_sys_clk_clk_p", "direction": "input", "width": "1"}, @@ -274,9 +274,9 @@ def setup(py_params_dict): "AXI_DATA_W": "AXI_DATA_W", }, "connect": { - "clk_en_rst": "clk_en_rst", - "rs232": "rs232_int", - "axi": "axi", + "clk_en_rst_s": "clk_en_rst", + "rs232_m": "rs232_int", + "axi_m": "axi", }, "dest_dir": "hardware/common_src", "iob_soc_params": params, @@ -292,11 +292,11 @@ def setup(py_params_dict): "AXI_DATA_W": "AXI_DATA_W", }, "connect": { - "clk_rst_i": "intercon_clk_rst", + "clk_rst_s": "intercon_clk_rst", "m0_clk_rst": "intercon_m0_clk_rst", - "m0_axi": "memory_axi", + "m0_axi_m": "memory_axi", "s0_clk_rst": "intercon_s0_clk_rst", - "s0_axi": "axi", + "s0_axi_s": "axi", }, "num_slaves": 1, }, @@ -315,10 +315,10 @@ def setup(py_params_dict): "AXI_DATA_W": "AXI_DATA_W", }, "connect": { - "clk_rst": "clk_rst", - "ui_clk_out": "ddr4_ui_clk_out", + "clk_rst_i": "clk_rst_i", + "ui_clk_o": "ddr4_ui_clk_out", "axi_clk_rst": "ddr4_axi_clk_rst", - "axi": "memory_axi", + "axi_s": "memory_axi", "ddr4": "ddr4_pins", }, }, @@ -335,7 +335,7 @@ def setup(py_params_dict): "INPUT_PER": 4, }, "connect": { - "clk_rst_i": "clk_rst", + "clk_rst_i": "clk_rst_i", "clk_rst_o": "clk_wizard_out", }, }, @@ -350,9 +350,9 @@ def setup(py_params_dict): "READ_ON_WRITE": "1", }, "connect": { - "clk": "axi_ram_clk", - "rst": "axi_ram_rst", - "axi": "memory_axi", + "clk_i": "axi_ram_clk", + "rst_i": "axi_ram_rst", + "axi_s": "memory_axi", }, }, ] diff --git a/hardware/modules/iob_soc_cache_system/iob_soc_cache_system.py b/hardware/modules/iob_soc_cache_system/iob_soc_cache_system.py index 9de6ae284..472d8e0bf 100644 --- a/hardware/modules/iob_soc_cache_system/iob_soc_cache_system.py +++ b/hardware/modules/iob_soc_cache_system/iob_soc_cache_system.py @@ -66,7 +66,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -74,7 +74,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "i_bus", + "name": "i_bus_s", "interface": { "type": "iob", "subtype": "slave", @@ -85,7 +85,7 @@ def setup(py_params_dict): "descr": "Instruction bus", }, { - "name": "d_bus", + "name": "d_bus_s", "interface": { "type": "iob", "subtype": "slave", @@ -96,7 +96,7 @@ def setup(py_params_dict): "descr": "Data bus", }, { - "name": "axi", + "name": "axi_m", "interface": { "type": "axi", "subtype": "master", @@ -154,11 +154,11 @@ def setup(py_params_dict): "name": "iob_i_d_into_l2_merge", "instance_name": "iob_i_d_into_l2_merge", "connect": { - "clk_en_rst": "clk_en_rst", - "reset": "never_reset", + "clk_en_rst_s": "clk_en_rst_s", + "reset_i": "never_reset", "input_0": "dcache", "input_1": "icache", - "output": "l2cache", + "output_m": "l2cache", }, "num_inputs": 2, "addr_w": MEM_ADDR_W, diff --git a/hardware/modules/iob_soc_sim_wrapper/iob_soc_sim_wrapper.py b/hardware/modules/iob_soc_sim_wrapper/iob_soc_sim_wrapper.py index a6622b635..bd53e5017 100644 --- a/hardware/modules/iob_soc_sim_wrapper/iob_soc_sim_wrapper.py +++ b/hardware/modules/iob_soc_sim_wrapper/iob_soc_sim_wrapper.py @@ -45,7 +45,7 @@ def setup(py_params_dict): # attributes_dict["ports"] = [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "descr": "Clock, clock enable and reset", "interface": { "type": "clk_en_rst", @@ -53,7 +53,7 @@ def setup(py_params_dict): }, }, { - "name": "uart", + "name": "uart_s", "descr": "Testbench uart csrs interface", "interface": { "type": "iob", @@ -66,7 +66,7 @@ def setup(py_params_dict): if params["use_ethernet"]: attributes_dict["ports"] += [ { - "name": "ethernet", + "name": "ethernet_s", "descr": "Testbench ethernet csrs interface", "interface": { "type": "iob", @@ -186,9 +186,9 @@ def setup(py_params_dict): "AXI_DATA_W": "AXI_DATA_W", }, "connect": { - "clk_en_rst": "clk_en_rst", - "rs232": "rs232", - "axi": "axi", + "clk_en_rst_s": "clk_en_rst_s", + "rs232_m": "rs232", + "axi_m": "axi", }, "dest_dir": "hardware/common_src", "iob_soc_params": params, @@ -200,9 +200,9 @@ def setup(py_params_dict): "instance_description": "Testbench uart core", "csr_if": "iob", "connect": { - "clk_en_rst": "clk_en_rst", - "cbus": "uart", - "rs232": "rs232_invert", + "clk_en_rst_s": "clk_en_rst_s", + "cbus_s": "uart_s", + "rs232_m": "rs232_invert", }, }, { @@ -216,10 +216,10 @@ def setup(py_params_dict): "AXI_DATA_W": "AXI_DATA_W", }, "connect": { - "clk": "clk", - "rst": "rst", - "s0_axi": "axi", - "m0_axi": "memory_axi", + "clk_i": "clk", + "rst_i": "rst", + "s0_axi_s": "axi", + "m0_axi_m": "memory_axi", }, "num_slaves": 1, "num_masters": 1, @@ -234,9 +234,9 @@ def setup(py_params_dict): "DATA_WIDTH": "AXI_DATA_W", }, "connect": { - "clk": "clk", - "rst": "rst", - "axi": "memory_axi", + "clk_i": "clk", + "rst_i": "rst", + "axi_s": "memory_axi", }, }, ] @@ -258,7 +258,7 @@ def setup(py_params_dict): "AXI_DATA_W": "AXI_DATA_W", }, "connect": { - "clk_en_rst": "clk_en_rst", + "clk_en_rst": "clk_en_rst_s", "iob": "ethernet", "axi": "eth_axi", "mii": "eth_mii_invert", diff --git a/iob_soc.py b/iob_soc.py index 665af6e81..8c9361964 100755 --- a/iob_soc.py +++ b/iob_soc.py @@ -30,9 +30,9 @@ def setup(py_params_dict): "instance_description": "UART peripheral", "parameters": {}, "connect": { - "clk_en_rst": "clk_en_rst", - "cbus": "uart0_cbus", - "rs232": "rs232", + "clk_en_rst_s": "clk_en_rst_s", + "cbus_s": "uart0_cbus", + "rs232_m": "rs232_m", }, }, { @@ -41,8 +41,8 @@ def setup(py_params_dict): "instance_description": "Timer peripheral", "parameters": {}, "connect": { - "clk_en_rst": "clk_en_rst", - "cbus": "timer0_cbus", + "clk_en_rst_s": "clk_en_rst_s", + "cbus_s": "timer0_cbus", }, }, # NOTE: Instantiate other peripherals here @@ -168,7 +168,7 @@ def setup(py_params_dict): } attributes_dict["ports"] = [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "descr": "Clock, clock enable and reset", "interface": { "type": "clk_en_rst", @@ -197,7 +197,7 @@ def setup(py_params_dict): ], }, { - "name": "axi", + "name": "axi_m", "descr": "AXI master interface for memory", "interface": { "type": "axi", @@ -211,7 +211,7 @@ def setup(py_params_dict): }, # Peripheral IO ports { - "name": "rs232", + "name": "rs232_m", "descr": "iob-soc uart interface", "interface": { "type": "rs232", @@ -378,13 +378,13 @@ def setup(py_params_dict): "AXI_LEN_W": "AXI_LEN_W", }, "connect": { - "clk_en_rst": "clk_en_rst", - "rst": "rst", - "i_bus": "cpu_ibus", - "d_bus": "cpu_dbus", - "plic_interrupts": "interrupts", - "plic_cbus": "plic_cbus", - "clint_cbus": "clint_cbus", + "clk_en_rst_s": "clk_en_rst_s", + "rst_i": "rst", + "i_bus_m": "cpu_ibus", + "d_bus_m": "cpu_dbus", + "plic_interrupts_i": "interrupts", + "plic_cbus_s": "plic_cbus", + "clint_cbus_s": "clint_cbus", }, }, { @@ -398,13 +398,13 @@ def setup(py_params_dict): "AXI_DATA_W": "AXI_DATA_W", }, "connect": { - "clk": "clk", - "rst": "rst", - "s0_axi": "cpu_ibus", - "s1_axi": "cpu_dbus", - "mem_axi": "axi", - "bootrom_axi": "bootrom_cbus", - "peripherals_axi": "axi_periphs_cbus", + "clk_i": "clk", + "rst_i": "rst", + "s0_axi_s": "cpu_ibus", + "s1_axi_s": "cpu_dbus", + "mem_axi_m": "axi_m", + "bootrom_axi_m": "bootrom_cbus", + "peripherals_axi_m": "axi_periphs_cbus", }, "num_slaves": 2, "masters": { @@ -424,8 +424,8 @@ def setup(py_params_dict): "AXI_LEN_W": "AXI_LEN_W", }, "connect": { - "clk_en_rst": "clk_en_rst", - "cbus": "bootrom_cbus", + "clk_en_rst_s": "clk_en_rst_s", + "cbus_s": "bootrom_cbus", "ext_rom_bus": "rom_bus", }, "bootrom_addr_w": params["bootrom_addr_w"], @@ -441,8 +441,8 @@ def setup(py_params_dict): "AXI_LEN_W": "AXI_LEN_W", }, "connect": { - "axi": "axi_periphs_cbus", - "axil": "axil_periphs_cbus", + "axi_s": "axi_periphs_cbus", + "axil_m": "axil_periphs_cbus", }, }, { @@ -451,14 +451,14 @@ def setup(py_params_dict): "instance_name": "iob_axil_pbus_split", "instance_description": "Split between peripherals", "connect": { - "clk_en_rst": "clk_en_rst", - "reset": "split_reset", - "input": "axil_periphs_cbus", - "output_0": "uart0_cbus", - "output_1": "timer0_cbus", + "clk_en_rst_s": "clk_en_rst_s", + "reset_i": "split_reset", + "input_s": "axil_periphs_cbus", + "output_0_m": "uart0_cbus", + "output_1_m": "timer0_cbus", # NOTE: Connect other peripherals here - "output_2": "clint_cbus", - "output_3": "plic_cbus", + "output_2_m": "clint_cbus", + "output_3_m": "plic_cbus", }, "num_outputs": num_peripherals, "addr_w": params["addr_w"] - 1, diff --git a/lib/hardware/altera/altera_alt_ddr3/altera_alt_ddr3.py b/lib/hardware/altera/altera_alt_ddr3/altera_alt_ddr3.py index e322a0c49..de3aa0cca 100644 --- a/lib/hardware/altera/altera_alt_ddr3/altera_alt_ddr3.py +++ b/lib/hardware/altera/altera_alt_ddr3/altera_alt_ddr3.py @@ -44,7 +44,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_rst", + "name": "clk_rst_i", "descr": "Clock and reset", "signals": [ {"name": "clk", "direction": "input", "width": "1"}, @@ -86,7 +86,7 @@ def setup(py_params_dict): for i in range(N_SLAVES): attributes_dict["ports"] += [ { - "name": f"s{i}_axi", + "name": f"s{i}_axi_s", "interface": { "type": "axi", "subtype": "slave", diff --git a/lib/hardware/amd/xilinx_axi_interconnect/xilinx_axi_interconnect.py b/lib/hardware/amd/xilinx_axi_interconnect/xilinx_axi_interconnect.py index 6e4aad09e..29f4f5695 100644 --- a/lib/hardware/amd/xilinx_axi_interconnect/xilinx_axi_interconnect.py +++ b/lib/hardware/amd/xilinx_axi_interconnect/xilinx_axi_interconnect.py @@ -54,7 +54,7 @@ def setup(py_params_dict): # "ports": [ { - "name": "clk_rst_i", + "name": "clk_rst_s", "descr": "Clock and reset inputs", "interface": { "type": "clk_rst", @@ -74,7 +74,7 @@ def setup(py_params_dict): ], }, { - "name": f"s{i}_axi", + "name": f"s{i}_axi_s", "interface": { "type": "axi", "subtype": "slave", @@ -98,7 +98,7 @@ def setup(py_params_dict): ], }, { - "name": f"m{i}_axi", + "name": f"m{i}_axi_m", "interface": { "type": "axi", "subtype": "master", diff --git a/lib/hardware/amd/xilinx_clock_wizard/xilinx_clock_wizard.py b/lib/hardware/amd/xilinx_clock_wizard/xilinx_clock_wizard.py index 6ca75b9cc..6fa5d9ffa 100644 --- a/lib/hardware/amd/xilinx_clock_wizard/xilinx_clock_wizard.py +++ b/lib/hardware/amd/xilinx_clock_wizard/xilinx_clock_wizard.py @@ -63,7 +63,7 @@ def setup(py_params_dict): "core_name": "iob_reset_sync", "instance_name": "rst_sync", "connect": { - "clk_rst": "reset_sync_clk_rst", + "clk_rst_s": "reset_sync_clk_rst", "arst_o": "reset_sync_rst_out", }, }, diff --git a/lib/hardware/amd/xilinx_ddr4_ctrl/xilinx_ddr4_ctrl.py b/lib/hardware/amd/xilinx_ddr4_ctrl/xilinx_ddr4_ctrl.py index 5f3ea5816..467456050 100644 --- a/lib/hardware/amd/xilinx_ddr4_ctrl/xilinx_ddr4_ctrl.py +++ b/lib/hardware/amd/xilinx_ddr4_ctrl/xilinx_ddr4_ctrl.py @@ -45,7 +45,7 @@ def setup(py_params_dict): # Ports # { - "name": "clk_rst", + "name": "clk_rst_i", "signals": [ {"name": "clk_p", "direction": "input", "width": "1"}, {"name": "clk_n", "direction": "input", "width": "1"}, @@ -53,7 +53,7 @@ def setup(py_params_dict): ], }, { - "name": "ui_clk_out", + "name": "ui_clk_o", "signals": [ {"name": "clkout", "direction": "output", "width": "1"}, ], @@ -68,7 +68,7 @@ def setup(py_params_dict): ], }, { - "name": "axi", + "name": "axi_s", "interface": { "type": "axi", "subtype": "slave", diff --git a/lib/hardware/arith_logic/accumulators/iob_acc/iob_acc.py b/lib/hardware/arith_logic/accumulators/iob_acc/iob_acc.py deleted file mode 100644 index 7ec94b083..000000000 --- a/lib/hardware/arith_logic/accumulators/iob_acc/iob_acc.py +++ /dev/null @@ -1,120 +0,0 @@ -def setup(py_params_dict): - attributes_dict = { - "original_name": "iob_acc", - "name": "iob_acc", - "version": "0.1", - "confs": [ - { - "name": "DATA_W", - "type": "P", - "val": "21", - "min": "NA", - "max": "NA", - "descr": "Data bus width", - }, - { - "name": "RST_VAL", - "type": "P", - "val": "{DATA_W{1'b0}}", - "min": "NA", - "max": "NA", - "descr": "Reset value.", - }, - ], - "ports": [ - { - "name": "clk_en_rst", - "interface": { - "type": "clk_en_rst", - "subtype": "slave", - }, - "descr": "clock, clock enable and reset", - }, - { - "name": "en_rst", - "descr": "Enable and Synchronous reset interface", - "signals": [ - { - "name": "en", - "direction": "input", - "width": 1, - "descr": "Enable input", - }, - { - "name": "rst", - "direction": "input", - "width": 1, - "descr": "Synchronous reset input", - }, - ], - }, - { - "name": "incr", - "descr": "Input port", - "signals": [ - { - "name": "incr", - "width": "DATA_W", - "direction": "input", - }, - ], - }, - { - "name": "data_o", - "descr": "Output port", - "signals": [ - { - "name": "data", - "width": "DATA_W", - "direction": "output", - }, - ], - }, - { - "name": "data_nxt", - "descr": "Output port", - "signals": [ - { - "name": "data_nxt", - "width": "DATA_W+1", - "direction": "output", - }, - ], - }, - ], - "wires": [ - { - "name": "data_int", - "descr": "data_int wire", - "signals": [ - {"name": "data_int", "width": "DATA_W"}, - ], - }, - ], - "blocks": [ - { - "core_name": "iob_reg_re", - "instance_name": "reg0", - "parameters": { - "DATA_W": "DATA_W", - "RST_VAL": "RST_VAL", - }, - "connect": { - "clk_en_rst": "clk_en_rst", - "en_rst": "en_rst", - "data_i": "data_int", - "data_o": "data_o", - }, - }, - ], - "snippets": [ - { - "verilog_code": f""" - assign data_nxt_o = data_o + incr_i; - assign data_int = data_nxt_o[DATA_W-1:0]; - """, - }, - ], - } - - return attributes_dict diff --git a/lib/hardware/arith_logic/accumulators/iob_acc_ld/iob_acc_ld.py b/lib/hardware/arith_logic/accumulators/iob_acc_ld/iob_acc_ld.py deleted file mode 100644 index bd0bee510..000000000 --- a/lib/hardware/arith_logic/accumulators/iob_acc_ld/iob_acc_ld.py +++ /dev/null @@ -1,142 +0,0 @@ -def setup(py_params_dict): - attributes_dict = { - "original_name": "iob_acc_ld", - "name": "iob_acc_ld", - "version": "0.1", - "confs": [ - { - "name": "DATA_W", - "type": "P", - "val": "21", - "min": "NA", - "max": "NA", - "descr": "Data bus width", - }, - { - "name": "RST_VAL", - "type": "P", - "val": "{DATA_W{1'b0}}", - "min": "NA", - "max": "NA", - "descr": "Reset value.", - }, - ], - "ports": [ - { - "name": "clk_en_rst", - "interface": { - "type": "clk_en_rst", - "subtype": "slave", - }, - "descr": "clock, clock enable and reset", - }, - { - "name": "en_rst", - "descr": "Enable and Synchronous reset interface", - "signals": [ - { - "name": "en", - "direction": "input", - "width": 1, - "descr": "Enable input", - }, - { - "name": "rst", - "direction": "input", - "width": 1, - "descr": "Synchronous reset input", - }, - ], - }, - { - "name": "ld_i", - "descr": "Input port", - "signals": [ - { - "name": "ld", - "width": 1, - "direction": "input", - }, - ], - }, - { - "name": "ld_val_i", - "descr": "Input port", - "signals": [ - { - "name": "ld_val", - "width": "DATA_W", - "direction": "input", - }, - ], - }, - { - "name": "incr_i", - "descr": "Input port", - "signals": [ - { - "name": "incr", - "width": "DATA_W", - "direction": "input", - }, - ], - }, - { - "name": "data_o", - "descr": "Output port", - "signals": [ - { - "name": "data", - "width": "DATA_W", - "direction": "output", - }, - ], - }, - { - "name": "data_nxt_o", - "descr": "Output port", - "signals": [ - { - "name": "data_nxt", - "width": "DATA_W+1", - "direction": "output", - }, - ], - }, - ], - "wires": [ - { - "name": "data_int", - "descr": "data_int wire", - "signals": [ - {"name": "data_int", "width": "DATA_W+1"}, - ], - }, - ], - "blocks": [ - { - "core_name": "iob_reg_re", - "instance_name": "reg0", - "parameters": { - "DATA_W": "DATA_W+1", - "RST_VAL": "RST_VAL", - }, - "connect": { - "clk_en_rst": "clk_en_rst", - "en_rst": "en_rst", - "data_i": "data_nxt_o", - "data_o": "data_int", - }, - }, - ], - "snippets": [ - { - "verilog_code": """ - assign data_nxt_o = ld_i ? ld_val_i : data_o + incr_i; - assign data_o = data_int[DATA_W-1:0]; - """, - }, - ], - } - - return attributes_dict diff --git a/lib/hardware/arith_logic/counter/iob_counter/iob_counter.py b/lib/hardware/arith_logic/counter/iob_counter/iob_counter.py index 753023f49..34c6a5166 100644 --- a/lib/hardware/arith_logic/counter/iob_counter/iob_counter.py +++ b/lib/hardware/arith_logic/counter/iob_counter/iob_counter.py @@ -23,7 +23,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -31,7 +31,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "en_rst", + "name": "en_rst_i", "descr": "Enable and Synchronous reset interface", "signals": [ { @@ -74,8 +74,8 @@ def setup(py_params_dict): "RST_VAL": "RST_VAL", }, "connect": { - "clk_en_rst": "clk_en_rst", - "en_rst": "en_rst", + "clk_en_rst_s": "clk_en_rst_s", + "en_rst_i": "en_rst_i", "data_i": "data_int", "data_o": "data_o", }, diff --git a/lib/hardware/arith_logic/counter/iob_counter_ld/iob_counter_ld.py b/lib/hardware/arith_logic/counter/iob_counter_ld/iob_counter_ld.py index 551920788..8f0bc674d 100644 --- a/lib/hardware/arith_logic/counter/iob_counter_ld/iob_counter_ld.py +++ b/lib/hardware/arith_logic/counter/iob_counter_ld/iob_counter_ld.py @@ -23,7 +23,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -31,7 +31,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "en_rst", + "name": "en_rst_i", "descr": "Enable and Synchronous reset interface", "signals": [ { @@ -88,8 +88,8 @@ def setup(py_params_dict): "RST_VAL": "RST_VAL", }, "connect": { - "clk_en_rst": "clk_en_rst", - "en_rst": "en_rst", + "clk_en_rst_s": "clk_en_rst_s", + "en_rst_i": "en_rst_i", "data_i": "data_int", "data_o": "data_o", }, diff --git a/lib/hardware/arith_logic/counter/iob_modcnt/iob_modcnt.py b/lib/hardware/arith_logic/counter/iob_modcnt/iob_modcnt.py index 4d2c9b30a..cf07dab6d 100644 --- a/lib/hardware/arith_logic/counter/iob_modcnt/iob_modcnt.py +++ b/lib/hardware/arith_logic/counter/iob_modcnt/iob_modcnt.py @@ -23,7 +23,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -31,7 +31,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "en_rst", + "name": "en_rst_i", "descr": "Enable and Synchronous reset interface", "signals": [ { @@ -88,8 +88,8 @@ def setup(py_params_dict): "RST_VAL": "RST_VAL", }, "connect": { - "clk_en_rst": "clk_en_rst", - "en_rst": "en_rst", + "clk_en_rst_s": "clk_en_rst_s", + "en_rst_i": "en_rst_i", "ld_i": "ld_count", "ld_val_i": "ld_val", "data_o": "data_o", diff --git a/lib/hardware/arith_logic/div/iob_div_pipe/iob_div_pipe.py b/lib/hardware/arith_logic/div/iob_div_pipe/iob_div_pipe.py index 30c5502b2..20fbf9936 100755 --- a/lib/hardware/arith_logic/div/iob_div_pipe/iob_div_pipe.py +++ b/lib/hardware/arith_logic/div/iob_div_pipe/iob_div_pipe.py @@ -23,7 +23,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk", + "name": "clk_i", "descr": "Clock", "signals": [ { diff --git a/lib/hardware/arith_logic/div/iob_div_subshift/iob_div_subshift.py b/lib/hardware/arith_logic/div/iob_div_subshift/iob_div_subshift.py index 194842e4f..ea64f72f8 100755 --- a/lib/hardware/arith_logic/div/iob_div_subshift/iob_div_subshift.py +++ b/lib/hardware/arith_logic/div/iob_div_subshift/iob_div_subshift.py @@ -15,7 +15,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", diff --git a/lib/hardware/arith_logic/div/iob_div_subshift_frac/iob_div_subshift_frac.py b/lib/hardware/arith_logic/div/iob_div_subshift_frac/iob_div_subshift_frac.py index 778a79bdc..ccd869b7a 100755 --- a/lib/hardware/arith_logic/div/iob_div_subshift_frac/iob_div_subshift_frac.py +++ b/lib/hardware/arith_logic/div/iob_div_subshift_frac/iob_div_subshift_frac.py @@ -15,7 +15,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -149,7 +149,7 @@ def setup(py_params_dict): "RST_VAL": "1'b0", }, "connect": { - "clk_en_rst": "clk_en_rst", + "clk_en_rst_s": "clk_en_rst_s", "data_i": "divisor_i", "data_o": "divisor_reg", }, @@ -161,7 +161,7 @@ def setup(py_params_dict): "DATA_W": "DATA_W", }, "connect": { - "clk_en_rst": "clk_en_rst", + "clk_en_rst_s": "clk_en_rst_s", "status": "status", "div": "div_frac", }, diff --git a/lib/hardware/arith_logic/iob_edge_detect/iob_edge_detect.py b/lib/hardware/arith_logic/iob_edge_detect/iob_edge_detect.py index 8c3eb032d..b9260be17 100644 --- a/lib/hardware/arith_logic/iob_edge_detect/iob_edge_detect.py +++ b/lib/hardware/arith_logic/iob_edge_detect/iob_edge_detect.py @@ -6,7 +6,7 @@ def setup(py_params_dict): "generate_hw": False, "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", diff --git a/lib/hardware/buses/apb2iob/apb2iob.py b/lib/hardware/buses/apb2iob/apb2iob.py index 28b705752..05685a554 100644 --- a/lib/hardware/buses/apb2iob/apb2iob.py +++ b/lib/hardware/buses/apb2iob/apb2iob.py @@ -6,7 +6,7 @@ def setup(py_params_dict): "generate_hw": False, "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -14,7 +14,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "apb", + "name": "apb_s", "interface": { "type": "apb", "subtype": "slave", @@ -22,7 +22,7 @@ def setup(py_params_dict): "descr": "APB interface", }, { - "name": "iob", + "name": "iob_m", "interface": { "type": "iob", "subtype": "master", diff --git a/lib/hardware/buses/axi2axil/axi2axil.py b/lib/hardware/buses/axi2axil/axi2axil.py index 988c6458d..b89b8b8c5 100644 --- a/lib/hardware/buses/axi2axil/axi2axil.py +++ b/lib/hardware/buses/axi2axil/axi2axil.py @@ -43,7 +43,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "axi", + "name": "axi_s", "descr": "AXI slave interface to connect to external master", "interface": { "type": "axi", @@ -55,7 +55,7 @@ def setup(py_params_dict): }, }, { - "name": "axil", + "name": "axil_m", "descr": "AXI Lite master interface to connect to external slave", "interface": { "type": "axil", diff --git a/lib/hardware/buses/axi2iob/axi2iob.py b/lib/hardware/buses/axi2iob/axi2iob.py index 65b352879..ed985bb20 100644 --- a/lib/hardware/buses/axi2iob/axi2iob.py +++ b/lib/hardware/buses/axi2iob/axi2iob.py @@ -40,7 +40,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -48,7 +48,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "axi", + "name": "axi_s", "descr": "Slave AXI interface", "interface": { "type": "axi", @@ -59,7 +59,7 @@ def setup(py_params_dict): }, }, { - "name": "iob", + "name": "iob_m", "descr": "Master IOb interface", "interface": { "type": "iob", diff --git a/lib/hardware/buses/axi_interconnect/axi_interconnect.py b/lib/hardware/buses/axi_interconnect/axi_interconnect.py index b4d4b0109..2facfb6e1 100644 --- a/lib/hardware/buses/axi_interconnect/axi_interconnect.py +++ b/lib/hardware/buses/axi_interconnect/axi_interconnect.py @@ -56,7 +56,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk", + "name": "clk_i", "descr": "Clock", "signals": [ { @@ -67,7 +67,7 @@ def setup(py_params_dict): ], }, { - "name": "rst", + "name": "rst_i", "descr": "Synchronous reset", "signals": [ { @@ -78,7 +78,7 @@ def setup(py_params_dict): ], }, { - "name": "s_axi", + "name": "s_axi_s", "interface": { "type": "axi", "subtype": "slave", @@ -98,7 +98,7 @@ def setup(py_params_dict): ], }, { - "name": "m_axi", + "name": "m_axi_m", "interface": { "type": "axi", "subtype": "master", diff --git a/lib/hardware/buses/axi_interconnect_wrapper/axi_interconnect_wrapper.py b/lib/hardware/buses/axi_interconnect_wrapper/axi_interconnect_wrapper.py index 7764e9bc4..b0e1d8d29 100644 --- a/lib/hardware/buses/axi_interconnect_wrapper/axi_interconnect_wrapper.py +++ b/lib/hardware/buses/axi_interconnect_wrapper/axi_interconnect_wrapper.py @@ -101,7 +101,7 @@ def setup(py_params_dict): # "ports": [ { - "name": "clk", + "name": "clk_i", "descr": "Clock", "signals": [ { @@ -112,7 +112,7 @@ def setup(py_params_dict): ], }, { - "name": "rst", + "name": "rst_i", "descr": "Synchronous reset", "signals": [ { @@ -128,7 +128,7 @@ def setup(py_params_dict): for i in range(N_SLAVES): slave_axi_ports += [ { - "name": f"s{i}_axi", + "name": f"s{i}_axi_s", "descr": f"Slave {i} interface", "interface": { "type": "axi", @@ -146,7 +146,7 @@ def setup(py_params_dict): for name, width in MASTERS.items(): master_axi_ports += [ { - "name": f"{name}_axi", + "name": f"{name}_axi_m", "descr": f"Master '{name}' axi interface", "interface": { "type": "axi", @@ -225,10 +225,10 @@ def setup(py_params_dict): "M_ADDR_WIDTH": master_addr_w_parameter, }, "connect": { - "clk": "clk", - "rst": "rst", - "s_axi": "interconnect_s_axi", - "m_axi": "interconnect_m_axi", + "clk_i": "clk_i", + "rst_i": "rst_i", + "s_axi_s": "interconnect_s_axi", + "m_axi_m": "interconnect_m_axi", }, }, ] diff --git a/lib/hardware/buses/axil2iob/axil2iob.py b/lib/hardware/buses/axil2iob/axil2iob.py index 1a05a9178..68c2f9bf4 100644 --- a/lib/hardware/buses/axil2iob/axil2iob.py +++ b/lib/hardware/buses/axil2iob/axil2iob.py @@ -6,7 +6,7 @@ def setup(py_params_dict): "generate_hw": False, "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -14,7 +14,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "axil", + "name": "axil_s", "interface": { "type": "axil", "subtype": "slave", @@ -22,7 +22,7 @@ def setup(py_params_dict): "descr": "AXIL interface", }, { - "name": "iob", + "name": "iob_m", "interface": { "type": "iob", "subtype": "master", diff --git a/lib/hardware/buses/axis2axi/axis2axi.py b/lib/hardware/buses/axis2axi/axis2axi.py index a5b7ac0db..10b89a3f6 100644 --- a/lib/hardware/buses/axis2axi/axis2axi.py +++ b/lib/hardware/buses/axis2axi/axis2axi.py @@ -6,7 +6,7 @@ def setup(py_params_dict): "generate_hw": False, "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -14,7 +14,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "rst", + "name": "rst_i", "descr": "Synchronous reset interface", "signals": [ { @@ -128,7 +128,7 @@ def setup(py_params_dict): ], }, { - "name": "axi", + "name": "axi_m", "interface": { "type": "axi", "subtype": "master", diff --git a/lib/hardware/buses/axis2axi/submodules/axis2axi_in/axis2axi_in.py b/lib/hardware/buses/axis2axi/submodules/axis2axi_in/axis2axi_in.py index 4db37a10b..38efe336a 100644 --- a/lib/hardware/buses/axis2axi/submodules/axis2axi_in/axis2axi_in.py +++ b/lib/hardware/buses/axis2axi/submodules/axis2axi_in/axis2axi_in.py @@ -6,7 +6,7 @@ def setup(py_params_dict): "generate_hw": False, "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -14,7 +14,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "rst", + "name": "rst_i", "descr": "Synchronous reset interface", "signals": [ { @@ -74,7 +74,7 @@ def setup(py_params_dict): ], }, { - "name": "axi_write", + "name": "axi_write_m", "interface": { "type": "axi_write", "subtype": "master", diff --git a/lib/hardware/buses/axis2axi/submodules/axis2axi_out/axis2axi_out.py b/lib/hardware/buses/axis2axi/submodules/axis2axi_out/axis2axi_out.py index bdcf896ad..1d3898273 100644 --- a/lib/hardware/buses/axis2axi/submodules/axis2axi_out/axis2axi_out.py +++ b/lib/hardware/buses/axis2axi/submodules/axis2axi_out/axis2axi_out.py @@ -6,7 +6,7 @@ def setup(py_params_dict): "generate_hw": False, "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -14,7 +14,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "rst", + "name": "rst_i", "descr": "Synchronous reset interface", "signals": [ { @@ -80,7 +80,7 @@ def setup(py_params_dict): ], }, { - "name": "axi_read", + "name": "axi_read_m", "interface": { "type": "axi_read", "subtype": "master", diff --git a/lib/hardware/buses/iob2apb/iob2apb.py b/lib/hardware/buses/iob2apb/iob2apb.py index 55c31186e..682b2a36a 100644 --- a/lib/hardware/buses/iob2apb/iob2apb.py +++ b/lib/hardware/buses/iob2apb/iob2apb.py @@ -39,7 +39,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -47,7 +47,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "iob", + "name": "iob_s", "interface": { "type": "iob", "subtype": "slave", @@ -55,7 +55,7 @@ def setup(py_params_dict): "descr": "CPU native interface", }, { - "name": "apb", + "name": "apb_m", "interface": { "type": "apb", "subtype": "master", @@ -116,7 +116,7 @@ def setup(py_params_dict): "RST_VAL": 0, }, "connect": { - "clk_en_rst": "clk_en_rst", + "clk_en_rst_s": "clk_en_rst_s", "data_i": "pc_nxt_int", "data_o": "pc_int", }, @@ -129,7 +129,7 @@ def setup(py_params_dict): "RST_VAL": 0, }, "connect": { - "clk_en_rst": "clk_en_rst", + "clk_en_rst_s": "clk_en_rst_s", "data_i": "apb_rdata_int", "data_o": "iob_rdata_int", }, @@ -142,7 +142,7 @@ def setup(py_params_dict): "RST_VAL": 0, }, "connect": { - "clk_en_rst": "clk_en_rst", + "clk_en_rst_s": "clk_en_rst_s", "data_i": "apb_ready_int", "data_o": "iob_rvalid_int", }, diff --git a/lib/hardware/buses/iob_asym_converter/iob_asym_converter.py b/lib/hardware/buses/iob_asym_converter/iob_asym_converter.py index 21d246090..c38bb32a7 100644 --- a/lib/hardware/buses/iob_asym_converter/iob_asym_converter.py +++ b/lib/hardware/buses/iob_asym_converter/iob_asym_converter.py @@ -6,7 +6,7 @@ def setup(py_params_dict): "generate_hw": False, "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -14,7 +14,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "rst", + "name": "rst_i", "descr": "Synchronous reset interface", "signals": [ { @@ -26,7 +26,7 @@ def setup(py_params_dict): ], }, { - "name": "write", + "name": "write_i", "descr": "Write interface", "signals": [ { diff --git a/lib/hardware/buses/iob_axil_split/iob_axil_split.py b/lib/hardware/buses/iob_axil_split/iob_axil_split.py index 0c1c7328a..4d1ac31cc 100644 --- a/lib/hardware/buses/iob_axil_split/iob_axil_split.py +++ b/lib/hardware/buses/iob_axil_split/iob_axil_split.py @@ -48,7 +48,7 @@ def setup(py_params_dict): "version": "0.1", "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -56,7 +56,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and async reset", }, { - "name": "reset", + "name": "reset_i", "descr": "Reset signal", "signals": [ { @@ -67,7 +67,7 @@ def setup(py_params_dict): ], }, { - "name": "input", + "name": "input_s", "interface": { "type": "axil", "subtype": "slave", @@ -83,7 +83,7 @@ def setup(py_params_dict): for port_idx in range(NUM_OUTPUTS): attributes_dict["ports"].append( { - "name": f"output_{port_idx}", + "name": f"output_{port_idx}_m", "interface": { "type": "axil", "subtype": "master", @@ -190,8 +190,8 @@ def setup(py_params_dict): "RST_VAL": f"{NBITS}'b0", }, "connect": { - "clk_en_rst": "clk_en_rst", - "en_rst": "sel_reg_en_rst", + "clk_en_rst_s": "clk_en_rst_s", + "en_rst_i": "sel_reg_en_rst", "data_i": "sel_reg_data_i", "data_o": "sel_reg_data_o", }, diff --git a/lib/hardware/buses/iob_axistream_in/iob_axistream_in.py b/lib/hardware/buses/iob_axistream_in/iob_axistream_in.py index 0b96a617f..8d79140b1 100755 --- a/lib/hardware/buses/iob_axistream_in/iob_axistream_in.py +++ b/lib/hardware/buses/iob_axistream_in/iob_axistream_in.py @@ -41,7 +41,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -49,7 +49,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "iob", + "name": "iob_s", "interface": { "type": "iob", "subtype": "slave", @@ -59,7 +59,7 @@ def setup(py_params_dict): "descr": "CPU native interface", }, { - "name": "interrupt", + "name": "interrupt_o", "descr": "Interrupt signal", "signals": [ { @@ -342,9 +342,9 @@ def setup(py_params_dict): }, ], "connect": { - "clk_en_rst": "clk_en_rst", - "control_if": "iob", - "csrs_iob_output": "csrs_iob", + "clk_en_rst_s": "clk_en_rst_s", + "control_if_s": "iob_s", + "csrs_iob_o": "csrs_iob", # Register interfaces "soft_reset": "soft_reset", "enable": "enable", diff --git a/lib/hardware/buses/iob_axistream_out/iob_axistream_out.py b/lib/hardware/buses/iob_axistream_out/iob_axistream_out.py index 0d30c5348..6588828ee 100755 --- a/lib/hardware/buses/iob_axistream_out/iob_axistream_out.py +++ b/lib/hardware/buses/iob_axistream_out/iob_axistream_out.py @@ -41,7 +41,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -49,7 +49,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "iob", + "name": "iob_s", "interface": { "type": "iob", "subtype": "slave", @@ -59,7 +59,7 @@ def setup(py_params_dict): "descr": "CPU native interface", }, { - "name": "interrupt", + "name": "interrupt_o", "descr": "Interrupt signal", "signals": [ { @@ -321,9 +321,9 @@ def setup(py_params_dict): }, ], "connect": { - "clk_en_rst": "clk_en_rst", - "control_if": "iob", - "csrs_iob_output": "csrs_iob", + "clk_en_rst_s": "clk_en_rst_s", + "control_if_s": "iob_s", + "csrs_iob_o": "csrs_iob", # Register interfaces "soft_reset": "soft_reset", "enable": "enable", diff --git a/lib/hardware/buses/iob_bus_demux/iob_bus_demux.py b/lib/hardware/buses/iob_bus_demux/iob_bus_demux.py index fbc0478f8..dbe56c8fd 100644 --- a/lib/hardware/buses/iob_bus_demux/iob_bus_demux.py +++ b/lib/hardware/buses/iob_bus_demux/iob_bus_demux.py @@ -6,7 +6,7 @@ def setup(py_params_dict): "generate_hw": False, "ports": [ { - "name": "clk_rst", + "name": "clk_rst_s", "interface": { "type": "clk_rst", "subtype": "slave", diff --git a/lib/hardware/buses/iob_merge/iob_merge.py b/lib/hardware/buses/iob_merge/iob_merge.py index faf6214fa..cf4aed24b 100644 --- a/lib/hardware/buses/iob_merge/iob_merge.py +++ b/lib/hardware/buses/iob_merge/iob_merge.py @@ -19,7 +19,7 @@ def setup(py_params_dict): "version": "0.1", "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -27,7 +27,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and async reset", }, { - "name": "reset", + "name": "reset_i", "descr": "Reset signal", "signals": [ { @@ -38,7 +38,7 @@ def setup(py_params_dict): ], }, { - "name": "output", + "name": "output_m", "interface": { "type": "iob", "subtype": "master", @@ -54,7 +54,7 @@ def setup(py_params_dict): for port_idx in range(NUM_INPUTS): attributes_dict["ports"].append( { - "name": f"input_{port_idx}", + "name": f"input_{port_idx}_s", "interface": { "type": "iob", "subtype": "slave", @@ -228,8 +228,8 @@ def setup(py_params_dict): "RST_VAL": f"{NBITS}'b0", }, "connect": { - "clk_en_rst": "clk_en_rst", - "rst": "sel_reg_rst", + "clk_en_rst_s": "clk_en_rst_s", + "rst_i": "sel_reg_rst", "data_i": "sel_reg_data_i", "data_o": "sel_reg_data_o", }, diff --git a/lib/hardware/buses/iob_split/iob_split.py b/lib/hardware/buses/iob_split/iob_split.py index 4a8d32c20..c6a2f60e3 100644 --- a/lib/hardware/buses/iob_split/iob_split.py +++ b/lib/hardware/buses/iob_split/iob_split.py @@ -19,7 +19,7 @@ def setup(py_params_dict): "version": "0.1", "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -27,7 +27,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and async reset", }, { - "name": "reset", + "name": "reset_i", "descr": "Reset signal", "signals": [ { @@ -38,7 +38,7 @@ def setup(py_params_dict): ], }, { - "name": "input", + "name": "input_s", "interface": { "type": "iob", "subtype": "slave", @@ -54,7 +54,7 @@ def setup(py_params_dict): for port_idx in range(NUM_OUTPUTS): attributes_dict["ports"].append( { - "name": f"output_{port_idx}", + "name": f"output_{port_idx}_m", "interface": { "type": "iob", "subtype": "master", @@ -214,8 +214,8 @@ def setup(py_params_dict): "RST_VAL": f"{NBITS}'b0", }, "connect": { - "clk_en_rst": "clk_en_rst", - "en_rst": "sel_reg_en_rst", + "clk_en_rst_s": "clk_en_rst_s", + "en_rst_s": "sel_reg_en_rst", "data_i": "sel_reg_data_i", "data_o": "sel_reg_data_o", }, diff --git a/lib/hardware/buses/iob_wishbone2iob/iob_wishbone2iob.py b/lib/hardware/buses/iob_wishbone2iob/iob_wishbone2iob.py index bd058dd16..05709fb65 100644 --- a/lib/hardware/buses/iob_wishbone2iob/iob_wishbone2iob.py +++ b/lib/hardware/buses/iob_wishbone2iob/iob_wishbone2iob.py @@ -23,7 +23,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -31,7 +31,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "iob", + "name": "iob_m", "interface": { "type": "iob", "subtype": "master", @@ -41,7 +41,7 @@ def setup(py_params_dict): "descr": "IOb native master interface", }, { - "name": "wb", + "name": "wb_s", "interface": { "type": "wb", "subtype": "slave", @@ -162,8 +162,8 @@ def setup(py_params_dict): "RST_VAL": 0, }, "connect": { - "clk_en_rst": "clk_en_rst", - "en_rst": "int", + "clk_en_rst_s": "clk_en_rst_s", + "en_rst_i": "int", "data_i": "wack", "data_o": "wack_r", }, @@ -176,8 +176,8 @@ def setup(py_params_dict): "RST_VAL": 0, }, "connect": { - "clk_en_rst": "clk_en_rst", - "en_rst": "int_2", + "clk_en_rst_s": "clk_en_rst_s", + "en_rst_i": "int_2", "data_i": "valid", "data_o": "valid_r", }, diff --git a/lib/hardware/clocks_resets/iob_clock/iob_clock.py b/lib/hardware/clocks_resets/iob_clock/iob_clock.py index 05aa7ca3c..f1acdb7f6 100644 --- a/lib/hardware/clocks_resets/iob_clock/iob_clock.py +++ b/lib/hardware/clocks_resets/iob_clock/iob_clock.py @@ -15,7 +15,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk", + "name": "clk_o", "descr": "Output clock", "signals": [ {"name": "clk", "width": "1", "direction": "output"}, diff --git a/lib/hardware/clocks_resets/iob_nco/hardware/iob_nco_sync.py b/lib/hardware/clocks_resets/iob_nco/hardware/iob_nco_sync.py index 2386b1e2f..4462b3eba 100644 --- a/lib/hardware/clocks_resets/iob_nco/hardware/iob_nco_sync.py +++ b/lib/hardware/clocks_resets/iob_nco/hardware/iob_nco_sync.py @@ -15,7 +15,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_rst", + "name": "clk_rst_s", "interface": { "type": "clk_rst", "subtype": "slave", @@ -23,7 +23,7 @@ def setup(py_params_dict): "descr": "Clock and reset", }, { - "name": "clk_in", + "name": "clk_i", "descr": "Source clock domain", "signals": [ { @@ -35,7 +35,7 @@ def setup(py_params_dict): ], }, { - "name": "soft_reset_in", + "name": "soft_reset_i", "descr": "System soft reset", "signals": [ { @@ -47,7 +47,7 @@ def setup(py_params_dict): ], }, { - "name": "enable_in", + "name": "enable_i", "descr": "System enable", "signals": [ { @@ -59,7 +59,7 @@ def setup(py_params_dict): ], }, { - "name": "period_wdata_in", + "name": "period_wdata_i", "descr": "System period data", "signals": [ { @@ -71,7 +71,7 @@ def setup(py_params_dict): ], }, { - "name": "period_wen_in", + "name": "period_wen_i", "descr": "System period write enable", "signals": [ { @@ -83,7 +83,7 @@ def setup(py_params_dict): ], }, { - "name": "soft_reset_out", + "name": "soft_reset_o", "descr": "Source clock domain soft reset", "signals": [ { @@ -95,7 +95,7 @@ def setup(py_params_dict): ], }, { - "name": "enable_out", + "name": "enable_o", "descr": "Source clock domain enable", "signals": [ { @@ -107,7 +107,7 @@ def setup(py_params_dict): ], }, { - "name": "period_wdata_out", + "name": "period_wdata_o", "descr": "Source clock domain period data", "signals": [ { @@ -119,7 +119,7 @@ def setup(py_params_dict): ], }, { - "name": "period_wen_out", + "name": "period_wen_o", "descr": "Source clock domain period write enable", "signals": [ { @@ -157,9 +157,9 @@ def setup(py_params_dict): "DATA_W": "1", }, "connect": { - "clk_rst": "clk_rst", - "signal_i": "soft_reset_in", - "signal_o": "soft_reset_out", + "clk_rst_s": "clk_rst_s", + "signal_i": "soft_reset_i", + "signal_o": "soft_reset_o", }, }, { @@ -170,9 +170,9 @@ def setup(py_params_dict): "DATA_W": "1", }, "connect": { - "clk_rst": "clk_rst", - "signal_i": "enable_in", - "signal_o": "enable_out", + "clk_rst_s": "clk_rst_s", + "signal_i": "enable_i", + "signal_o": "enable_o", }, }, { @@ -183,7 +183,7 @@ def setup(py_params_dict): "DATA_W": "PERIOD_W+1", }, "connect": { - "clk_rst": "clk_rst", + "clk_rst_s": "clk_rst_s", "signal_i": "period_int", "signal_o": "period_out", }, diff --git a/lib/hardware/clocks_resets/iob_nco/iob_nco.py b/lib/hardware/clocks_resets/iob_nco/iob_nco.py index 457adc67c..1a2366b4b 100644 --- a/lib/hardware/clocks_resets/iob_nco/iob_nco.py +++ b/lib/hardware/clocks_resets/iob_nco/iob_nco.py @@ -31,7 +31,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -39,7 +39,7 @@ def setup(py_params_dict): "descr": "clock, clock enable and reset", }, { - "name": "iob", + "name": "iob_s", "interface": { "type": "iob", "subtype": "slave", @@ -49,7 +49,7 @@ def setup(py_params_dict): "descr": "CPU native interface", }, { - "name": "clk_src", + "name": "clk_src_i", "descr": "Source clock interface", "signals": [ { @@ -61,7 +61,7 @@ def setup(py_params_dict): ], }, { - "name": "clk_gen", + "name": "clk_gen_o", "descr": "Output generated clock interface", "signals": [ { @@ -237,13 +237,6 @@ def setup(py_params_dict): {"name": "acc_out", "width": "DATA_W"}, ], }, - { - "name": "acc_ld_data_nxt", - "descr": "", - "signals": [ - {"name": "acc_ld_data_nxt", "width": "DATA_W+1"}, - ], - }, # modcnt { "name": "modcnt_en_rst", @@ -317,9 +310,9 @@ def setup(py_params_dict): } ], "connect": { - "clk_en_rst": "clk_en_rst", - "control_if": "iob", - "csrs_iob_output": "csrs_iob", + "clk_en_rst_s": "clk_en_rst_s", + "control_if_s": "iob_s", + "csrs_iob_o": "csrs_iob", # Register interfaces "softreset": "softreset", "enable": "enable", @@ -334,8 +327,8 @@ def setup(py_params_dict): "DATA_W": "DATA_W", }, "connect": { - "clk_en_rst": "clk_en_rst", - "en_rst": "per_reg_en_rst", + "clk_en_rst_s": "clk_en_rst_s", + "en_rst_i": "per_reg_en_rst", "data_i": "per_reg_data_i", "data_o": "per_reg_data_o", }, @@ -348,10 +341,10 @@ def setup(py_params_dict): "DATA_W": "1", }, "connect": { - "clk_en_rst": "clk_en_rst", - "en_rst": "clk_out_reg_en_rst", + "clk_en_rst_s": "clk_en_rst_s", + "en_rst_i": "clk_out_reg_en_rst", "data_i": "clk_out_reg_data_i", - "data_o": "clk_gen", + "data_o": "clk_gen_o", }, }, { @@ -362,13 +355,12 @@ def setup(py_params_dict): "DATA_W": "DATA_W", }, "connect": { - "clk_en_rst": "acc_ld_clk_en_rst", - "en_rst": "clk_out_reg_en_rst", + "clk_en_rst_s": "acc_ld_clk_en_rst", + "en_rst_i": "clk_out_reg_en_rst", "ld_i": "acc_ld_ld", "ld_val_i": "acc_ld_ld_val", "incr_i": "acc_ld_incr", "data_o": "acc_ld_data", - "data_nxt_o": "acc_ld_data_nxt", }, }, { @@ -379,8 +371,8 @@ def setup(py_params_dict): "DATA_W": "DATA_W - FRAC_W", }, "connect": { - "clk_en_rst": "acc_ld_clk_en_rst", - "en_rst": "modcnt_en_rst", + "clk_en_rst_s": "acc_ld_clk_en_rst", + "en_rst_i": "modcnt_en_rst", "mod_i": "modcnt_mod", "data_o": "modcnt_data", }, @@ -393,16 +385,16 @@ def setup(py_params_dict): "PERIOD_W": "DATA_W", }, "connect": { - "clk_rst": "clk_rst", - "clk_in": "clk_src", - "soft_reset_in": "softreset", - "enable_in": "enable", - "period_wdata_in": "period_wdata_sync_in", - "period_wen_in": "period_wen_sync_in", - "soft_reset_out": "softreset_clk_src", - "enable_out": "enable_clk_src", - "period_wdata_out": "period_wdata_sync_out", - "period_wen_out": "period_wen_sync_out", + "clk_rst_s": "clk_rst", + "clk_i": "clk_src_i", + "soft_reset_i": "softreset", + "enable_i": "enable", + "period_wdata_i": "period_wdata_sync_in", + "period_wen_i": "period_wen_sync_in", + "soft_reset_o": "softreset_clk_src", + "enable_o": "enable_clk_src", + "period_wdata_o": "period_wdata_sync_out", + "period_wen_o": "period_wen_sync_out", }, }, # For simulation diff --git a/lib/hardware/clocks_resets/iob_pulse_gen/iob_pulse_gen.py b/lib/hardware/clocks_resets/iob_pulse_gen/iob_pulse_gen.py index f79f8c388..92d3abff9 100644 --- a/lib/hardware/clocks_resets/iob_pulse_gen/iob_pulse_gen.py +++ b/lib/hardware/clocks_resets/iob_pulse_gen/iob_pulse_gen.py @@ -47,7 +47,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -55,14 +55,14 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "start", + "name": "start_i", "descr": "Input port", "signals": [ {"name": "start", "width": 1, "direction": "input"}, ], }, { - "name": "pulse", + "name": "pulse_o", "descr": "Output port", "signals": [ {"name": "pulse", "width": 1, "direction": "output"}, @@ -116,7 +116,7 @@ def setup(py_params_dict): "RST_VAL": 0, }, "connect": { - "clk_en_rst": "clk_en_rst", + "clk_en_rst_s": "clk_en_rst_s", "data_i": "start_detected_nxt", "data_o": "start_detected", }, @@ -129,8 +129,8 @@ def setup(py_params_dict): "RST_VAL": "{WIDTH{1'b0}}", }, "connect": { - "clk_en_rst": "clk_en_rst", - "en_rst": "iob_pulse_gen_int", + "clk_en_rst_s": "clk_en_rst_s", + "en_rst_i": "iob_pulse_gen_int", "data_o": "cnt", }, }, @@ -142,9 +142,9 @@ def setup(py_params_dict): "RST_VAL": 0, }, "connect": { - "clk_en_rst": "clk_en_rst", + "clk_en_rst_s": "clk_en_rst_s", "data_i": "pulse_nxt", - "data_o": "pulse", + "data_o": "pulse_o", }, }, ], diff --git a/lib/hardware/fifo/iob_fifo_sync/iob_fifo_sync.py b/lib/hardware/fifo/iob_fifo_sync/iob_fifo_sync.py index d551419ff..3cdcebbda 100644 --- a/lib/hardware/fifo/iob_fifo_sync/iob_fifo_sync.py +++ b/lib/hardware/fifo/iob_fifo_sync/iob_fifo_sync.py @@ -80,7 +80,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -88,7 +88,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "rst", + "name": "rst_i", "descr": "Synchronous reset interface", "signals": [ { @@ -192,7 +192,7 @@ def setup(py_params_dict): ], }, { - "name": "fifo", + "name": "fifo_o", "descr": "FIFO interface", "signals": [ { diff --git a/lib/hardware/fifo/iob_gray_counter/iob_gray_counter.py b/lib/hardware/fifo/iob_gray_counter/iob_gray_counter.py index c3f09a1e6..8f9fd6bee 100644 --- a/lib/hardware/fifo/iob_gray_counter/iob_gray_counter.py +++ b/lib/hardware/fifo/iob_gray_counter/iob_gray_counter.py @@ -6,7 +6,7 @@ def setup(py_params_dict): "generate_hw": False, "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", diff --git a/lib/hardware/iob_gpio/iob_gpio.py b/lib/hardware/iob_gpio/iob_gpio.py index a48ae353d..7276769eb 100755 --- a/lib/hardware/iob_gpio/iob_gpio.py +++ b/lib/hardware/iob_gpio/iob_gpio.py @@ -48,7 +48,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -56,7 +56,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "iob", + "name": "iob_s", "interface": { "type": "iob", "subtype": "slave", @@ -68,7 +68,7 @@ def setup(py_params_dict): for idx in range(N_INPUTS): attributes_dict["ports"].append( { - "name": "input_" + str(idx), + "name": "input_" + str(idx) + "_i", "descr": "", "signals": [ { @@ -83,7 +83,7 @@ def setup(py_params_dict): for idx in range(N_OUTPUTS): attributes_dict["ports"].append( { - "name": "output_" + str(idx), + "name": "output_" + str(idx) + "_o", "descr": "", "signals": [ { @@ -98,7 +98,7 @@ def setup(py_params_dict): if TRISTATE: attributes_dict["ports"][-1]["signals"].append( { - "name": "output_enable_" + str(idx), + "name": "output_enable_" + str(idx) + "_o", "direction": "output", "width": "OUTPUT_GPIO_W", "descr": f"Output Enable interface bits can be used to tristate output {idx} on external module", @@ -198,9 +198,9 @@ def setup(py_params_dict): } ], "connect": { - "clk_en_rst": "clk_en_rst", - "control_if": "iob", - "csrs_iob_output": "csrs_iob", + "clk_en_rst_s": "clk_en_rst_s", + "control_if_s": "iob_s", + "csrs_iob_o": "csrs_iob", **reg_connections, }, }, diff --git a/lib/hardware/iob_picorv32/iob_picorv32.py b/lib/hardware/iob_picorv32/iob_picorv32.py index fdf0fd9a1..55d12fab1 100644 --- a/lib/hardware/iob_picorv32/iob_picorv32.py +++ b/lib/hardware/iob_picorv32/iob_picorv32.py @@ -40,7 +40,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_i", "signals": [ { "name": "clk", @@ -64,7 +64,7 @@ def setup(py_params_dict): "descr": "Clock, enable and synchronous reset", }, { - "name": "general", + "name": "general_o", "descr": "General interface signals", "signals": [ { @@ -76,7 +76,7 @@ def setup(py_params_dict): ], }, { - "name": "i_bus", + "name": "i_bus_m", "interface": { "type": "iob", "subtype": "master", @@ -89,7 +89,7 @@ def setup(py_params_dict): "descr": "iob-picorv32 instruction bus", }, { - "name": "d_bus", + "name": "d_bus_m", "interface": { "type": "iob", "subtype": "master", diff --git a/lib/hardware/iob_regfileif/iob_regfileif.py b/lib/hardware/iob_regfileif/iob_regfileif.py index 93fa0f388..77711927c 100755 --- a/lib/hardware/iob_regfileif/iob_regfileif.py +++ b/lib/hardware/iob_regfileif/iob_regfileif.py @@ -132,7 +132,7 @@ def setup(py_params_dict): "confs": confs, "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -140,7 +140,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "internal_control_if", + "name": "internal_control_if_s", "interface": { "type": params["internal_csr_if"], "subtype": "slave", @@ -149,7 +149,7 @@ def setup(py_params_dict): "descr": "Internal CPU native interface. Registers have their direction inverted from this CPU's perspective.", }, { - "name": "external_control_if", + "name": "external_control_if_s", "interface": { "type": params["external_csr_if"], "subtype": "slave", @@ -189,9 +189,9 @@ def setup(py_params_dict): "instance_description": "Control/Status Registers for external CPU", "csrs": params["csrs"], "connect": { - "clk_en_rst": "clk_en_rst", - "control_if": "external_control_if", - "csrs_iob_output": "csrs_iob", + "clk_en_rst_s": "clk_en_rst_s", + "control_if_s": "external_control_if_s", + "csrs_iob_o": "csrs_iob", **external_reg_connections, }, "csr_if": params["external_csr_if"], @@ -206,9 +206,9 @@ def setup(py_params_dict): "instance_description": "Control/Status Registers for internal CPU (inverted registers)", "csrs": csrs_inverted, "connect": { - "clk_en_rst": "clk_en_rst", - "control_if": "internal_control_if", - "csrs_iob_output": "internal_iob2", + "clk_en_rst_s": "clk_en_rst_s", + "control_if_s": "internal_control_if_s", + "csrs_iob_o": "internal_iob2", **internal_reg_connections, }, "csr_if": params["internal_csr_if"], diff --git a/lib/hardware/iob_timer/hardware/timer_core.py b/lib/hardware/iob_timer/hardware/timer_core.py index 0c0e12c76..d79f1f147 100644 --- a/lib/hardware/iob_timer/hardware/timer_core.py +++ b/lib/hardware/iob_timer/hardware/timer_core.py @@ -6,7 +6,7 @@ def setup(py_params_dict): "generate_hw": False, "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", diff --git a/lib/hardware/iob_timer/iob_timer.py b/lib/hardware/iob_timer/iob_timer.py index 59c46f324..011e6e0bb 100755 --- a/lib/hardware/iob_timer/iob_timer.py +++ b/lib/hardware/iob_timer/iob_timer.py @@ -31,7 +31,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -39,7 +39,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "cbus", + "name": "cbus_s", "interface": { "type": "axil", "subtype": "slave", @@ -176,9 +176,9 @@ def setup(py_params_dict): ], "csr_if": "axil", "connect": { - "clk_en_rst": "clk_en_rst", - "control_if": "cbus", - "csrs_iob_output": "csrs_iob", + "clk_en_rst_s": "clk_en_rst_s", + "control_if_s": "cbus_s", + "csrs_iob_o": "csrs_iob", # Register interfaces "reset": "reset", "enable": "enable", @@ -192,7 +192,7 @@ def setup(py_params_dict): "instance_name": "timer_core_inst", "instance_description": "Timer core driver", "connect": { - "clk_en_rst": "clk_en_rst", + "clk_en_rst_s": "clk_en_rst_s", "reg_interface": "timer_core_reg_interface", }, }, diff --git a/lib/hardware/iob_uart/hardware/uart_core.py b/lib/hardware/iob_uart/hardware/uart_core.py index 008934fe0..0abe3c647 100644 --- a/lib/hardware/iob_uart/hardware/uart_core.py +++ b/lib/hardware/iob_uart/hardware/uart_core.py @@ -6,7 +6,7 @@ def setup(py_params_dict): "generate_hw": False, "ports": [ { - "name": "clk_rst", + "name": "clk_rst_s", "interface": { "type": "clk_rst", "subtype": "slave", @@ -34,7 +34,7 @@ def setup(py_params_dict): ], }, { - "name": "rs232", + "name": "rs232_m", "interface": { "type": "rs232", }, diff --git a/lib/hardware/iob_uart/iob_uart.py b/lib/hardware/iob_uart/iob_uart.py index dddaee4a9..5075af0c3 100755 --- a/lib/hardware/iob_uart/iob_uart.py +++ b/lib/hardware/iob_uart/iob_uart.py @@ -34,7 +34,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -42,7 +42,7 @@ def setup(py_params_dict): "descr": "Clock, clock enable and reset", }, { - "name": "cbus", + "name": "cbus_s", "interface": { "type": CSR_IF, "subtype": "slave", @@ -52,7 +52,7 @@ def setup(py_params_dict): "descr": "CPU native interface", }, { - "name": "rs232", + "name": "rs232_m", "interface": { "type": "rs232", }, @@ -271,9 +271,9 @@ def setup(py_params_dict): ], "csr_if": CSR_IF, "connect": { - "clk_en_rst": "clk_en_rst", - "control_if": "cbus", - "csrs_iob_output": "csrs_iob", + "clk_en_rst_s": "clk_en_rst_s", + "control_if_s": "cbus_s", + "csrs_iob_o": "csrs_iob", # Register interfaces "softreset": "softreset", "div": "div", @@ -294,7 +294,7 @@ def setup(py_params_dict): "RST_VAL": "1'b0", }, "connect": { - "clk_en_rst": "clk_en_rst", + "clk_en_rst_s": "clk_en_rst_s", "data_i": "iob_reg_rvalid_data_i", "data_o": "iob_reg_rvalid_data_o", }, @@ -304,9 +304,9 @@ def setup(py_params_dict): "instance_name": "uart_core_inst", "instance_description": "UART core driver", "connect": { - "clk_rst": "clk_rst", + "clk_rst_s": "clk_rst", "reg_interface": "uart_core_reg_interface", - "rs232": "rs232", + "rs232_m": "rs232_m", }, }, ], diff --git a/lib/hardware/memories/axi_ram/axi_ram.py b/lib/hardware/memories/axi_ram/axi_ram.py index 14407f84a..f7125ad33 100644 --- a/lib/hardware/memories/axi_ram/axi_ram.py +++ b/lib/hardware/memories/axi_ram/axi_ram.py @@ -80,7 +80,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk", + "name": "clk_i", "descr": "Clock", "signals": [ { @@ -91,7 +91,7 @@ def setup(py_params_dict): ], }, { - "name": "rst", + "name": "rst_i", "descr": "Synchronous reset", "signals": [ { @@ -102,7 +102,7 @@ def setup(py_params_dict): ], }, { - "name": "axi", + "name": "axi_s", "interface": { "type": "axi", "subtype": "slave", diff --git a/lib/hardware/memories/ram/iob_ram_sp_se/iob_ram_sp_se.py b/lib/hardware/memories/ram/iob_ram_sp_se/iob_ram_sp_se.py index eeb898157..0e5d992f2 100644 --- a/lib/hardware/memories/ram/iob_ram_sp_se/iob_ram_sp_se.py +++ b/lib/hardware/memories/ram/iob_ram_sp_se/iob_ram_sp_se.py @@ -47,7 +47,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk", + "name": "clk_i", "descr": "Clock", "signals": [ {"name": "clk", "width": 1, "direction": "input"}, diff --git a/lib/hardware/memories/ram/iob_ram_t2p/iob_ram_t2p.py b/lib/hardware/memories/ram/iob_ram_t2p/iob_ram_t2p.py index 4db1fd983..5a83c9329 100644 --- a/lib/hardware/memories/ram/iob_ram_t2p/iob_ram_t2p.py +++ b/lib/hardware/memories/ram/iob_ram_t2p/iob_ram_t2p.py @@ -39,7 +39,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk", + "name": "clk_i", "descr": "Clock", "signals": [ {"name": "clk", "width": 1, "direction": "input"}, diff --git a/lib/hardware/memories/ram/iob_ram_t2p_be/iob_ram_t2p_be.py b/lib/hardware/memories/ram/iob_ram_t2p_be/iob_ram_t2p_be.py index 3c165c576..7d4805a84 100644 --- a/lib/hardware/memories/ram/iob_ram_t2p_be/iob_ram_t2p_be.py +++ b/lib/hardware/memories/ram/iob_ram_t2p_be/iob_ram_t2p_be.py @@ -47,7 +47,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk", + "name": "clk_i", "descr": "Clock", "signals": [ {"name": "clk", "width": 1, "direction": "input"}, diff --git a/lib/hardware/memories/ram/iob_ram_t2p_tiled/iob_ram_t2p_tiled.py b/lib/hardware/memories/ram/iob_ram_t2p_tiled/iob_ram_t2p_tiled.py index f7574b3c1..0b68f6b27 100644 --- a/lib/hardware/memories/ram/iob_ram_t2p_tiled/iob_ram_t2p_tiled.py +++ b/lib/hardware/memories/ram/iob_ram_t2p_tiled/iob_ram_t2p_tiled.py @@ -39,7 +39,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk", + "name": "clk_i", "descr": "Clock", "signals": [ {"name": "clk", "width": 1, "direction": "input"}, diff --git a/lib/hardware/memories/ram/iob_ram_tdp/iob_ram_tdp.py b/lib/hardware/memories/ram/iob_ram_tdp/iob_ram_tdp.py index 5caa7c2e8..d90c43bfa 100644 --- a/lib/hardware/memories/ram/iob_ram_tdp/iob_ram_tdp.py +++ b/lib/hardware/memories/ram/iob_ram_tdp/iob_ram_tdp.py @@ -47,7 +47,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk", + "name": "clk_i", "descr": "clock", "signals": [ {"name": "clk", "width": 1, "direction": "input"}, diff --git a/lib/hardware/memories/ram/iob_ram_tdp_be/iob_ram_tdp_be.py b/lib/hardware/memories/ram/iob_ram_tdp_be/iob_ram_tdp_be.py index 9bb81f152..22b18fc80 100644 --- a/lib/hardware/memories/ram/iob_ram_tdp_be/iob_ram_tdp_be.py +++ b/lib/hardware/memories/ram/iob_ram_tdp_be/iob_ram_tdp_be.py @@ -63,7 +63,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk", + "name": "clk_i", "descr": "Clock", "signals": [ {"name": "clk", "width": 1, "direction": "input"}, diff --git a/lib/hardware/memories/ram/iob_ram_tdp_be_xil/iob_ram_tdp_be_xil.py b/lib/hardware/memories/ram/iob_ram_tdp_be_xil/iob_ram_tdp_be_xil.py index 5a9468204..fdcf56a5e 100644 --- a/lib/hardware/memories/ram/iob_ram_tdp_be_xil/iob_ram_tdp_be_xil.py +++ b/lib/hardware/memories/ram/iob_ram_tdp_be_xil/iob_ram_tdp_be_xil.py @@ -55,7 +55,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk", + "name": "clk_i", "descr": "Clock", "signals": [ {"name": "clk", "width": 1, "direction": "input"}, diff --git a/lib/hardware/memories/regfile/iob_regfile_2p/iob_regfile_2p.py b/lib/hardware/memories/regfile/iob_regfile_2p/iob_regfile_2p.py index c047a07e5..d1d17e066 100644 --- a/lib/hardware/memories/regfile/iob_regfile_2p/iob_regfile_2p.py +++ b/lib/hardware/memories/regfile/iob_regfile_2p/iob_regfile_2p.py @@ -6,7 +6,7 @@ def setup(py_params_dict): "generate_hw": False, "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", diff --git a/lib/hardware/memories/regfile/iob_regfile_sp/iob_regfile_sp.py b/lib/hardware/memories/regfile/iob_regfile_sp/iob_regfile_sp.py index 1df5e9348..b7a1a9742 100644 --- a/lib/hardware/memories/regfile/iob_regfile_sp/iob_regfile_sp.py +++ b/lib/hardware/memories/regfile/iob_regfile_sp/iob_regfile_sp.py @@ -6,7 +6,7 @@ def setup(py_params_dict): "generate_hw": False, "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", diff --git a/lib/hardware/shifters/iob_piso_reg/iob_piso_reg.py b/lib/hardware/shifters/iob_piso_reg/iob_piso_reg.py index ba57413fa..1d2371068 100644 --- a/lib/hardware/shifters/iob_piso_reg/iob_piso_reg.py +++ b/lib/hardware/shifters/iob_piso_reg/iob_piso_reg.py @@ -15,7 +15,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -81,7 +81,7 @@ def setup(py_params_dict): "RST_VAL": 0, }, "connect": { - "clk_en_rst": "clk_en_rst", + "clk_en_rst_s": "clk_en_rst_s", "data_i": "data_int", "data_o": "data_reg_int", }, diff --git a/lib/hardware/shifters/iob_shift_reg/iob_shift_reg.py b/lib/hardware/shifters/iob_shift_reg/iob_shift_reg.py index f7ce8d980..0dda55f7f 100644 --- a/lib/hardware/shifters/iob_shift_reg/iob_shift_reg.py +++ b/lib/hardware/shifters/iob_shift_reg/iob_shift_reg.py @@ -6,7 +6,7 @@ def setup(py_params_dict): "generate_hw": False, "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", diff --git a/lib/hardware/synchronizers/iob_neg2posedge_sync/iob_neg2posedge_sync.py b/lib/hardware/synchronizers/iob_neg2posedge_sync/iob_neg2posedge_sync.py index cf8c4ff0c..5dcc74940 100644 --- a/lib/hardware/synchronizers/iob_neg2posedge_sync/iob_neg2posedge_sync.py +++ b/lib/hardware/synchronizers/iob_neg2posedge_sync/iob_neg2posedge_sync.py @@ -23,7 +23,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "interface": { "type": "clk_en_rst", "subtype": "slave", @@ -71,7 +71,7 @@ def setup(py_params_dict): "RST_VAL": "RST_VAL", }, "connect": { - "clk_en_rst": "clk_en_rst", + "clk_en_rst_s": "clk_en_rst_s", "data_i": "signal_i", "data_o": "synchronizer", }, @@ -84,7 +84,7 @@ def setup(py_params_dict): "RST_VAL": "RST_VAL", }, "connect": { - "clk_en_rst": "clk_en_rst", + "clk_en_rst_s": "clk_en_rst_s", "data_i": "synchronizer", "data_o": "signal_o", }, diff --git a/lib/hardware/synchronizers/iob_reset_sync/iob_reset_sync.py b/lib/hardware/synchronizers/iob_reset_sync/iob_reset_sync.py index 271ed005b..b24be9741 100644 --- a/lib/hardware/synchronizers/iob_reset_sync/iob_reset_sync.py +++ b/lib/hardware/synchronizers/iob_reset_sync/iob_reset_sync.py @@ -11,7 +11,7 @@ def setup(py_params_dict): "version": "0.1", "ports": [ { - "name": "clk_rst", + "name": "clk_rst_s", "interface": { "type": "clk_rst", "subtype": "slave", @@ -55,7 +55,7 @@ def setup(py_params_dict): "RST_VAL": "2'd3" if edge else "2'd0", }, "connect": { - "clk_rst": "clk_rst", + "clk_rst_s": "clk_rst_s", "iob_r_data_i": "data_int", "iob_r_data_o": "sync", }, diff --git a/lib/hardware/synchronizers/iob_sync/iob_sync.py b/lib/hardware/synchronizers/iob_sync/iob_sync.py index 275cd43e1..d60061563 100644 --- a/lib/hardware/synchronizers/iob_sync/iob_sync.py +++ b/lib/hardware/synchronizers/iob_sync/iob_sync.py @@ -23,7 +23,7 @@ def setup(py_params_dict): ], "ports": [ { - "name": "clk_rst", + "name": "clk_rst_s", "interface": { "type": "clk_rst", "subtype": "slave", @@ -71,7 +71,7 @@ def setup(py_params_dict): "RST_VAL": "RST_VAL", }, "connect": { - "clk_rst": "clk_rst", + "clk_rst_s": "clk_rst_s", "iob_r_data_i": "signal_i", "iob_r_data_o": "synchronizer", }, @@ -84,7 +84,7 @@ def setup(py_params_dict): "RST_VAL": "RST_VAL", }, "connect": { - "clk_rst": "clk_rst", + "clk_rst_s": "clk_rst_s", "iob_r_data_i": "synchronizer", "iob_r_data_o": "signal_o", }, diff --git a/lib/scripts/default.nix b/lib/scripts/default.nix index c622abca2..ca34026e3 100644 --- a/lib/scripts/default.nix +++ b/lib/scripts/default.nix @@ -1,8 +1,8 @@ { pkgs ? import {} }: let - py2hwsw_commit = "4d51b94283522d53f1c3c293efda1fc9c180ae3d"; # Replace with the desired commit. - py2hwsw_sha256 = "X5jjz014jxpOh0rK7rOrvpTIvIcdX2QgU6JEaKjWTsI="; # Replace with the actual SHA256 hash. + py2hwsw_commit = "ca2341bea68e2d235b86dd3fbe46560c2a865116"; # Replace with the desired commit. + py2hwsw_sha256 = "HTl/6gYNt9ykSerZOZ4wm+AURSCahVcOhzKoJ8QmcCE="; # Replace with the actual SHA256 hash. py2hwsw = pkgs.python3.pkgs.buildPythonPackage rec { pname = "py2hwsw"; diff --git a/submodules/BOOTROM/iob_bootrom.py b/submodules/BOOTROM/iob_bootrom.py index efd3cdb23..0f1228424 100644 --- a/submodules/BOOTROM/iob_bootrom.py +++ b/submodules/BOOTROM/iob_bootrom.py @@ -63,7 +63,7 @@ def setup(py_params_dict): # "ports": [ { - "name": "clk_en_rst", + "name": "clk_en_rst_s", "descr": "Clock and reset", "interface": { "type": "clk_en_rst", @@ -71,7 +71,7 @@ def setup(py_params_dict): }, }, { - "name": "cbus", + "name": "cbus_s", "descr": "Front-end control interface", "interface": { "type": "axi", @@ -170,9 +170,9 @@ def setup(py_params_dict): ], "csr_if": "axi", "connect": { - "clk_en_rst": "clk_en_rst", - "control_if": "cbus", - "csrs_iob_output": "csrs_iob", + "clk_en_rst_s": "clk_en_rst_s", + "control_if_s": "cbus_s", + "csrs_iob_o": "csrs_iob", # Register interfaces "rom": "rom", }, @@ -186,7 +186,7 @@ def setup(py_params_dict): "RST_VAL": "1'b0", }, "connect": { - "clk_en_rst": "clk_en_rst", + "clk_en_rst_s": "clk_en_rst_s", "data_i": "rom_rvalid_data_i", "data_o": "rom_rvalid_data_o", }, diff --git a/submodules/VEXRISCV b/submodules/VEXRISCV index da8b3fda9..2069eaf0b 160000 --- a/submodules/VEXRISCV +++ b/submodules/VEXRISCV @@ -1 +1 @@ -Subproject commit da8b3fda97efd749c39e214453a59a28228dfabc +Subproject commit 2069eaf0b9db6c476c5e8385839bc154426e12c7