diff --git a/hardware/fpga/quartus/CYCLONEV-GT-DK/iob_soc_fpga_wrapper.v b/hardware/fpga/quartus/CYCLONEV-GT-DK/iob_soc_fpga_wrapper.v
index 5e05f4a1e..d505570c7 100644
--- a/hardware/fpga/quartus/CYCLONEV-GT-DK/iob_soc_fpga_wrapper.v
+++ b/hardware/fpga/quartus/CYCLONEV-GT-DK/iob_soc_fpga_wrapper.v
@@ -124,6 +124,7 @@ module iob_soc_fpga_wrapper (
       //`endif
       `include "iob_soc_pportmaps.vs"
       .clk_i (clk),
+      .cke_i (1'b1),
       .arst_i(rst),
       .trap_o(trap)
    );
diff --git a/hardware/fpga/vivado/AES-KU040-DB-G/iob_soc_fpga_wrapper.v b/hardware/fpga/vivado/AES-KU040-DB-G/iob_soc_fpga_wrapper.v
index ecf3e25dc..661cdaef5 100644
--- a/hardware/fpga/vivado/AES-KU040-DB-G/iob_soc_fpga_wrapper.v
+++ b/hardware/fpga/vivado/AES-KU040-DB-G/iob_soc_fpga_wrapper.v
@@ -120,6 +120,7 @@ module iob_soc_fpga_wrapper (
       //`endif
       `include "iob_soc_pportmaps.vs"
       .clk_i (clk),
+      .cke_i (1'b1),
       .arst_i(rst),
       .trap_o(trap)
    );
diff --git a/hardware/fpga/vivado/BASYS3/iob_soc_fpga_wrapper.v b/hardware/fpga/vivado/BASYS3/iob_soc_fpga_wrapper.v
index d8a7fb737..5d6774b0c 100644
--- a/hardware/fpga/vivado/BASYS3/iob_soc_fpga_wrapper.v
+++ b/hardware/fpga/vivado/BASYS3/iob_soc_fpga_wrapper.v
@@ -36,6 +36,7 @@ module iob_soc_fpga_wrapper (
    //
    iob_soc iob_soc (
       .clk_i   (clk),
+      .cke_i   (1'b1),
       .arst_i  (sys_rst),
       .trap_o  (trap),
       //UART
diff --git a/hardware/simulation/src/iob_soc_sim_wrapper.v b/hardware/simulation/src/iob_soc_sim_wrapper.v
index d3037e5e6..15c4110b9 100644
--- a/hardware/simulation/src/iob_soc_sim_wrapper.v
+++ b/hardware/simulation/src/iob_soc_sim_wrapper.v
@@ -63,6 +63,7 @@ module iob_soc_sim_wrapper (
    ) iob_soc0 (
       `include "iob_soc_pportmaps.vs"
       .clk_i (clk),
+      .cke_i (1'b1),
       .arst_i(rst),
       .trap_o(trap_o)
    );
diff --git a/hardware/src/iob_soc.v b/hardware/src/iob_soc.v
index 4bfb4d0b1..d3a01d88b 100644
--- a/hardware/src/iob_soc.v
+++ b/hardware/src/iob_soc.v
@@ -26,9 +26,6 @@ module iob_soc #(
    wire boot;
    wire cpu_reset;
 
-   wire cke_i;
-   assign cke_i = 1'b1;
-
    //
    //  CPU
    //
diff --git a/iob_soc.py b/iob_soc.py
index dc51a8d30..a8e022675 100755
--- a/iob_soc.py
+++ b/iob_soc.py
@@ -318,6 +318,12 @@ def _setup_ios(cls):
                         "n_bits": "1",
                         "descr": "System clock input",
                     },
+                    {
+                        "name": "cke_i",
+                        "type": "I",
+                        "n_bits": "1",
+                        "descr": "System clock enable",
+                    },
                     {
                         "name": "arst_i",
                         "type": "I",
diff --git a/scripts/iob_soc_create_wrapper_files.py b/scripts/iob_soc_create_wrapper_files.py
index 16004beac..4f7b3b5cf 100755
--- a/scripts/iob_soc_create_wrapper_files.py
+++ b/scripts/iob_soc_create_wrapper_files.py
@@ -94,8 +94,8 @@ def create_interconnect_instance(out_dir, name, num_extmem_connections):
       .S_COUNT     ({num_extmem_connections}),
       .M_COUNT     (1)
    ) system_axi_interconnect (
-      .clk(clk),
-      .rst(rst),
+      .clk(clk_i),
+      .rst(arst_i),
 
       // Need to use manually defined connections because awlock and arlock of interconnect is only on bit for each slave
       .s_axi_awid    (axi_awid),    //Address write channel ID.