FIFO_FWFT implementation causes output to pause unexpectedly long after flow control assertion

[JulianKemmerer]

The FIFO_FWFT implementation is correct in its use of valid+ready handshake signaling clock by clock.

However because of the weird way that the implementation uses its 2 cycle latency BRAM, asserting flow control ready=0 one cycle later causes 2 cycles of pause/valid=0 output data in a way that typical streams of data/FIFOs do not do...

Fix this because it can be a corner case folks get stuck on if not strictly following handshake signals...

[JulianKemmerer]

A similar but not as visible extra latency exists on the write side of the fifo valid in to valid out - running fifo near empty probably doesn't perform exactly as expected duty cycle/rates wise...

[JulianKemmerer]

Solution is to redo not using the built in dual port fifo prim, but raw VHDL fifo from fifo.h that can have more signals like clock enables that make feedback/buffering through the RAM possible without needing to resort to the current weird implementation with extra buffers.