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where in and out are global wires - then, if some_func is selected for having IO registers added to meet timing - the design will break - will get a VHDL syntax error and synth faills.
Missing logic for registering (non volatile) global wires.
Work around for now with ex. #pragma FUNC_NO_ADD_IO_REGS some_func to stop func from getting these broken IO regs added...
The text was updated successfully, but these errors were encountered:
if have ex.
where
in
andout
are global wires - then, ifsome_func
is selected for having IO registers added to meet timing - the design will break - will get a VHDL syntax error and synth faills.Missing logic for registering (non volatile) global wires.
Work around for now with ex.
#pragma FUNC_NO_ADD_IO_REGS some_func
to stop func from getting these broken IO regs added...The text was updated successfully, but these errors were encountered: