diff --git a/hw/chisel/src/main/scala/snax/readerWriter/AddressGenUnit.scala b/hw/chisel/src/main/scala/snax/readerWriter/AddressGenUnit.scala
index 90f45b0cf..6e6db4dff 100644
--- a/hw/chisel/src/main/scala/snax/readerWriter/AddressGenUnit.scala
+++ b/hw/chisel/src/main/scala/snax/readerWriter/AddressGenUnit.scala
@@ -200,7 +200,8 @@ class AddressGenUnit(
     new ComplexQueueConcat(
       inputWidth = io.addr.head.bits.getWidth * param.numChannel,
       outputWidth = io.addr.head.bits.getWidth,
-      depth = param.outputBufferDepth
+      depth = param.outputBufferDepth,
+      pipe = param.pipeFifo
     ) {
       override val desiredName = s"${moduleNamePrefix}_AddressBufferFIFO"
     }
@@ -208,10 +209,12 @@ class AddressGenUnit(
 
   // Calculate the current base address: the first stride need to be left-shifted
   val temporalOffset = VecInit(counters.map(_.io.value)).reduceTree(_ + _)
+
   // This is a table for all possible values that the spatial offset can take
   val spatialOffsetTable = for (i <- 0 until param.spatialBounds.length) yield {
     (0 until param.spatialBounds(i)).map(io.cfg.spatialStrides(i) * _.U)
   }
+
   val spatialOffsets = for (i <- 0 until param.numChannel) yield {
     var remainder = i
     var spatialOffset = temporalOffset
diff --git a/hw/chisel/src/main/scala/snax/readerWriter/DesignParams.scala b/hw/chisel/src/main/scala/snax/readerWriter/DesignParams.scala
index f3c2e3996..14ed44849 100644
--- a/hw/chisel/src/main/scala/snax/readerWriter/DesignParams.scala
+++ b/hw/chisel/src/main/scala/snax/readerWriter/DesignParams.scala
@@ -32,7 +32,8 @@ class AddressGenUnitParam(
     val addressWidth: Int,
     val numChannel: Int,
     val outputBufferDepth: Int,
-    val tcdmSize: Int
+    val tcdmSize: Int,
+    val pipeFifo: Boolean
 )
 
 object AddressGenUnitParam {
@@ -41,14 +42,16 @@ object AddressGenUnitParam {
       temporalDimension: Int,
       numChannel: Int,
       outputBufferDepth: Int,
-      tcdmSize: Int
+      tcdmSize: Int,
+      pipeFifo: Boolean
   ): AddressGenUnitParam = new AddressGenUnitParam(
     spatialBounds = spatialBounds,
     temporalDimension = temporalDimension,
     addressWidth = log2Ceil(tcdmSize) + 10,
     numChannel = numChannel,
     outputBufferDepth = outputBufferDepth,
-    tcdmSize = tcdmSize
+    tcdmSize = tcdmSize,
+    pipeFifo = pipeFifo
   )
 
   // The Very Simple instantiation of the Param
@@ -57,7 +60,8 @@ object AddressGenUnitParam {
     temporalDimension = 2,
     numChannel = 8,
     outputBufferDepth = 8,
-    tcdmSize = 128
+    tcdmSize = 128,
+    pipeFifo = true
   )
 }
 
@@ -70,14 +74,16 @@ class ReaderWriterParam(
     addressBufferDepth: Int = 8,
     dataBufferDepth: Int = 8,
     val configurableChannel: Boolean = false,
-    val configurableByteMask: Boolean = false
+    val configurableByteMask: Boolean = false,
+    val pipeFifo: Boolean = true
 ) {
   val aguParam = AddressGenUnitParam(
     spatialBounds = spatialBounds,
     temporalDimension = temporalDimension,
     numChannel = numChannel,
     outputBufferDepth = addressBufferDepth,
-    tcdmSize = tcdmSize
+    tcdmSize = tcdmSize,
+    pipeFifo = pipeFifo
   )
 
   val tcdmParam = TCDMParam(
diff --git a/hw/chisel/src/main/scala/snax/readerWriter/Reader.scala b/hw/chisel/src/main/scala/snax/readerWriter/Reader.scala
index d22a24c39..266331a31 100644
--- a/hw/chisel/src/main/scala/snax/readerWriter/Reader.scala
+++ b/hw/chisel/src/main/scala/snax/readerWriter/Reader.scala
@@ -55,7 +55,8 @@ class Reader(
     new ComplexQueueConcat(
       inputWidth = param.tcdmParam.dataWidth,
       outputWidth = param.tcdmParam.dataWidth * param.tcdmParam.numChannel,
-      depth = param.bufferDepth
+      depth = param.bufferDepth,
+      pipe = param.pipeFifo
     ) {
       override val desiredName = s"${moduleNamePrefix}_Reader_DataBuffer"
     }
diff --git a/hw/chisel/src/main/scala/snax/readerWriter/Writer.scala b/hw/chisel/src/main/scala/snax/readerWriter/Writer.scala
index 5e1cee8a2..b53050e9e 100644
--- a/hw/chisel/src/main/scala/snax/readerWriter/Writer.scala
+++ b/hw/chisel/src/main/scala/snax/readerWriter/Writer.scala
@@ -39,7 +39,8 @@ class Writer(
     new ComplexQueueConcat(
       inputWidth = param.tcdmParam.dataWidth * param.tcdmParam.numChannel,
       outputWidth = param.tcdmParam.dataWidth,
-      depth = param.bufferDepth
+      depth = param.bufferDepth,
+      pipe = param.pipeFifo
     ) {
       override val desiredName = s"${moduleNamePrefix}_Writer_DataBuffer"
     }
diff --git a/hw/chisel/src/main/scala/snax/utils/ComplexQueue.scala b/hw/chisel/src/main/scala/snax/utils/ComplexQueue.scala
index 44e6d81ab..c7e3ab13c 100644
--- a/hw/chisel/src/main/scala/snax/utils/ComplexQueue.scala
+++ b/hw/chisel/src/main/scala/snax/utils/ComplexQueue.scala
@@ -16,8 +16,12 @@ import chisel3.util._
   *   will be the second option No matter which case, the big width one should
   *   equal to integer times of the small width one
   */
-class ComplexQueueConcat(inputWidth: Int, outputWidth: Int, depth: Int)
-    extends Module
+class ComplexQueueConcat(
+    inputWidth: Int,
+    outputWidth: Int,
+    depth: Int,
+    pipe: Boolean = false
+) extends Module
     with RequireAsyncReset {
   val bigWidth = Seq(inputWidth, outputWidth).max
   val smallWidth = Seq(inputWidth, outputWidth).min
@@ -50,7 +54,7 @@ class ComplexQueueConcat(inputWidth: Int, outputWidth: Int, depth: Int)
   })
 
   val queues = for (i <- 0 until numChannel) yield {
-    val queue = Module(new Queue(UInt(smallWidth.W), depth))
+    val queue = Module(new Queue(UInt(smallWidth.W), depth, pipe))
     io.nearlyEmpty(i) := queue.io.count < 2.U
     io.nearlyFull(i) := queue.io.count > (depth - 2).U
     queue
diff --git a/hw/chisel/src/main/scala/snax/xdma/xdmaTop/xdmaTop.scala b/hw/chisel/src/main/scala/snax/xdma/xdmaTop/xdmaTop.scala
index 4385a69bf..69a78ed17 100644
--- a/hw/chisel/src/main/scala/snax/xdma/xdmaTop/xdmaTop.scala
+++ b/hw/chisel/src/main/scala/snax/xdma/xdmaTop/xdmaTop.scala
@@ -174,7 +174,8 @@ object xdmaTopGen extends App {
       parsedArgs("axiDataWidth").toInt / parsedArgs("tcdmDataWidth").toInt,
     addressBufferDepth = parsedArgs("readerBufferDepth").toInt,
     configurableChannel = true,
-    configurableByteMask = false
+    configurableByteMask = false,
+    pipeFifo = true
   )
 
   val writerparam = new ReaderWriterParam(
@@ -187,7 +188,8 @@ object xdmaTopGen extends App {
       parsedArgs("axiDataWidth").toInt / parsedArgs("tcdmDataWidth").toInt,
     addressBufferDepth = parsedArgs("writerBufferDepth").toInt,
     configurableChannel = true,
-    configurableByteMask = true
+    configurableByteMask = true,
+    pipeFifo = true
   )
   var readerextensionparam = Seq[HasDataPathExtension]()
   var writerextensionparam = Seq[HasDataPathExtension]()
diff --git a/hw/chisel/src/test/scala/snax/readerWriter/AddressGenUnitTester.scala b/hw/chisel/src/test/scala/snax/readerWriter/AddressGenUnitTester.scala
index 9863bd467..bf027d423 100644
--- a/hw/chisel/src/test/scala/snax/readerWriter/AddressGenUnitTester.scala
+++ b/hw/chisel/src/test/scala/snax/readerWriter/AddressGenUnitTester.scala
@@ -34,7 +34,8 @@ class AddressGenUnitTester extends AnyFlatSpec with ChiselScalatestTester {
         temporalDimension = 2,
         numChannel = 8,
         outputBufferDepth = 2,
-        tcdmSize = 128
+        tcdmSize = 128, 
+        pipeFifo = false
       )
     )
   )
@@ -68,7 +69,8 @@ class AddressGenUnitTester extends AnyFlatSpec with ChiselScalatestTester {
         temporalDimension = 2,
         numChannel = 8,
         outputBufferDepth = 2,
-        tcdmSize = 128
+        tcdmSize = 128, 
+        pipeFifo = false
       )
     )
   )
diff --git a/hw/chisel/src/test/scala/snax/readerWriter/ReaderTester.scala b/hw/chisel/src/test/scala/snax/readerWriter/ReaderTester.scala
index 1c58e124c..14ee9bdcf 100644
--- a/hw/chisel/src/test/scala/snax/readerWriter/ReaderTester.scala
+++ b/hw/chisel/src/test/scala/snax/readerWriter/ReaderTester.scala
@@ -17,7 +17,8 @@ class ReaderTester extends AnyFreeSpec with ChiselScalatestTester {
     new Reader(
       new ReaderWriterParam(
         configurableByteMask = false,
-        configurableChannel = true
+        configurableChannel = true,
+        pipeFifo = false
       )
     )
   ).withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)) {
diff --git a/hw/chisel/src/test/scala/snax/readerWriter/WriterTester.scala b/hw/chisel/src/test/scala/snax/readerWriter/WriterTester.scala
index ce4969395..e262c6069 100644
--- a/hw/chisel/src/test/scala/snax/readerWriter/WriterTester.scala
+++ b/hw/chisel/src/test/scala/snax/readerWriter/WriterTester.scala
@@ -51,7 +51,8 @@ class WriterTester extends AnyFreeSpec with ChiselScalatestTester {
     new Writer(
       new ReaderWriterParam(
         configurableByteMask = true,
-        configurableChannel = true
+        configurableChannel = true,
+        pipeFifo = false
       )
     )
   ).withAnnotations(Seq(WriteVcdAnnotation, VerilatorBackendAnnotation)) {