From 583bd601d9b694abac0ae369d8482628b0dbc388 Mon Sep 17 00:00:00 2001 From: Scott Lahteine Date: Thu, 26 Nov 2020 03:26:20 -0600 Subject: [PATCH] TFT FMSC patches --- Marlin/src/HAL/STM32/tft/tft_fsmc.cpp | 75 +++++++++++++++++++-------- Marlin/src/HAL/STM32/tft/tft_fsmc.h | 60 ++++++++++++++------- 2 files changed, 92 insertions(+), 43 deletions(-) diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp b/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp index 94bb113bebea..393577923766 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.cpp @@ -29,10 +29,15 @@ SRAM_HandleTypeDef TFT_FSMC::SRAMx; DMA_HandleTypeDef TFT_FSMC::DMAtx; -LCD_CONTROLLER_TypeDef *TFT_FSMC::LCD; + +#if !IS_ANET_ET + LCD_CONTROLLER_TypeDef *TFT_FSMC::LCD; +#endif void TFT_FSMC::Init() { - uint32_t controllerAddress; + #if !IS_ANET_ET + uint32_t controllerAddress; + #endif #if PIN_EXISTS(TFT_RESET) OUT_WRITE(TFT_RESET_PIN, HIGH); @@ -45,23 +50,25 @@ void TFT_FSMC::Init() { FSMC_NORSRAM_TimingTypeDef Timing, ExtTiming; - uint32_t NSBank = (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_CS_PIN), PinMap_FSMC_CS); + #if !IS_ANET_ET + const uint32_t NSBank = (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_CS_PIN), PinMap_FSMC_CS); + #endif // Perform the SRAM1 memory initialization sequence SRAMx.Instance = FSMC_NORSRAM_DEVICE; SRAMx.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; - SRAMx.Init.NSBank = NSBank; // SRAMx.Init + SRAMx.Init.NSBank = TERN(IS_ANET_ET, FSMC_NORSRAM_BANK1, NSBank); SRAMx.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; SRAMx.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; - SRAMx.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16; + SRAMx.Init.MemoryDataWidth = TERN(IS_ANET_ET, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16); SRAMx.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; SRAMx.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; SRAMx.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; SRAMx.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; SRAMx.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; SRAMx.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; - SRAMx.Init.ExtendedMode = FSMC_EXTENDED_MODE_ENABLE; + SRAMx.Init.ExtendedMode = TERN(IS_ANET_ET, FSMC_EXTENDED_MODE_DISABLE, FSMC_EXTENDED_MODE_ENABLE); SRAMx.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; SRAMx.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; #ifdef STM32F4xx @@ -73,8 +80,8 @@ void TFT_FSMC::Init() { Timing.AddressHoldTime = 15; Timing.DataSetupTime = 24; Timing.BusTurnAroundDuration = 0; - Timing.CLKDivision = 16; - Timing.DataLatency = 17; + Timing.CLKDivision = TERN(IS_ANET_ET, 0, 16); + Timing.DataLatency = TERN(IS_ANET_ET, 0, 17); Timing.AccessMode = FSMC_ACCESS_MODE_A; // Write Timing // Can be decreases from 8-15-8 to 0-0-1 with risk of stability loss @@ -93,7 +100,10 @@ void TFT_FSMC::Init() { pinmap_pinout(digitalPinToPinName(TFT_CS_PIN), PinMap_FSMC_CS); pinmap_pinout(digitalPinToPinName(TFT_RS_PIN), PinMap_FSMC_RS); - controllerAddress = FSMC_BANK1_1; + #if !IS_ANET_ET + controllerAddress = FSMC_BANK1_1; + #endif + #ifdef PF0 switch (NSBank) { case FSMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break; @@ -102,7 +112,9 @@ void TFT_FSMC::Init() { } #endif - controllerAddress |= (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_RS_PIN), PinMap_FSMC_RS); + #if !IS_ANET_ET + controllerAddress |= (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_RS_PIN), PinMap_FSMC_RS); + #endif HAL_SRAM_Init(&SRAMx, &Timing, &ExtTiming); @@ -126,21 +138,33 @@ void TFT_FSMC::Init() { DMAtx.Init.Mode = DMA_NORMAL; DMAtx.Init.Priority = DMA_PRIORITY_HIGH; - LCD = (LCD_CONTROLLER_TypeDef *)controllerAddress; + #if IS_ANET_ET + //controllerAddress = (uint32_t)0x60000000U; + //LCD = (LCD_CONTROLLER_TypeDef *)controllerAddress; + //LCD->RAM = (uint16_t *)LCD_RAM_ADR; + #else + LCD = (LCD_CONTROLLER_TypeDef *)controllerAddress; + #endif } uint32_t TFT_FSMC::GetID() { - uint32_t id; - WriteReg(0x0000); - id = LCD->RAM; - - if (id == 0) - id = ReadID(LCD_READ_ID); - if ((id & 0xFFFF) == 0 || (id & 0xFFFF) == 0xFFFF) - id = ReadID(LCD_READ_ID4); - return id; + #if IS_ANET_ET + return 0x8552; + #else + uint32_t id; + WriteReg(0x0000); + id = LCD->RAM; + + if (id == 0) + id = ReadID(LCD_READ_ID); + if ((id & 0xFFFF) == 0 || (id & 0xFFFF) == 0xFFFF) + id = ReadID(LCD_READ_ID4); + return id; + #endif } +#if !IS_ANET_ET + uint32_t TFT_FSMC::ReadID(uint16_t Reg) { uint32_t id; WriteReg(Reg); @@ -148,10 +172,12 @@ uint32_t TFT_FSMC::GetID() { id = Reg << 24; id |= (LCD->RAM & 0x00FF) << 16; id |= (LCD->RAM & 0x00FF) << 8; - id |= LCD->RAM & 0x00FF; + id |= (LCD->RAM & 0x00FF); return id; } +#endif + bool TFT_FSMC::isBusy() { if (__IS_DMA_ENABLED(&DMAtx)) if (__HAL_DMA_GET_FLAG(&DMAtx, __HAL_DMA_GET_TC_FLAG_INDEX(&DMAtx)) != 0 || __HAL_DMA_GET_FLAG(&DMAtx, __HAL_DMA_GET_TE_FLAG_INDEX(&DMAtx)) != 0) @@ -169,11 +195,14 @@ void TFT_FSMC::TransmitDMA(uint32_t MemoryIncrease, uint16_t *Data, uint16_t Cou #ifdef STM32F1xx DMAtx.Instance->CNDTR = Count; DMAtx.Instance->CPAR = (uint32_t)Data; - DMAtx.Instance->CMAR = (uint32_t)&(LCD->RAM); + DMAtx.Instance->CMAR = (uint32_t)&(LCD_RAM); #elif defined(STM32F4xx) + //#if IS_ANET_ET + //DMAtx.Instance->NDTR = (Count*2); + //#endif DMAtx.Instance->NDTR = Count; DMAtx.Instance->PAR = (uint32_t)Data; - DMAtx.Instance->M0AR = (uint32_t)&(LCD->RAM); + DMAtx.Instance->M0AR = (uint32_t)TERN(IS_ANET_ET, LCD_RAM_ADR, &LCD->RAM); #endif __HAL_DMA_ENABLE(&DMAtx); } diff --git a/Marlin/src/HAL/STM32/tft/tft_fsmc.h b/Marlin/src/HAL/STM32/tft/tft_fsmc.h index e2e0128c5efc..bdef3383beb4 100644 --- a/Marlin/src/HAL/STM32/tft/tft_fsmc.h +++ b/Marlin/src/HAL/STM32/tft/tft_fsmc.h @@ -49,6 +49,17 @@ typedef struct { __IO uint16_t RAM; } LCD_CONTROLLER_TypeDef; +#if IS_ANET_ET + #define LCD_RAM_ADR 0x60040000 + #define LCD_RAM *(__IO uint8_t *)LCD_RAM_ADR + #define LCD_REG *(__IO uint8_t *)0x60000000 + #define LCD_REG_DATA(V) ((V) & 0xFF) +#else + #define LCD_RAM LCD->RAM + #define LCD_REG LCD->REG + #define LCD_REG_DATA(V) (V) +#endif + class TFT_FSMC { private: static SRAM_HandleTypeDef SRAMx; @@ -56,8 +67,11 @@ class TFT_FSMC { static LCD_CONTROLLER_TypeDef *LCD; - static uint32_t ReadID(uint16_t Reg); - static void Transmit(uint16_t Data) { LCD->RAM = Data; __DSB(); } + #if !IS_ANET_ET + static uint32_t ReadID(uint16_t Reg); + #endif + + static void Transmit(uint8_t Data) { LCD_RAM = Data; __DSB(); } static void TransmitDMA(uint32_t MemoryIncrease, uint16_t *Data, uint16_t Count); public: @@ -66,11 +80,11 @@ class TFT_FSMC { static bool isBusy(); static void Abort() { __HAL_DMA_DISABLE(&DMAtx); } - static void DataTransferBegin(uint16_t DataWidth = DATASIZE_16BIT) {} + static void DataTransferBegin(uint16_t DataWidth = TERN(IS_ANET_ET, DATASIZE_8BIT, DATASIZE_16BIT)) {} static void DataTransferEnd() {}; - static void WriteData(uint16_t Data) { Transmit(Data); } - static void WriteReg(uint16_t Reg) { LCD->REG = Reg; __DSB(); } + static void WriteData(uint16_t Data) { Transmit(LCD_REG_DATA(Data)); } + static void WriteReg(uint16_t Reg) { LCD_REG = LCD_REG_DATA(Reg); __DSB(); } static void WriteSequence(uint16_t *Data, uint16_t Count) { TransmitDMA(DMA_PINC_ENABLE, Data, Count); } static void WriteMultiple(uint16_t Color, uint16_t Count) { static uint16_t Data; Data = Color; TransmitDMA(DMA_PINC_DISABLE, &Data, Count); } @@ -98,14 +112,16 @@ const PinMap PinMap_FSMC[] = { {PE_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D05 {PE_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D06 {PE_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D07 - {PE_11, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08 - {PE_12, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09 - {PE_13, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10 - {PE_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11 - {PE_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12 - {PD_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13 - {PD_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14 - {PD_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15 + #if !IS_ANET_ET + {PE_11, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08 + {PE_12, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09 + {PE_13, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10 + {PE_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11 + {PE_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12 + {PD_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13 + {PD_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14 + {PD_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15 + #endif {PD_4, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NOE {PD_5, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NWE {NC, NP, 0} @@ -142,14 +158,18 @@ const PinMap PinMap_FSMC_RS[] = { {PG_4, FSMC_RS(14), FSMC_PIN_DATA}, // FSMC_A14 {PG_5, FSMC_RS(15), FSMC_PIN_DATA}, // FSMC_A15 #endif - {PD_11, FSMC_RS(16), FSMC_PIN_DATA}, // FSMC_A16 - {PD_12, FSMC_RS(17), FSMC_PIN_DATA}, // FSMC_A17 + #if !IS_ANET_ET + {PD_11, FSMC_RS(16), FSMC_PIN_DATA}, // FSMC_A16 + {PD_12, FSMC_RS(17), FSMC_PIN_DATA}, // FSMC_A17 + #endif {PD_13, FSMC_RS(18), FSMC_PIN_DATA}, // FSMC_A18 - {PE_3, FSMC_RS(19), FSMC_PIN_DATA}, // FSMC_A19 - {PE_4, FSMC_RS(20), FSMC_PIN_DATA}, // FSMC_A20 - {PE_5, FSMC_RS(21), FSMC_PIN_DATA}, // FSMC_A21 - {PE_6, FSMC_RS(22), FSMC_PIN_DATA}, // FSMC_A22 - {PE_2, FSMC_RS(23), FSMC_PIN_DATA}, // FSMC_A23 + #if !IS_ANET_ET + {PE_3, FSMC_RS(19), FSMC_PIN_DATA}, // FSMC_A19 + {PE_4, FSMC_RS(20), FSMC_PIN_DATA}, // FSMC_A20 + {PE_5, FSMC_RS(21), FSMC_PIN_DATA}, // FSMC_A21 + {PE_6, FSMC_RS(22), FSMC_PIN_DATA}, // FSMC_A22 + {PE_2, FSMC_RS(23), FSMC_PIN_DATA}, // FSMC_A23 + #endif #ifdef PF0 {PG_13, FSMC_RS(24), FSMC_PIN_DATA}, // FSMC_A24 {PG_14, FSMC_RS(25), FSMC_PIN_DATA}, // FSMC_A25