Fix arm32 FIQ mask in IRQ/ABT/SVC/UND handlers for GICv3 #1748
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This takes care of the problem with unmasked foreign interrupts, but doesn't address the issue with masked local interrupts. In #1742 I've added an idea on how to address the latter problem. Since it's all related perhaps we'd better take care of both issues in the PR. |
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@jenswi-linaro , good idea. I will do this. :) |
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Rebased and refined. |
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Please apply my r-b. |
added 2 commits
August 25, 2017 14:14
Disable native and foreign interrupts in thread handlers for arm32. The tee handlers can decide when the native interrupts can be enabled. Signed-off-by: David Wang <[email protected]> Reviewed-by: Jens Wiklander <[email protected]>
In Arm aarch32 mode, FIQ is not masked by hardware in IRQ mode. For GICv2, IRQ is for foreign interrupt and already masked by hardware in FIQ mode which is used for native interrupt. For GICv3, FIQ is for foreign interrupt. It's not masked by hardware in IRQ mode which is used for natvie interrupt. We need to mask it explicitly. Signed-off-by: David Wang <[email protected]> Reviewed-by: Jens Wiklander <[email protected]>
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In Arm aarch32 mode, FIQ is not masked by hardware in IRQ, ABT, SVC and
UND mode.
For GICv2, IRQ is for foreign interrupt and already masked by hardware
in the exception modes listed above.
For GICv3, FIQ is for foreign interrupt. So, we need to mask FIQ
explicitly in these exception modes.
Signed-off-by: David Wang [email protected]