From 22e8538e7e2f9028f2faceae05586ac241e19796 Mon Sep 17 00:00:00 2001
From: xiaokamikami <fengkehan@bosc.ac.cn>
Date: Mon, 22 Apr 2024 09:56:35 +0800
Subject: [PATCH] update: update clk_gate

---
 Utility                                        | 2 +-
 src/main/scala/huancun/BaseDirectory.scala     | 9 ++-------
 src/main/scala/huancun/utils/SRAMWrapper.scala | 8 ++------
 3 files changed, 5 insertions(+), 14 deletions(-)

diff --git a/Utility b/Utility
index 0010c02d..5511b799 160000
--- a/Utility
+++ b/Utility
@@ -1 +1 @@
-Subproject commit 0010c02d702cf860b1bdeab593f7ee49342f0f5a
+Subproject commit 5511b799eada1e0195d23bea1a2d7ff5549cdf49
diff --git a/src/main/scala/huancun/BaseDirectory.scala b/src/main/scala/huancun/BaseDirectory.scala
index 0d67426f..ca77764a 100644
--- a/src/main/scala/huancun/BaseDirectory.scala
+++ b/src/main/scala/huancun/BaseDirectory.scala
@@ -26,8 +26,7 @@ import chisel3.util.random.LFSR
 import freechips.rocketchip.tilelink.TLMessages
 import freechips.rocketchip.util.{Pow2ClockDivider, ReplacementPolicy}
 import huancun.utils._
-import utility.{Code}
-import utility.ClockGate
+import utility.{ClockGate, Code}
 
 trait BaseDirResult extends HuanCunBundle {
   val idOH = UInt(mshrsAll.W) // which mshr the result should be sent to
@@ -107,13 +106,9 @@ class SubDirectory[T <: Data](
   val resetIdx = RegInit((sets - 1).U)
   val metaArray = Module(new SRAMTemplate(chiselTypeOf(dir_init), sets, ways, singlePort = true, input_clk_div_by_2 = clk_div_by_2))
 
-  val clkGate = Module(new ClockGate)
   val clk_en = RegInit(false.B)
   clk_en := ~clk_en
-  clkGate.io.TE := false.B
-  clkGate.io.E := clk_en
-  clkGate.io.CK := clock
-  val masked_clock = clkGate.io.Q
+  val masked_clock = ClockGate(false.B, clk_en, clock)
 
   val tag_wen = io.tag_w.valid
   val dir_wen = io.dir_w.valid
diff --git a/src/main/scala/huancun/utils/SRAMWrapper.scala b/src/main/scala/huancun/utils/SRAMWrapper.scala
index 6069fbc5..0126b93f 100644
--- a/src/main/scala/huancun/utils/SRAMWrapper.scala
+++ b/src/main/scala/huancun/utils/SRAMWrapper.scala
@@ -3,7 +3,7 @@ package huancun.utils
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.util.Pow2ClockDivider
-import utility.ClockGate
+import utility.{ClockGate}
 
 class SRAMWrapper[T <: Data]
 (
@@ -31,13 +31,9 @@ class SRAMWrapper[T <: Data]
       gen, innerSet, 1, singlePort = true, input_clk_div_by_2 = clk_div_by_2
     ))
 
-    val clkGate = Module(new ClockGate)
     val clk_en = RegInit(false.B)
     clk_en := ~clk_en
-    clkGate.io.TE := false.B
-    clkGate.io.E := clk_en
-    clkGate.io.CK := clock
-    val masked_clock = clkGate.io.Q
+    val masked_clock = ClockGate(false.B, clk_en, clock)
 
     if (clk_div_by_2) {
       sram.clock := masked_clock