diff --git a/Utility b/Utility
index 1b7acf09..5511b799 160000
--- a/Utility
+++ b/Utility
@@ -1 +1 @@
-Subproject commit 1b7acf0998ddf175527aa0609788c3fea1262b1f
+Subproject commit 5511b799eada1e0195d23bea1a2d7ff5549cdf49
diff --git a/src/main/resources/STD_CLKGT_func.v b/src/main/resources/STD_CLKGT_func.v
deleted file mode 100644
index 922f6cff..00000000
--- a/src/main/resources/STD_CLKGT_func.v
+++ /dev/null
@@ -1,34 +0,0 @@
-module STD_CLKGT_func (
-  input  wire TE,
-  input  wire E,
-  input  wire CK,
-  output wire Q
-);
-
-  wire clk_en;
-  reg  clk_en_reg;
-
-  assign clk_en = E | TE;
-
-`ifdef VCS
-  always @(CK or clk_en) begin
-    if (CK == 1'b0)
-      clk_en_reg <= clk_en;
-  end
-`else
-`ifdef VERILATOR_5
-  always @(CK or clk_en) begin
-    if (CK == 1'b0)
-      clk_en_reg <= clk_en;
-  end
-`else
-  always @(posedge CK) 
-    begin
-      clk_en_reg = clk_en;
-    end
-`endif
-`endif
-
-  assign Q = CK & clk_en_reg;
-
-endmodule
diff --git a/src/main/scala/huancun/BaseDirectory.scala b/src/main/scala/huancun/BaseDirectory.scala
index c50a5f63..ca77764a 100644
--- a/src/main/scala/huancun/BaseDirectory.scala
+++ b/src/main/scala/huancun/BaseDirectory.scala
@@ -26,7 +26,7 @@ import chisel3.util.random.LFSR
 import freechips.rocketchip.tilelink.TLMessages
 import freechips.rocketchip.util.{Pow2ClockDivider, ReplacementPolicy}
 import huancun.utils._
-import utility.{Code}
+import utility.{ClockGate, Code}
 
 trait BaseDirResult extends HuanCunBundle {
   val idOH = UInt(mshrsAll.W) // which mshr the result should be sent to
@@ -106,13 +106,9 @@ class SubDirectory[T <: Data](
   val resetIdx = RegInit((sets - 1).U)
   val metaArray = Module(new SRAMTemplate(chiselTypeOf(dir_init), sets, ways, singlePort = true, input_clk_div_by_2 = clk_div_by_2))
 
-  val clkGate = Module(new STD_CLKGT_func)
   val clk_en = RegInit(false.B)
   clk_en := ~clk_en
-  clkGate.io.TE := false.B
-  clkGate.io.E := clk_en
-  clkGate.io.CK := clock
-  val masked_clock = clkGate.io.Q
+  val masked_clock = ClockGate(false.B, clk_en, clock)
 
   val tag_wen = io.tag_w.valid
   val dir_wen = io.dir_w.valid
diff --git a/src/main/scala/huancun/utils/SRAMWrapper.scala b/src/main/scala/huancun/utils/SRAMWrapper.scala
index e8346037..c24a2451 100644
--- a/src/main/scala/huancun/utils/SRAMWrapper.scala
+++ b/src/main/scala/huancun/utils/SRAMWrapper.scala
@@ -3,17 +3,7 @@ package huancun.utils
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.util.Pow2ClockDivider
-
-class STD_CLKGT_func extends BlackBox with HasBlackBoxResource {
-  val io = IO(new Bundle {
-    val TE = Input(Bool())
-    val E  = Input(Bool())
-    val CK = Input(Clock())
-    val Q  = Output(Clock())
-  })
-
-  addResource("/STD_CLKGT_func.v")
-}
+import utility.ClockGate
 
 class SRAMWrapper[T <: Data]
 (
@@ -41,13 +31,9 @@ class SRAMWrapper[T <: Data]
       gen, innerSet, 1, singlePort = true, input_clk_div_by_2 = clk_div_by_2
     ))
 
-    val clkGate = Module(new STD_CLKGT_func)
     val clk_en = RegInit(false.B)
     clk_en := ~clk_en
-    clkGate.io.TE := false.B
-    clkGate.io.E := clk_en
-    clkGate.io.CK := clock
-    val masked_clock = clkGate.io.Q
+    val masked_clock = ClockGate(false.B, clk_en, clock)
 
     if (clk_div_by_2) {
       sram.clock := masked_clock