From 06e1154fc2f73c2a0588f3b9ea6de5e6ea5e6d6a Mon Sep 17 00:00:00 2001 From: LinJiawei Date: Sun, 17 Jan 2021 17:18:25 +0800 Subject: [PATCH 1/2] SinglePortSRAM: place 'mem.read' out of 'otherwise' block --- src/main/scala/utils/SRAMWrapper.scala | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main/scala/utils/SRAMWrapper.scala b/src/main/scala/utils/SRAMWrapper.scala index e8e27601fd..598dd027f8 100644 --- a/src/main/scala/utils/SRAMWrapper.scala +++ b/src/main/scala/utils/SRAMWrapper.scala @@ -67,10 +67,11 @@ class SinglePortSRAM(set: Int, way: Int, width: Int) extends SRAMTemplate { val wmask = Input(UInt(way.W)) }) val mem = SyncReadMem(set, Vec(way, UInt(width.W))) - io.rdata := mem.read(io.addr, io.ren) + val addr = io.addr when(io.wen){ - mem.write(io.addr, VecInit(Seq.fill(way)(io.wdata)), io.wmask.asBools()) + mem.write(addr, VecInit(Seq.fill(way)(io.wdata)), io.wmask.asBools()) } + io.rdata := mem.read(addr, io.ren && !io.wen) override def read(addr: UInt, ren: Bool): Vec[UInt] = { io.addr := addr @@ -147,7 +148,7 @@ class SRAMWrapper[T <: Data] } val (ren, wen) = (io.r.req.valid, io.w.req.valid || resetState) - val realRen = (if (singlePort) ren && !wen else ren) + val realRen = ren //(if (singlePort) ren && !wen else ren) do mutex inside inner sram val setIdx = Mux(resetState, resetSet, if(singlePort) Mux(io.w.req.valid, io.w.req.bits.setIdx, io.r.req.bits.setIdx) From 1ce26f6d9bd5880cb6bc8fe6e155923e622f520d Mon Sep 17 00:00:00 2001 From: Yinan Xu Date: Fri, 22 Jan 2021 12:45:43 +0800 Subject: [PATCH 2/2] makefile: remove -X verilog to support --repl-seq-mem --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index fb0610fc44..e4551293ef 100644 --- a/Makefile +++ b/Makefile @@ -27,7 +27,7 @@ help: $(TOP_V): $(SCALA_FILE) mkdir -p $(@D) - mill XiangShan.test.runMain $(SIMTOP) -X verilog -td $(@D) --full-stacktrace --output-file $(@F) --disable-all --fpga-platform --remove-assert $(SIM_ARGS) + mill XiangShan.test.runMain $(SIMTOP) -td $(@D) --full-stacktrace --output-file $(@F) --disable-all --fpga-platform --remove-assert --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf $(SIM_ARGS) # mill XiangShan.runMain top.$(TOP) -X verilog -td $(@D) --output-file $(@F) --infer-rw $(FPGATOP) --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf # $(MEM_GEN) $(@D)/$(@F).conf >> $@ # sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $@