From d15c243328aae56cfe5914c3540ed6d89066c9b0 Mon Sep 17 00:00:00 2001 From: Xiaokun-Pei Date: Tue, 27 Aug 2024 10:28:20 +0800 Subject: [PATCH] =?UTF-8?q?PTW,=20RVH:=20init=20the=20A=E3=80=81D=E3=80=81?= =?UTF-8?q?PPN=20of=20fake=20pte=20to=20avoid=20wrong=20pf=20and=20wrong?= =?UTF-8?q?=20gpaddr=20in=20L1TLB=20(#3423)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1. init a、d、ppn of fake pte 2. modify the logic of isPf and isAf --- src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala b/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala index bd6674ef22..68029de74a 100644 --- a/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala +++ b/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala @@ -186,6 +186,10 @@ class PTW()(implicit p: Parameters) extends XSModule with HasPtwConst with HasPe fake_pte.perm.r := true.B fake_pte.perm.w := true.B fake_pte.perm.x := true.B + fake_pte.perm.a := true.B + fake_pte.perm.d := true.B + fake_pte.ppn := ppn(ppnLen - 1, 0) + fake_pte.ppn_high := ppn(ptePPNLen - 1, ppnLen) io.req.ready := idle val ptw_resp = Wire(new PtwMergeResp)