make verilog fail

[sasakiakaya]

Before start

• I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集本身的问题。
• I have read the XiangShan Documents. 我已经阅读过香山文档。
• I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
• I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。

Describe the bug

          total        used        free      shared  buff/cache   available

Mem: 60 1 55 0 3 58
Swap: 39 0 39

Expected behavior

run make verilog should be PASS

To Reproduce

make init
make verilog

Environment

• XiangShan branch: master e80f666
  OS: ubuntu 22.04
  mem: 60 phy+30 swap
  jdk:17

Additional context

No response

[Ma-YX]

Please ensure that you have thoroughly read the XiangShan Documents, especially https://docs.xiangshan.cc/zh-cn/latest/tools/xsenv/.

According to your log, some files are lost in submodule huancun; you can double check whether your submodules are correctly cloned.

Before you start compiling XiangShan, make sure to execute the following commands to ensure the environment are set up correctly in xs-env folder:
sudo -s ./setup-tools.sh (for first time)
source setup.sh
sudo -s ./setup-tools.sh
./setup.sh

And make sure to clone essential submodules in XiangShan folder:
make init

For details, please read XiangShan Documents.