From 9a3d8eb2d19debb94bd82abfc0a9cf5fcb9dfbaa Mon Sep 17 00:00:00 2001 From: sinceforYy <1017657683@qq.com> Date: Fri, 13 Sep 2024 10:51:54 +0800 Subject: [PATCH 1/4] fix(csr, difftest): remove skip csr and add diffevent to csr Remove skip csr for xip, menvcfg, henvcfg to diff Add diffevent to support no reg interrupt pending --- .../xiangshan/backend/fu/NewCSR/NewCSR.scala | 40 ++++++++++++++++--- 1 file changed, 35 insertions(+), 5 deletions(-) diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala index e09586d076..e19891da64 100644 --- a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala +++ b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala @@ -774,10 +774,7 @@ class NewCSR(implicit val p: Parameters) extends Module (addr >= CSRs.mcycle.U) && (addr <= CSRs.mhpmcounter31.U) || (addr === mcountinhibit.addr.U) || (addr >= CSRs.cycle.U) && (addr <= CSRs.hpmcounter31.U) || - (addr === CSRs.mip.U) || (addr === CSRs.sip.U) || (addr === CSRs.vsip.U) || - (addr === CSRs.hip.U) || (addr === CSRs.mvip.U) || (addr === CSRs.hvip.U) || - Cat(aiaSkipCSRs.map(_.addr.U === addr)).orR || - (addr === CSRs.stimecmp.U) + Cat(aiaSkipCSRs.map(_.addr.U === addr)).orR ) // flush @@ -1286,7 +1283,7 @@ class NewCSR(implicit val p: Parameters) extends Module diffCSRState.mcause := mcause.rdata.asUInt diffCSRState.scause := scause.rdata.asUInt diffCSRState.satp := satp.rdata.asUInt - diffCSRState.mip := mip.regOut.asUInt + diffCSRState.mip := mip.rdata.asUInt diffCSRState.mie := mie.rdata.asUInt diffCSRState.mscratch := mscratch.rdata.asUInt diffCSRState.sscratch := sscratch.rdata.asUInt @@ -1342,6 +1339,39 @@ class NewCSR(implicit val p: Parameters) extends Module diffHCSRState.vsatp := vsatp.rdata.asUInt diffHCSRState.vsscratch := vsscratch.rdata.asUInt + val platformIRPMeipChange = !platformIRP.MEIP && RegNext(platformIRP.MEIP) || + platformIRP.MEIP && !RegNext(platformIRP.MEIP) || + !fromAIA.meip && RegNext(fromAIA.meip) || + fromAIA.meip && !RegNext(fromAIA.meip) + val platformIRPMtipChange = !platformIRP.MTIP && RegNext(platformIRP.MTIP) || platformIRP.MTIP && !RegNext(platformIRP.MTIP) + val platformIRPMsipChange = !platformIRP.MSIP && RegNext(platformIRP.MSIP) || platformIRP.MSIP && !RegNext(platformIRP.MSIP) + val platformIRPSeipChange = !platformIRP.SEIP && RegNext(platformIRP.SEIP) || + platformIRP.SEIP && !RegNext(platformIRP.SEIP) || + !fromAIA.seip && RegNext(fromAIA.seip) || + fromAIA.seip && !RegNext(fromAIA.seip) + val platformIRPStipChange = !sstcIRGen.o.STIP && RegNext(sstcIRGen.o.STIP) || sstcIRGen.o.STIP && !RegNext(sstcIRGen.o.STIP) + val platformIRPVseipChange = !platformIRP.VSEIP && RegNext(platformIRP.VSEIP) || + platformIRP.VSEIP && !RegNext(platformIRP.VSEIP) || + !hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt) && RegNext(hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt)) || + hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt) && !RegNext(hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt)) + val platformIRPVstipChange = !platformIRP.VSTIP && RegNext(platformIRP.VSTIP) || platformIRP.VSTIP && !RegNext(platformIRP.VSTIP) + val lcofiReqChange = !lcofiReq && RegNext(lcofiReq) || lcofiReq && !RegNext(lcofiReq) + + val diffNonRegInterruptPendingEvent = DifftestModule(new DiffNonRegInterruptPendingEvent) + diffNonRegInterruptPendingEvent.coreid := hartId + diffNonRegInterruptPendingEvent.valid := platformIRPMeipChange || platformIRPMtipChange || platformIRPMsipChange || + platformIRPSeipChange || platformIRPStipChange || + platformIRPVseipChange || platformIRPVstipChange || + lcofiReqChange + diffNonRegInterruptPendingEvent.platformIRPMeip := platformIRP.MEIP || fromAIA.meip + diffNonRegInterruptPendingEvent.platformIRPMtip := platformIRP.MTIP + diffNonRegInterruptPendingEvent.platformIRPMsip := platformIRP.MSIP + diffNonRegInterruptPendingEvent.platformIRPSeip := platformIRP.SEIP || fromAIA.seip + diffNonRegInterruptPendingEvent.platformIRPStip := sstcIRGen.o.STIP + diffNonRegInterruptPendingEvent.platformIRPVseip := platformIRP.VSEIP || hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt) + diffNonRegInterruptPendingEvent.platformIRPVstip := sstcIRGen.o.VSTIP + diffNonRegInterruptPendingEvent.localCounterOverflowInterruptReq := lcofiReq + } } From 9d9917792ed84c96c13864934065d628022c9abf Mon Sep 17 00:00:00 2001 From: sinceforYy <1017657683@qq.com> Date: Mon, 30 Sep 2024 18:25:34 +0800 Subject: [PATCH 2/4] submodule(difftest): bump difftest * difftest commit: fbd72a2e718dc37b924bc3e7239d86f8452bd428 including: * fix(config): allow 8GB memory as default for unknown CPUs (#466) * fix(csr): add support non register interrupt pending (#465) * fix(csr): fix struct non-reg interrupt pending to order (#469) * palladium: Build DPILIB_EMU shared library as separated targets (#468) * Difftest: Use file API compatible with with Java8 (#467) * Batch: pack Batch param to facilitate migration between DPIC/PCIe (#474) --- difftest | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/difftest b/difftest index ada5ab1bf2..fbd72a2e71 160000 --- a/difftest +++ b/difftest @@ -1 +1 @@ -Subproject commit ada5ab1bf29244df879c98c84afb7f33ead24181 +Subproject commit fbd72a2e718dc37b924bc3e7239d86f8452bd428 From fb095852037fc400e2007476c3c5df19a7a0c510 Mon Sep 17 00:00:00 2001 From: sinceforYy <1017657683@qq.com> Date: Mon, 30 Sep 2024 18:34:16 +0800 Subject: [PATCH 3/4] submodule(ready-to-run): bump ready-to-run --- ready-to-run | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ready-to-run b/ready-to-run index 31918822e4..6736823ec1 160000 --- a/ready-to-run +++ b/ready-to-run @@ -1 +1 @@ -Subproject commit 31918822e474d426592ad3d3b42e368a5737565d +Subproject commit 6736823ec116284d175d445494f680f9d7f00ece From e624459e52cc41b6929950dab9a0ae250a98186f Mon Sep 17 00:00:00 2001 From: Haojin Tang Date: Tue, 1 Oct 2024 14:59:50 +0800 Subject: [PATCH 4/4] fix(CSR): fix `platformIRPVstipChange` assignment --- src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala index e19891da64..c91ed33392 100644 --- a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala +++ b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala @@ -1354,7 +1354,7 @@ class NewCSR(implicit val p: Parameters) extends Module platformIRP.VSEIP && !RegNext(platformIRP.VSEIP) || !hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt) && RegNext(hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt)) || hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt) && !RegNext(hgeip.rdata.asUInt(hstatus.regOut.VGEIN.asUInt)) - val platformIRPVstipChange = !platformIRP.VSTIP && RegNext(platformIRP.VSTIP) || platformIRP.VSTIP && !RegNext(platformIRP.VSTIP) + val platformIRPVstipChange = !sstcIRGen.o.VSTIP && RegNext(sstcIRGen.o.VSTIP) || sstcIRGen.o.VSTIP && !RegNext(sstcIRGen.o.VSTIP) val lcofiReqChange = !lcofiReq && RegNext(lcofiReq) || lcofiReq && !RegNext(lcofiReq) val diffNonRegInterruptPendingEvent = DifftestModule(new DiffNonRegInterruptPendingEvent)