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STM32H7 Multicore FIR is a finite impulse response filter implementation for a family of multicore processors from STM32 - family H7. The algorithm runs in parallel on both cores and this helps users to achieve high sampling frequencies or higher FIR filter order.
This document is for the latest STM32H7_MulticoreFIR 1.0.0 release and later.
Built with:
- STM32CubeIDE Version: 1.5.1
- Build: 9029_20201210_1234 (UTC)
For successful import of the project in STM32CubeIDE is needed:
- In the main menu go to File
- Choose option Open Projects from File System...
- In option Import Source choose the cloned repository
Note: For multicore debugging please read Multicore debugging
- Running on frequency 480 MHz
- Uses ADC1, DAC1, TIM3 and L1 Cache
- Running on frequency 240 MHz
- Uses -
- Single Ended
- Clock Prescaler /4
- Sampling frequency is 192KHz
- Conversion is triggered with TIM3
- Resolution is 16Bit
- DMA stores data after conversion and trigger conversion complete ISR
- Mode - Connected to external pin only
- Output buffer enabled
- Sampling frequency is 192KHz
- Resolution is 12Bit
- DAC1 output is mapped to pin PA4
- ADC1 output is mapped to pin PF11
FIR Filter algorithm calculation is split between two cores. Inside settings header you can easily change the splitter macro that defines how many samples are calculated on core M7 and core M4. On the UML diagram below you can see FIR filter execution flow. Delay of the FIR algorithm is equal to the sampling period.
For the FIR filter design you can use Matlab filter designer. The example below is from this package and coefficient from this design are currently used in the settings source.
Warning: If you change the order of the filter, you have to change also macro FILTER_ORDER inside settings header
The measurement was made with STM32H7_MulticoreFIR release v1.0.0 and eval board NUCLEO-H755ZI-Q
Core M7: 480 MHz Core M4: 240 MHz Filter Order: 45 Splitter : 35 ADC1 resolution : 16 bit DAC1 resolution : 12 bit Sampling frequency: 192 KHz
Measurement was made with a logic analyzer. On the picture below you can see FIR algorithm calculation time.
- Number 1 is core M7. Logical high means that ADC1 conversion completed interrupt was already triggered and the prior result of FIR algorithm is written to DAC1. Core M7 then triggers the partial FIR calculation on core M4 with SEV interrupt.
- Number 2 is core M4. Logical high means that SEV interrupt triggered by core M7 is executing. After finishing the FIR algorithm calculation the logic level goes back to low. Crucial is to tune core M4 to end with the calculation before the ADC1 conversion completed interrupt is triggered again on the core M7.
Measurement was made with the soundcard (192KHz sampling frequency and 32-bit resolution). Despite that, the results are not so exact and it would be good to redo measurement with an oscilloscope.
Signal was generated with JDS2800 Signal Generator Digital Control Dual-channel DDS Function Signal Generator.
The measurement was made with STM32H7_MulticoreFIR release v1.0.0 and eval board NUCLEO-H755ZI-Q
Core M7: 480 MHz Core M4: 240 MHz Filter Order: 45 Cutoff frequency: 15 KHz low pass filter Splitter : 35 ADC1 resolution : 16 bit DAC1 resolution : 12 bit Sampling frequency: 192 KHz FIR – Taylor Window, Nbar 4, Sidelobe Level 30
The picture below shows captured 15 KHz LP filter magnitude response simulated in Matlab and measured on real hardware with soundcard oscilloscope.
The measurement was made with STM32H7_MulticoreFIR release v1.0.0 and eval board NUCLEO-H755ZI-Q
Core M7: 480 MHz Core M4: 240 MHz Filter Order: 45 Cutoff frequency: 5 KHz high pass filter Splitter : 35 ADC1 resolution : 16 bit DAC1 resolution : 12 bit Sampling frequency: 192 KHz FIR – Taylor Window, Nbar 4, Sidelobe Level 30
The picture below shows captured 5 KHz HP filter magnitude response simulated in Matlab and measured on real hardware with soundcard oscilloscope.
The measurement was made with STM32H7_MulticoreFIR release v1.0.0 and eval board NUCLEO-H755ZI-Q
Core M7: 480 MHz Core M4: 240 MHz Filter Order: 45 Cutoff frequency: 2KHz - 18KHz band pass filter Splitter : 35 ADC1 resolution : 16 bit DAC1 resolution : 12 bit Sampling frequency: 192 KHz FIR – Taylor Window, Nbar 4, Sidelobe Level 30
The picture below shows captured 2KHz - 18KHz BP filter magnitude response simulated in Matlab and measured on real hardware with soundcard oscilloscope.
The STM32H7 Multicore FIR is licensed under the terms of the DBAD license and is available for free.