From e468b7c8a6c1b181c02e2e5989aa10d728a49e16 Mon Sep 17 00:00:00 2001 From: Joshua Milas Date: Fri, 26 May 2023 08:08:23 -0400 Subject: [PATCH 1/3] Commit what works --- mcu/attiny-hal/src/lib.rs | 5 ++++ mcu/attiny-hal/src/spi.rs | 63 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/mcu/attiny-hal/src/lib.rs b/mcu/attiny-hal/src/lib.rs index 9dee18cdc6..9648311cc7 100644 --- a/mcu/attiny-hal/src/lib.rs +++ b/mcu/attiny-hal/src/lib.rs @@ -68,6 +68,11 @@ pub mod adc; #[cfg(all(feature = "device-selected", not(feature = "attiny2313")))] pub use adc::Adc; +#[cfg(feature = "attiny85")] +pub mod spi; +#[cfg(feature = "attiny85")] +pub use spi::Spi; + #[cfg(feature = "device-selected")] pub mod port; #[cfg(feature = "device-selected")] diff --git a/mcu/attiny-hal/src/spi.rs b/mcu/attiny-hal/src/spi.rs index 88c5ea0ed2..c4189da6c7 100644 --- a/mcu/attiny-hal/src/spi.rs +++ b/mcu/attiny-hal/src/spi.rs @@ -39,3 +39,66 @@ avr_hal_generic::impl_spi! { miso: port::PA2, cs: port::PA6, } + + +#[cfg(feature = "attiny85")] +pub type Spi = avr_hal_generic::spi::Spi< + crate::Attiny, + crate::pac::USI, + port::PB2, //SCLK + port::PB0, //MOSI + port::PB1, //MISO + port::PB4, //Chip select + >; +#[cfg(feature = "attiny85")] +impl crate::spi::SpiOps for crate::pac::USI { + fn raw_setup(&mut self, _settings: &Settings) { + self.usicr.write(|w| { + w.usiwm().three_wire(); + w.usics().no_clock() + }); + } + + fn raw_release(&mut self) { + self.usicr.write(|w| { + w.usiwm().disabled() + }); + } + + fn raw_check_iflag(&self) -> bool { + // USIOIF is set when the counter overflows, from the datasheet + // ... "Can therefor be used to determine when a transfer is completed" (p 109) + self.usisr.read().usioif().bit_is_set() + } + + fn raw_read(&self) -> u8 { + // TODO how to determine if its read fully? + // USIOIF tells if 8 cycles has completed, should we check first? + self.usibr.read().bits() + } + + fn raw_write(&mut self, byte: u8) { + self.usidr.write(|w| { + w.bits(byte) + }); + + // Make sure the finished bit is cleared (by setting it) + self.usisr.write(|w| { + w.usioif().set_bit() + }); + + // clock bytes out + for _ in 0..16 { + self.usicr.write(|w| { + //w.usiwm().three_wire(); + //w.usics().no_clock(); + w.usiclk().set_bit(); + w.usitc().set_bit() + }); + avr_device::asm::nop(); + avr_device::asm::nop(); + avr_device::asm::nop(); + } + // USIOIF should be set now + } +} From fee667fadb648b544ca8c30bdf2bc6279cfbf9ea Mon Sep 17 00:00:00 2001 From: Joshua Milas Date: Fri, 26 May 2023 18:36:23 -0400 Subject: [PATCH 2/3] Got SPI master to work --- mcu/attiny-hal/src/spi.rs | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/mcu/attiny-hal/src/spi.rs b/mcu/attiny-hal/src/spi.rs index c4189da6c7..40472b3bea 100644 --- a/mcu/attiny-hal/src/spi.rs +++ b/mcu/attiny-hal/src/spi.rs @@ -45,17 +45,18 @@ avr_hal_generic::impl_spi! { pub type Spi = avr_hal_generic::spi::Spi< crate::Attiny, crate::pac::USI, - port::PB2, //SCLK - port::PB0, //MOSI - port::PB1, //MISO - port::PB4, //Chip select + port::PB2, + port::PB1, + port::PB0, + port::PB4, >; #[cfg(feature = "attiny85")] -impl crate::spi::SpiOps for crate::pac::USI { +impl crate::spi::SpiOps for crate::pac::USI { fn raw_setup(&mut self, _settings: &Settings) { self.usicr.write(|w| { w.usiwm().three_wire(); - w.usics().no_clock() + w.usics().ext_pos(); + w.usiclk().set_bit() }); } @@ -88,10 +89,11 @@ impl crate::spi::SpiOps Date: Fri, 26 May 2023 18:38:27 -0400 Subject: [PATCH 3/3] Cleaned up comments --- mcu/attiny-hal/src/spi.rs | 5 ----- 1 file changed, 5 deletions(-) diff --git a/mcu/attiny-hal/src/spi.rs b/mcu/attiny-hal/src/spi.rs index 40472b3bea..fd1b25c488 100644 --- a/mcu/attiny-hal/src/spi.rs +++ b/mcu/attiny-hal/src/spi.rs @@ -67,8 +67,6 @@ impl crate::spi::SpiOps bool { - // USIOIF is set when the counter overflows, from the datasheet - // ... "Can therefor be used to determine when a transfer is completed" (p 109) self.usisr.read().usioif().bit_is_set() } @@ -83,12 +81,10 @@ impl crate::spi::SpiOps