From 6b4be880096daf9f0ea1822afd9c63c25f082266 Mon Sep 17 00:00:00 2001 From: antirez Date: Tue, 24 Jan 2023 09:32:34 +0100 Subject: [PATCH] CC1101 custom presets updated. --- app_subghz.c | 5 ++- custom_presets.h | 95 +++++++++++++++++++++++++++++++++++++----------- 2 files changed, 76 insertions(+), 24 deletions(-) diff --git a/app_subghz.c b/app_subghz.c index d9dd0e0d7ef..b503e0bfc49 100644 --- a/app_subghz.c +++ b/app_subghz.c @@ -23,8 +23,9 @@ ProtoViewModulation ProtoViewModulations[] = { FuriHalSubGhzPreset2FSKDev476Async, NULL}, {"TPMS 1 (FSK)", NULL, 0, (uint8_t*)protoview_subghz_tpms1_fsk_async_regs}, {"TPMS 2 (OOK)", NULL, 0, (uint8_t*)protoview_subghz_tpms2_ook_async_regs}, - {"TPMS 3 (FSK)", NULL, 0, (uint8_t*)protoview_subghz_tpms3_fsk_async_regs}, - {"TPMS 4 (FSK)", NULL, 0, (uint8_t*)protoview_subghz_tpms4_fsk_async_regs}, + {"TPMS 3 (GFSK)", NULL, 0, (uint8_t*)protoview_subghz_tpms3_gfsk_async_regs}, + {"OOK 40kBaud", NULL, 0, (uint8_t*)protoview_subghz_40k_ook_async_regs}, + {"FSK 40kBaud", NULL, 0, (uint8_t*)protoview_subghz_40k_fsk_async_regs}, {NULL, NULL, 0, NULL} /* End of list sentinel. */ }; diff --git a/custom_presets.h b/custom_presets.h index 19184593330..fe459a18b54 100644 --- a/custom_presets.h +++ b/custom_presets.h @@ -1,5 +1,4 @@ #include - /* ========================== DATA RATE SETTINGS =============================== * * This is how to configure registers MDMCFG3 and MDMCFG4. @@ -159,8 +158,55 @@ static const uint8_t protoview_subghz_tpms2_ook_async_regs[][2] = { {0, 0xC0}, {0,0}, {0,0}, {0,0} }; +/* GFSK 19k dev, 325 Khz filter, 20kBaud. Different AGI settings. + * Works well with Toyota. */ +static uint8_t protoview_subghz_tpms3_gfsk_async_regs[][2] = { + /* GPIO GD0 */ + {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input + + /* Frequency Synthesizer Control */ + {CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz + + /* Packet engine */ + {CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening + {CC1101_PKTCTRL1, 0x04}, + + // // Modem Configuration + {CC1101_MDMCFG0, 0x00}, + {CC1101_MDMCFG1, 0x02}, // 2 is the channel spacing exponet: not used + {CC1101_MDMCFG2, 0x10}, // GFSK without any other check + {CC1101_MDMCFG3, 0x93}, // Data rate is 20kBaud + {CC1101_MDMCFG4, 0x59}, // Rx bandwidth filter is 325 kHz + {CC1101_DEVIATN, 0x34}, // Deviation 19.04 Khz. + + /* Main Radio Control State Machine */ + {CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us) + + /* Frequency Offset Compensation Configuration */ + {CC1101_FOCCFG, + 0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off + + /* Automatic Gain Control */ + {CC1101_AGCCTRL0, 0x80}, + {CC1101_AGCCTRL1, 0x58}, + {CC1101_AGCCTRL2, 0x87}, + + /* Wake on radio and timeouts control */ + {CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours + + /* Frontend configuration */ + {CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer + {CC1101_FREND1, 0x56}, + + /* End */ + {0, 0}, + + /* CC1101 2FSK PATABLE. */ + {0xC0, 0}, {0,0}, {0,0}, {0,0} +}; + /* 40 KBaud, 2FSK, 28 kHz deviation, 270 Khz bandwidth filter. */ -static uint8_t protoview_subghz_tpms3_fsk_async_regs[][2] = { +static uint8_t protoview_subghz_40k_fsk_async_regs[][2] = { /* GPIO GD0 */ {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input @@ -207,49 +253,54 @@ static uint8_t protoview_subghz_tpms3_fsk_async_regs[][2] = { {0xC0, 0}, {0,0}, {0,0}, {0,0} }; -/* FSK 19k dev, 325 Khz filter, 20kBaud. Works well with Toyota. */ -static uint8_t protoview_subghz_tpms4_fsk_async_regs[][2] = { +/* This is like the default Flipper OOK 640Khz bandwidth preset, but + * the bandwidth is changed to 40kBaud, in order to receive signals + * with a pulse width ~25us/30us. */ +static const uint8_t protoview_subghz_40k_ook_async_regs[][2] = { /* GPIO GD0 */ {CC1101_IOCFG0, 0x0D}, // GD0 as async serial data output/input - /* Frequency Synthesizer Control */ - {CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz + /* FIFO and internals */ + {CC1101_FIFOTHR, 0x07}, // The only important bit is ADC_RETENTION /* Packet engine */ {CC1101_PKTCTRL0, 0x32}, // Async, continious, no whitening - {CC1101_PKTCTRL1, 0x04}, - // // Modem Configuration - {CC1101_MDMCFG0, 0x00}, - {CC1101_MDMCFG1, 0x02}, // 2 is the channel spacing exponet: not used - {CC1101_MDMCFG2, 0x10}, // GFSK without any other check - {CC1101_MDMCFG3, 0x93}, // Data rate is 20kBaud - {CC1101_MDMCFG4, 0x59}, // Rx bandwidth filter is 325 kHz - {CC1101_DEVIATN, 0x34}, // Deviation 19.04 Khz. + /* Frequency Synthesizer Control */ + {CC1101_FSCTRL1, 0x06}, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz + + // Modem Configuration + {CC1101_MDMCFG0, 0x00}, // Channel spacing is 25kHz + {CC1101_MDMCFG1, 0x00}, // Channel spacing is 25kHz + {CC1101_MDMCFG2, 0x30}, // Format ASK/OOK, No preamble/sync + {CC1101_MDMCFG3, 0x93}, // Data rate is 40kBaud + {CC1101_MDMCFG4, 0x1A}, // Rx BW filter is 650.000kHz /* Main Radio Control State Machine */ {CC1101_MCSM0, 0x18}, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us) /* Frequency Offset Compensation Configuration */ {CC1101_FOCCFG, - 0x16}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off + 0x18}, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off /* Automatic Gain Control */ - {CC1101_AGCCTRL0, 0x80}, - {CC1101_AGCCTRL1, 0x58}, - {CC1101_AGCCTRL2, 0x87}, + {CC1101_AGCCTRL0, + 0x91}, // 10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary + {CC1101_AGCCTRL1, + 0x0}, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET + {CC1101_AGCCTRL2, 0x07}, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB /* Wake on radio and timeouts control */ {CC1101_WORCTRL, 0xFB}, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours /* Frontend configuration */ - {CC1101_FREND0, 0x10}, // Adjusts current TX LO buffer - {CC1101_FREND1, 0x56}, + {CC1101_FREND0, 0x11}, // Adjusts current TX LO buffer + high is PATABLE[1] + {CC1101_FREND1, 0xB6}, // /* End */ {0, 0}, - /* CC1101 2FSK PATABLE. */ - {0xC0, 0}, {0,0}, {0,0}, {0,0} + /* CC1101 OOK PATABLE. */ + {0, 0xC0}, {0,0}, {0,0}, {0,0} };