From a25d821917bc518a30252ab9f73ffbcf846461ed Mon Sep 17 00:00:00 2001 From: Wirut Getbamrung Date: Fri, 8 May 2020 11:17:08 +0700 Subject: [PATCH 1/2] [sonic-device-data]: update tests function to latest version --- src/sonic-device-data/tests/config_checker | 14 +++- src/sonic-device-data/tests/permitted_list | 83 +++++++++++++++++----- 2 files changed, 79 insertions(+), 18 deletions(-) diff --git a/src/sonic-device-data/tests/config_checker b/src/sonic-device-data/tests/config_checker index 6e59d1f44ce4..ee39d5d9bbf1 100755 --- a/src/sonic-device-data/tests/config_checker +++ b/src/sonic-device-data/tests/config_checker @@ -30,10 +30,14 @@ def check_file(file_name): continue p = line.split("=", 1)[0] + # Remove trailing chip name "bcm8869x" + p = re.sub(r"\.bcm8869x(_adapter|_[a-z]\d)?$", "", p) # Remove trailing unit ".$" p = re.sub(r"\.[0-9]+$", '', p) # Remove trailing port name - p = re.sub(r"_[cxg]e(\d+)?$", '', p) + p = re.sub(r"_[cxg][de](\d+)?$", '', p) + # Remove trailing port id "{id/number}" + p = re.sub(r"\{.*\}", '', p) # Remove trailing port name example p = re.sub(r"_$", '', p) # Remove trailing port number @@ -45,6 +49,12 @@ def check_file(file_name): p = re.sub(r"_lane\d+$", '', p) # Remove trailing "{.}$" p = re.sub(r"{[0-9]+\.[0-9]+}$", '', p) + # Remove trailing phy with number + p = re.sub(r"_phy\d+$", '', p) + # Remove trailing phase of data granularity + p = re.sub(r"_data_granularity_\w\w$", '_data_granularity', p) + # Remove trailing type of port_init_speed + p = re.sub(r"^port_init_speed_\w+$", 'port_init_speed', p) if not check_property(p): file_ok = False @@ -84,4 +94,4 @@ def main(argv): sys.exit(-1) if __name__ == "__main__": - main(sys.argv[1:]) + main(sys.argv[1:]) \ No newline at end of file diff --git a/src/sonic-device-data/tests/permitted_list b/src/sonic-device-data/tests/permitted_list index 3d85569afe58..a7e51d2d13e5 100644 --- a/src/sonic-device-data/tests/permitted_list +++ b/src/sonic-device-data/tests/permitted_list @@ -2,6 +2,7 @@ arl_clean_timeout_usec asf_mem_profile bcm_linkscan_interval bcm_num_cos +default_cpu_tx_queue bcm_stat_flags bcm_stat_interval bcm_stat_jumbo @@ -13,17 +14,20 @@ bcm56340_config cdma_timeout_usec core_clock_frequency ctr_evict_enable +device_clock_frequency dma_desc_timeout_usec dport_map_direct dport_map_enable dport_map_indexed dport_map_port dpp_clock_ratio +dpr_clock_frequency ext_sram_freq ext_tcam_freq force_core_pll fpem_mem_entries higig2_hdr_mode +ifp_inports_support_enable ipmc_do_vlan ipv6_lpm_128b_enable knet_filter_persist @@ -33,6 +37,7 @@ l2mod_dma_intr_enable l2xmsg_hostbuf_size l2xmsg_mode l3_alpm_enable +l3_alpm_ipv6_128b_bkt_rsvd l3_intf_vlan_split_egress l3_max_ecmp_mode l3_mem_entries @@ -53,6 +58,7 @@ miim_intr_enable miim_timeout_usec mmu_init_config mmu_lossless +mmu_port_num_mc_queue module_64ports multicast_l2_r multicast_l2_range @@ -95,6 +101,8 @@ phy_tx_polarity_flip phy_xaui_rx_polarity_flip phy_xaui_tx_polarity_flip physical_ports +pll_bypass +port_flex_enable port_init_autoneg port_init_cl72 port_init_speed @@ -115,6 +123,8 @@ schan_intr_enable schan_timeout_usec serdes_automed serdes_automedium +serdes_core_rx_polarity_flip_physical +serdes_core_tx_polarity_flip_physical serdes_driver_current serdes_fiber_pref serdes_firmware_mode @@ -123,6 +133,7 @@ serdes_pre_driver_current serdes_preemphasis serdes_rx_los serdes_sgmii_m +serdes_tx_taps skip_L2_USER_ENTRY sram_scan_enable stable_size @@ -140,29 +151,69 @@ xgxs_lcpll_xtal_refclk xgxs_pdetect xgxs_rx_lane_map xgxs_tx_lane_map +ifp_inports_support_enable +port_flex_enable +pdma_descriptor_prefetch_enable +pktdma_poll_mode_channel_bitmap ccm_dma_enable ccmdma_intr_enable phy_enable -phy_null -pll_bypass init_all_modules -serdes_core_tx_polarity_flip_physical -serdes_core_rx_polarity_flip_physical -dpr_clock_frequency -device_clock_frequency -port_flex_enable +port_fec +appl_enable_intr_init +custom_feature_ucode_path +dma_desc_aggregator_buff_size_kb +dma_desc_aggregator_chain_length_max +dma_desc_aggregator_enable_specific_mdb_fec +dma_desc_aggregator_enable_specific_mdb_lpm +dma_desc_aggregator_timeout_usec +dram_phy_tune_mode_on_init +dtm_flow_mapping_mode_region +dtm_flow_nof_remote_cores_region +fabric_connect_mode +fabric_logical_port_base +l4_protocols_load_balancing_enable +lane_to_serdes_map_fabric +lane_to_serdes_map_nif +mdb_profile +mem_cache_enable_ecc +mem_cache_enable_parity +num_olp_tm_ports +outlif_logical_to_physical_phase_map +outlif_physical_phase_data_granularity +pmf_sexem3_stage +polled_irq_delay +polled_irq_mode +port_priorities +protocol_traps_mode +rif_id_max +sat_enable +serdes_fabric_clk_freq_in +serdes_fabric_clk_freq_out +serdes_nif_clk_freq_in +serdes_nif_clk_freq_out +soc_family +stable_filename +stable_location +suppress_unknown_prop_warnings +sw_state_max_size +system_headers_mode +tm_port_header_type_in +tm_port_header_type_out +trunk_group_max_members +ucode_port +led_fw_path +l2xlrn_thread_interval +l2xlrn_intr_en +serdes_lane_config_media_type +sai_preinit_cmd_file +sai_preinit_warmboot_cmd_file +sai_postinit_cmd_file +sai_postinit_warmboot_cmd_file help_cli_enable -ifp_inports_support_enable memlist_enable -pbmp_gport_stack -reglist_enable -cls_cmd_daemon serdes_lane_config_dfe serdes_fec_enable pbmp_gport_stack reglist_enable -scache_filename -ifp_inports_support_enable -port_fec -serdes_tx_taps - +scache_filename \ No newline at end of file From dffa4b96ba25f65f49f83b78674f71302350e558 Mon Sep 17 00:00:00 2001 From: Wirut Getbamrung Date: Fri, 8 May 2020 11:18:57 +0700 Subject: [PATCH 2/2] [platform/cel]: fix invalid version --- platform/broadcom/platform-modules-cel.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/broadcom/platform-modules-cel.mk b/platform/broadcom/platform-modules-cel.mk index ab6b0b6209d1..5fd1b3ddbc89 100644 --- a/platform/broadcom/platform-modules-cel.mk +++ b/platform/broadcom/platform-modules-cel.mk @@ -3,7 +3,7 @@ CEL_DX010_PLATFORM_MODULE_VERSION = 1.0 CEL_HALIBURTON_PLATFORM_MODULE_VERSION = 1.0 CEL_MYSTONE_PLATFORM_MODULE_VERSION = 1.0 -CEL_SILVERSTONE_PLATFORM_MODULE_VERSION = 0.9 +CEL_SILVERSTONE_PLATFORM_MODULE_VERSION = 1.0 export CEL_DX010_PLATFORM_MODULE_VERSION export CEL_HALIBURTON_PLATFORM_MODULE_VERSION