Write Enable instruction execution

[escherstair]

From M95M01 datasheet, in paragraph 6.4 I read

The Write Status Register (WRSR) instruction is used to write new values to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.

and in parapgraph 6.1

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected by Chip Select (S) being driven
high.

And so I assume that to complete a Write Enable instruction, the Chip Select (S) must be driven high.

In file eeprma1_m95.c I see two different approaches:

X-CUBE-EEPRMA1/Drivers/BSP/EEPRMA1/eeprma1_m95.c

Line 508 in 1ae7d7c

if ( EEPRMA1_M95_WriteCmd( EEPROMEX_WREN, DevAddr ) != BSP_ERROR_NONE )

calls EPRMA1_M95_WriteCmd() taht internally sets Chip Select low and then high.

On the other side, the following call

X-CUBE-EEPRMA1/Drivers/BSP/EEPRMA1/eeprma1_m95.c

Line 525 in 1ae7d7c

if ( EEPRMA1_M95_IOWrite( EEPROMEX_WREN ) != BSP_ERROR_NONE )

doesn't handle Chip Select, which is driven low by the previous function

X-CUBE-EEPRMA1/Drivers/BSP/EEPRMA1/eeprma1_m95.c

Line 524 in 1ae7d7c

EEPROMEX_CTRL_LOW( Devaddr & EEPROMEX_SPI_SLAVESEL );

but it's not driven high before the following call to EEPRMA1_M95_IOWrite( EEPROMEX_WRSR )

X-CUBE-EEPRMA1/Drivers/BSP/EEPRMA1/eeprma1_m95.c

Line 527 in 1ae7d7c

if (EEPRMA1_M95_IOWrite( EEPROMEX_WRSR ) != BSP_ERROR_NONE )

Can someone from ST verify this difference, please?
Which is the right way to send a Write Enable?