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wm8994_reg.h
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wm8994_reg.h
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/**
******************************************************************************
* @file wm8994_reg.h
* @author MCD Application Team
* @brief Header of wm8994_reg.c
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef WM8994_REG_H
#define WM8994_REG_H
#include <cmsis_compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
/** @addtogroup BSP
* @{
*/
/** @addtogroup Component
* @{
*/
/** @addtogroup WM8994
* @{
*/
/** @defgroup WM8994_Exported_Constants WM8994 Exported Constants
* @{
*/
/******************************************************************************/
/****************************** REGISTER MAPPING ******************************/
/******************************************************************************/
/* SW Reset */
#define WM8994_SW_RESET (uint16_t)0x0000
/* Power Management */
#define WM8994_PWR_MANAGEMENT_1 (uint16_t)0x0001
#define WM8994_PWR_MANAGEMENT_2 (uint16_t)0x0002
#define WM8994_PWR_MANAGEMENT_3 (uint16_t)0x0003
#define WM8994_PWR_MANAGEMENT_4 (uint16_t)0x0004
#define WM8994_PWR_MANAGEMENT_5 (uint16_t)0x0005
#define WM8994_PWR_MANAGEMENT_6 (uint16_t)0x0006
/* Input mixer */
#define WM8994_INPUT_MIXER_1 (uint16_t)0x0015
/* Input volume */
#define WM8994_LEFT_LINE_IN12_VOL (uint16_t)0x0018
#define WM8994_LEFT_LINE_IN34_VOL (uint16_t)0x0019
#define WM8994_RIGHT_LINE_IN12_VOL (uint16_t)0x001A
#define WM8994_RIGHT_LINE_IN34_VOL (uint16_t)0x001B
/* L/R Output volumes */
#define WM8994_LEFT_OUTPUT_VOL (uint16_t)0x001C
#define WM8994_RIGHT_OUTPUT_VOL (uint16_t)0x001D
#define WM8994_LINE_OUTPUT_VOL (uint16_t)0x001E
#define WM8994_OUTPUT2_VOL (uint16_t)0x001F
/* L/R OPGA volumes */
#define WM8994_LEFT_OPGA_VOL (uint16_t)0x0020
#define WM8994_RIGHT_OPGA_VOL (uint16_t)0x0021
/* SPKMIXL/R Attenuation */
#define WM8994_SPKMIXL_ATT (uint16_t)0x0022
#define WM8994_SPKMIXR_ATT (uint16_t)0x0023
#define WM8994_OUTPUT_MIXER (uint16_t)0x0024
#define WM8994_CLASS_D (uint16_t)0x0025
/* L/R Speakers volumes */
#define WM8994_SPK_LEFT_VOL (uint16_t)0x0026
#define WM8994_SPK_RIGHT_VOL (uint16_t)0x0027
/* Input mixer */
#define WM8994_INPUT_MIXER_2 (uint16_t)0x0028
#define WM8994_INPUT_MIXER_3 (uint16_t)0x0029
#define WM8994_INPUT_MIXER_4 (uint16_t)0x002A
#define WM8994_INPUT_MIXER_5 (uint16_t)0x002B
#define WM8994_INPUT_MIXER_6 (uint16_t)0x002C
/* Output mixer */
#define WM8994_OUTPUT_MIXER_1 (uint16_t)0x002D
#define WM8994_OUTPUT_MIXER_2 (uint16_t)0x002E
#define WM8994_OUTPUT_MIXER_3 (uint16_t)0x002F
#define WM8994_OUTPUT_MIXER_4 (uint16_t)0x0030
#define WM8994_OUTPUT_MIXER_5 (uint16_t)0x0031
#define WM8994_OUTPUT_MIXER_6 (uint16_t)0x0032
#define WM8994_OUTPUT2_MIXER (uint16_t)0x0033
#define WM8994_LINE_MIXER_1 (uint16_t)0x0034
#define WM8994_LINE_MIXER_2 (uint16_t)0x0035
#define WM8994_SPEAKER_MIXER (uint16_t)0x0036
#define WM8994_ADD_CONTROL (uint16_t)0x0037
/* Antipop */
#define WM8994_ANTIPOP1 (uint16_t)0x0038
#define WM8994_ANTIPOP2 (uint16_t)0x0039
#define WM8994_MICBIAS (uint16_t)0x003A
#define WM8994_LDO1 (uint16_t)0x003B
#define WM8994_LDO2 (uint16_t)0x003C
/* Charge pump */
#define WM8994_CHARGE_PUMP1 (uint16_t)0x004C
#define WM8994_CHARGE_PUMP2 (uint16_t)0x004D
#define WM8994_CLASS_W (uint16_t)0x0051
#define WM8994_DC_SERVO1 (uint16_t)0x0054
#define WM8994_DC_SERVO2 (uint16_t)0x0055
#define WM8994_DC_SERVO_READBACK (uint16_t)0x0058
#define WM8994_DC_SERVO_WRITEVAL (uint16_t)0x0059
/* Analog HP */
#define WM8994_ANALOG_HP (uint16_t)0x0060
#define WM8994_CHIP_REVISION (uint16_t)0x0100
#define WM8994_CONTROL_INTERFACE (uint16_t)0x0101
#define WM8994_WRITE_SEQ_CTRL1 (uint16_t)0x0110
#define WM8994_WRITE_SEQ_CTRL2 (uint16_t)0x0111
/* WM8994 clocking */
#define WM8994_AIF1_CLOCKING1 (uint16_t)0x0200
#define WM8994_AIF1_CLOCKING2 (uint16_t)0x0201
#define WM8994_AIF2_CLOCKING1 (uint16_t)0x0204
#define WM8994_AIF2_CLOCKING2 (uint16_t)0x0205
#define WM8994_CLOCKING1 (uint16_t)0x0208
#define WM8994_CLOCKING2 (uint16_t)0x0209
#define WM8994_AIF1_RATE (uint16_t)0x0210
#define WM8994_AIF2_RATE (uint16_t)0x0211
#define WM8994_RATE_STATUS (uint16_t)0x0212
/* FLL1 Control */
#define WM8994_FLL1_CONTROL1 (uint16_t)0x0220
#define WM8994_FLL1_CONTROL2 (uint16_t)0x0221
#define WM8994_FLL1_CONTROL3 (uint16_t)0x0222
#define WM8994_FLL1_CONTROL4 (uint16_t)0x0223
#define WM8994_FLL1_CONTROL5 (uint16_t)0x0224
/* FLL2 Control */
#define WM8994_FLL2_CONTROL1 (uint16_t)0x0240
#define WM8994_FLL2_CONTROL2 (uint16_t)0x0241
#define WM8994_FLL2_CONTROL3 (uint16_t)0x0242
#define WM8994_FLL2_CONTROL4 (uint16_t)0x0243
#define WM8994_FLL2_CONTROL5 (uint16_t)0x0244
/* AIF1 control */
#define WM8994_AIF1_CONTROL1 (uint16_t)0x0300
#define WM8994_AIF1_CONTROL2 (uint16_t)0x0301
#define WM8994_AIF1_MASTER_SLAVE (uint16_t)0x0302
#define WM8994_AIF1_BCLK (uint16_t)0x0303
#define WM8994_AIF1_ADC_LRCLK (uint16_t)0x0304
#define WM8994_AIF1_DAC_LRCLK (uint16_t)0x0305
#define WM8994_AIF1_DAC_DELTA (uint16_t)0x0306
#define WM8994_AIF1_ADC_DELTA (uint16_t)0x0307
/* AIF2 control */
#define WM8994_AIF2_CONTROL1 (uint16_t)0x0310
#define WM8994_AIF2_CONTROL2 (uint16_t)0x0311
#define WM8994_AIF2_MASTER_SLAVE (uint16_t)0x0312
#define WM8994_AIF2_BCLK (uint16_t)0x0313
#define WM8994_AIF2_ADC_LRCLK (uint16_t)0x0314
#define WM8994_AIF2_DAC_LRCLK (uint16_t)0x0315
#define WM8994_AIF2_DAC_DELTA (uint16_t)0x0316
#define WM8994_AIF2_ADC_DELTA (uint16_t)0x0317
/* AIF1 ADC/DAC LR volumes */
#define WM8994_AIF1_ADC1_LEFT_VOL (uint16_t)0x0400
#define WM8994_AIF1_ADC1_RIGHT_VOL (uint16_t)0x0401
#define WM8994_AIF1_DAC1_LEFT_VOL (uint16_t)0x0402
#define WM8994_AIF1_DAC1_RIGHT_VOL (uint16_t)0x0403
#define WM8994_AIF1_ADC2_LEFT_VOL (uint16_t)0x0404
#define WM8994_AIF1_ADC2_RIGHT_VOL (uint16_t)0x0405
#define WM8994_AIF1_DAC2_LEFT_VOL (uint16_t)0x0406
#define WM8994_AIF1_DAC2_RIGHT_VOL (uint16_t)0x0407
/* AIF1 ADC/DAC filters */
#define WM8994_AIF1_ADC1_FILTERS (uint16_t)0x0410
#define WM8994_AIF1_ADC2_FILTERS (uint16_t)0x0411
#define WM8994_AIF1_DAC1_FILTER1 (uint16_t)0x0420
#define WM8994_AIF1_DAC1_FILTER2 (uint16_t)0x0421
#define WM8994_AIF1_DAC2_FILTER1 (uint16_t)0x0422
#define WM8994_AIF1_DAC2_FILTER2 (uint16_t)0x0423
/* AIF1 DRC1 registers */
#define WM8994_AIF1_DRC1 (uint16_t)0x0440
#define WM8994_AIF1_DRC1_1 (uint16_t)0x0441
#define WM8994_AIF1_DRC1_2 (uint16_t)0x0442
#define WM8994_AIF1_DRC1_3 (uint16_t)0x0443
#define WM8994_AIF1_DRC1_4 (uint16_t)0x0444
/* AIF1 DRC2 registers */
#define WM8994_AIF1_DRC2 (uint16_t)0x0450
#define WM8994_AIF1_DRC2_1 (uint16_t)0x0451
#define WM8994_AIF1_DRC2_2 (uint16_t)0x0452
#define WM8994_AIF1_DRC2_3 (uint16_t)0x0453
#define WM8994_AIF1_DRC2_4 (uint16_t)0x0454
/* AIF1 DAC1 EQ Gains Bands */
#define WM8994_AIF1_DAC1_EQG_1 (uint16_t)0x0480
#define WM8994_AIF1_DAC1_EQG_2 (uint16_t)0x0481
#define WM8994_AIF1_DAC1_EQG_1A (uint16_t)0x0482
#define WM8994_AIF1_DAC1_EQG_1B (uint16_t)0x0483
#define WM8994_AIF1_DAC1_EQG_1PG (uint16_t)0x0484
#define WM8994_AIF1_DAC1_EQG_2A (uint16_t)0x0485
#define WM8994_AIF1_DAC1_EQG_2B (uint16_t)0x0486
#define WM8994_AIF1_DAC1_EQG_2C (uint16_t)0x0487
#define WM8994_AIF1_DAC1_EQG_2PG (uint16_t)0x0488
#define WM8994_AIF1_DAC1_EQG_3A (uint16_t)0x0489
#define WM8994_AIF1_DAC1_EQG_3B (uint16_t)0x048A
#define WM8994_AIF1_DAC1_EQG_3C (uint16_t)0x048B
#define WM8994_AIF1_DAC1_EQG_3PG (uint16_t)0x048C
#define WM8994_AIF1_DAC1_EQG_4A (uint16_t)0x048D
#define WM8994_AIF1_DAC1_EQG_4B (uint16_t)0x048E
#define WM8994_AIF1_DAC1_EQG_4C (uint16_t)0x048F
#define WM8994_AIF1_DAC1_EQG_4PG (uint16_t)0x0490
#define WM8994_AIF1_DAC1_EQG_5A (uint16_t)0x0491
#define WM8994_AIF1_DAC1_EQG_5B (uint16_t)0x0492
#define WM8994_AIF1_DAC1_EQG_5PG (uint16_t)0x0493
/* AIF1 DAC2 EQ Gains/bands */
#define WM8994_AIF1_DAC2_EQG_1 (uint16_t)0x04A0
#define WM8994_AIF1_DAC2_EQG_2 (uint16_t)0x04A1
#define WM8994_AIF1_DAC2_EQG_1A (uint16_t)0x04A2
#define WM8994_AIF1_DAC2_EQG_1B (uint16_t)0x04A3
#define WM8994_AIF1_DAC2_EQG_1PG (uint16_t)0x04A4
#define WM8994_AIF1_DAC2_EQG_2A (uint16_t)0x04A5
#define WM8994_AIF1_DAC2_EQG_2B (uint16_t)0x04A6
#define WM8994_AIF1_DAC2_EQG_2C (uint16_t)0x04A7
#define WM8994_AIF1_DAC2_EQG_2PG (uint16_t)0x04A8
#define WM8994_AIF1_DAC2_EQG_3A (uint16_t)0x04A9
#define WM8994_AIF1_DAC2_EQG_3B (uint16_t)0x04AA
#define WM8994_AIF1_DAC2_EQG_3C (uint16_t)0x04AB
#define WM8994_AIF1_DAC2_EQG_3PG (uint16_t)0x04AC
#define WM8994_AIF1_DAC2_EQG_4A (uint16_t)0x04AD
#define WM8994_AIF1_DAC2_EQG_4B (uint16_t)0x04AE
#define WM8994_AIF1_DAC2_EQG_4C (uint16_t)0x04AF
#define WM8994_AIF1_DAC2_EQG_4PG (uint16_t)0x04B0
#define WM8994_AIF1_DAC2_EQG_5A (uint16_t)0x04B1
#define WM8994_AIF1_DAC2_EQG_5B (uint16_t)0x04B2
#define WM8994_AIF1_DAC2_EQG_5PG (uint16_t)0x04B3
/* AIF2 ADC/DAC LR volumes */
#define WM8994_AIF2_ADC_LEFT_VOL (uint16_t)0x0500
#define WM8994_AIF2_ADC_RIGHT_VOL (uint16_t)0x0501
#define WM8994_AIF2_DAC_LEFT_VOL (uint16_t)0x0502
#define WM8994_AIF2_DAC_RIGHT_VOL (uint16_t)0x0503
/* AIF2 ADC/DAC filters */
#define WM8994_AIF2_ADC_FILTERS (uint16_t)0x0510
#define WM8994_AIF2_DAC_FILTER_1 (uint16_t)0x0520
#define WM8994_AIF2_DAC_FILTER_2 (uint16_t)0x0521
/* AIF2 DRC registers */
#define WM8994_AIF2_DRC_1 (uint16_t)0x0540
#define WM8994_AIF2_DRC_2 (uint16_t)0x0541
#define WM8994_AIF2_DRC_3 (uint16_t)0x0542
#define WM8994_AIF2_DRC_4 (uint16_t)0x0543
#define WM8994_AIF2_DRC_5 (uint16_t)0x0544
/* AIF2 EQ Gains/bands */
#define WM8994_AIF2_EQG_1 (uint16_t)0x0580
#define WM8994_AIF2_EQG_2 (uint16_t)0x0581
#define WM8994_AIF2_EQG_1A (uint16_t)0x0582
#define WM8994_AIF2_EQG_1B (uint16_t)0x0583
#define WM8994_AIF2_EQG_1PG (uint16_t)0x0584
#define WM8994_AIF2_EQG_2A (uint16_t)0x0585
#define WM8994_AIF2_EQG_2B (uint16_t)0x0586
#define WM8994_AIF2_EQG_2C (uint16_t)0x0587
#define WM8994_AIF2_EQG_2PG (uint16_t)0x0588
#define WM8994_AIF2_EQG_3A (uint16_t)0x0589
#define WM8994_AIF2_EQG_3B (uint16_t)0x058A
#define WM8994_AIF2_EQG_3C (uint16_t)0x058B
#define WM8994_AIF2_EQG_3PG (uint16_t)0x058C
#define WM8994_AIF2_EQG_4A (uint16_t)0x058D
#define WM8994_AIF2_EQG_4B (uint16_t)0x058E
#define WM8994_AIF2_EQG_4C (uint16_t)0x058F
#define WM8994_AIF2_EQG_4PG (uint16_t)0x0590
#define WM8994_AIF2_EQG_5A (uint16_t)0x0591
#define WM8994_AIF2_EQG_5B (uint16_t)0x0592
#define WM8994_AIF2_EQG_5PG (uint16_t)0x0593
/* AIF1 DAC1 Mixer volume */
#define WM8994_DAC1_MIXER_VOL (uint16_t)0x0600
/* AIF1 DAC1 Left Mixer Routing */
#define WM8994_AIF1_DAC1_LMR (uint16_t)0x0601
/* AIF1 DAC1 Righ Mixer Routing */
#define WM8994_AIF1_DAC1_RMR (uint16_t)0x0602
/* AIF1 DAC2 Mixer volume */
#define WM8994_DAC2_MIXER_VOL (uint16_t)0x0603
/* AIF1 DAC2 Left Mixer Routing */
#define WM8994_AIF1_DAC2_LMR (uint16_t)0x0604
/* AIF1 DAC2 Righ Mixer Routing */
#define WM8994_AIF1_DAC2_RMR (uint16_t)0x0605
/* AIF1 ADC1 Left Mixer Routing */
#define WM8994_AIF1_ADC1_LMR (uint16_t)0x0606
/* AIF1 ADC1 Righ Mixer Routing */
#define WM8994_AIF1_ADC1_RMR (uint16_t)0x0607
/* AIF1 ADC2 Left Mixer Routing */
#define WM8994_AIF1_ADC2_LMR (uint16_t)0x0608
/* AIF1 ADC2 Righ Mixer Routing */
#define WM8994_AIF1_ADC2_RMR (uint16_t)0x0609
/* Volume control */
#define WM8994_DAC1_LEFT_VOL (uint16_t)0x0610
#define WM8994_DAC1_RIGHT_VOL (uint16_t)0x0611
#define WM8994_DAC2_LEFT_VOL (uint16_t)0x0612
#define WM8994_DAC2_RIGHT_VOL (uint16_t)0x0613
#define WM8994_DAC_SOFTMUTE (uint16_t)0x0614
#define WM8994_OVERSAMPLING (uint16_t)0x0620
#define WM8994_SIDETONE (uint16_t)0x0621
/* GPIO */
#define WM8994_GPIO1 (uint16_t)0x0700
#define WM8994_GPIO2 (uint16_t)0x0701
#define WM8994_GPIO3 (uint16_t)0x0702
#define WM8994_GPIO4 (uint16_t)0x0703
#define WM8994_GPIO5 (uint16_t)0x0704
#define WM8994_GPIO6 (uint16_t)0x0705
#define WM8994_GPIO7 (uint16_t)0x0706
#define WM8994_GPIO8 (uint16_t)0x0707
#define WM8994_GPIO9 (uint16_t)0x0708
#define WM8994_GPIO10 (uint16_t)0x0709
#define WM8994_GPIO11 (uint16_t)0x070A
/* Pull Contol */
#define WM8994_PULL_CONTROL_1 (uint16_t)0x0720
#define WM8994_PULL_CONTROL_2 (uint16_t)0x0721
/* WM8994 Inturrupts */
#define WM8994_INT_STATUS_1 (uint16_t)0x0730
#define WM8994_INT_STATUS_2 (uint16_t)0x0731
#define WM8994_INT_RAW_STATUS_2 (uint16_t)0x0732
#define WM8994_INT_STATUS1_MASK (uint16_t)0x0738
#define WM8994_INT_STATUS2_MASK (uint16_t)0x0739
#define WM8994_INT_CONTROL (uint16_t)0x0740
#define WM8994_IRQ_DEBOUNCE (uint16_t)0x0748
/* Write Sequencer registers from 0 to 511 */
#define WM8994_WRITE_SEQUENCER0 (uint16_t)0x3000
#define WM8994_WRITE_SEQUENCER1 (uint16_t)0x3001
#define WM8994_WRITE_SEQUENCER2 (uint16_t)0x3002
#define WM8994_WRITE_SEQUENCER3 (uint16_t)0x3003
#define WM8994_WRITE_SEQUENCER4 (uint16_t)0x3508
#define WM8994_WRITE_SEQUENCER5 (uint16_t)0x3509
#define WM8994_WRITE_SEQUENCER6 (uint16_t)0x3510
#define WM8994_WRITE_SEQUENCER7 (uint16_t)0x3511
/**
* @}
*/
/************** Generic Function *******************/
typedef int32_t (*WM8994_Write_Func)(void *, uint16_t, uint8_t*, uint16_t);
typedef int32_t (*WM8994_Read_Func) (void *, uint16_t, uint8_t*, uint16_t);
typedef struct
{
WM8994_Write_Func WriteReg;
WM8994_Read_Func ReadReg;
void *handle;
} wm8994_ctx_t;
/*******************************************************************************
* Register : Generic - All
* Address : Generic - All
* Bit Group Name: None
* Permission : W
*******************************************************************************/
int32_t wm8994_write_reg(wm8994_ctx_t *ctx, uint16_t reg, uint16_t *data, uint16_t length);
int32_t wm8994_read_reg(wm8994_ctx_t *ctx, uint16_t reg, uint16_t* data, uint16_t length);
int32_t wm8994_register_set(wm8994_ctx_t *ctx, uint16_t reg, uint16_t value);
/**************** Base Function *******************/
/*******************************************************************************
* Register : WM8994_SW_RESET
* Address : 0X00
* Bit Group Name: SW_RESET[15:0]
* Permission : RW
*******************************************************************************/
#define WM8994_SW_RESET_MASK (uint16_t)0xFFFF
#define WM8994_SW_RESET_POSITION 0
int32_t wm8994_sw_reset_w(wm8994_ctx_t *ctx, uint16_t value);
int32_t wm8994_sw_reset_r(wm8994_ctx_t *ctx, uint16_t *value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_1
* Address : 0X01
* Bit Group Name: BIAS_EN
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_1_BIAS_EN_MASK (uint16_t)0x0001U
#define WM8994_PWR_MGMT_1_BIAS_EN_POSITION 0
int32_t wm8994_pwr_mgmt_1_bias_en(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_1
* Address : 0X01
* Bit Group Name: VMID_SEL [1:0]
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_1_VMID_SEL_MASK (uint16_t)0x0006U
#define WM8994_PWR_MGMT_1_VMID_SEL_POSITION 1
int32_t wm8994_pwr_mgmt_1_vmid_sel(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_1
* Address : 0X01
* Bit Group Name: MICB1_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_1_MICB1_ENA_MASK (uint16_t)0x0010U
#define WM8994_PWR_MGMT_1_MICB1_ENA_POSITION 4
int32_t wm8994_pwr_mgmt_1_micb1_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_1
* Address : 0X01
* Bit Group Name: MICB2_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_1_MICB2_ENA_MASK (uint16_t)0x0020U
#define WM8994_PWR_MGMT_1_MICB2_ENA_POSITION 5
int32_t wm8994_pwr_mgmt_1_micb2_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_1
* Address : 0X01
* Bit Group Name: HPOUT1R_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_1_HPOUT1R_ENA_MASK (uint16_t)0x0100U
#define WM8994_PWR_MGMT_1_HPOUT1R_ENA_POSITION 8
int32_t wm8994_pwr_mgmt_1_hpout1r_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_1
* Address : 0X01
* Bit Group Name: HPOUT1L_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_1_HPOUT1L_ENA_MASK (uint16_t)0x0200U
#define WM8994_PWR_MGMT_1_HPOUT1L_ENA_POSITION 9
int32_t wm8994_pwr_mgmt_1_hpout1l_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_1
* Address : 0X01
* Bit Group Name: HPOUT2_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_1_HPOUT2_ENA_MASK (uint16_t)0x0800U
#define WM8994_PWR_MGMT_1_HPOUT2_ENA_POSITION 11
int32_t wm8994_pwr_mgmt_1_hpout2_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_1
* Address : 0X01
* Bit Group Name: SPKOUTL_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_1_SPKOUTL_ENA_MASK (uint16_t)0x1000U
#define WM8994_PWR_MGMT_1_SPKOUTL_ENA_POSITION 12
int32_t wm8994_pwr_mgmt_1_spkoutl_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_1
* Address : 0X01
* Bit Group Name: SPKOUTR_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_1_SPKOUTR_ENA_MASK (uint16_t)0x2000U
#define WM8994_PWR_MGMT_1_SPKOUTR_ENA_POSITION 13
int32_t wm8994_pwr_mgmt_1_spkoutr_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_2
* Address : 0X02
* Bit Group Name: IN1R_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_2_IN1R_ENA_MASK (uint16_t)0x0010U
#define WM8994_PWR_MGMT_2_IN1R_ENA_POSITION 4
int32_t wm8994_pwr_mgmt_2_in1r_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_2
* Address : 0X02
* Bit Group Name: IN2R_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_2_IN2R_ENA_MASK (uint16_t)0x0020U
#define WM8994_PWR_MGMT_2_IN2R_ENA_POSITION 5
int32_t wm8994_pwr_mgmt_2_in2r_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_2
* Address : 0X02
* Bit Group Name: IN1L_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_2_IN1L_ENA_MASK (uint16_t)0x0040U
#define WM8994_PWR_MGMT_2_IN1L_ENA_POSITION 6
int32_t wm8994_pwr_mgmt_2_in1l_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_2
* Address : 0X02
* Bit Group Name: IN2L_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_2_IN2L_ENA_MASK (uint16_t)0x0080U
#define WM8994_PWR_MGMT_2_IN2L_ENA_POSITION 7
int32_t wm8994_pwr_mgmt_2_in2l_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_2
* Address : 0X02
* Bit Group Name: MIXINR_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_2_MIXINR_ENA_MASK (uint16_t)0x0100U
#define WM8994_PWR_MGMT_2_MIXINR_ENA_POSITION 8
int32_t wm8994_pwr_mgmt_2_mixinr_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_2
* Address : 0X02
* Bit Group Name: MIXINL_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_2_MIXINL_ENA_MASK (uint16_t)0x0200U
#define WM8994_PWR_MGMT_2_MIXINL_ENA_POSITION 9
int32_t wm8994_pwr_mgmt_2_mixinl_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_2
* Address : 0X02
* Bit Group Name: OPCLK_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_2_OPCLK_ENA_MASK (uint16_t)0x0800U
#define WM8994_PWR_MGMT_2_OPCLK_ENA_POSITION 11
int32_t wm8994_pwr_mgmt_2_opclk_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_2
* Address : 0X02
* Bit Group Name: TSHUT_OPDIS
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_2_TSHUT_OPDIS_MASK (uint16_t)0x2000U
#define WM8994_PWR_MGMT_2_TSHUT_OPDIS_POSITION 13
int32_t wm8994_pwr_mgmt_2_tshut_opdis(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_2
* Address : 0X02
* Bit Group Name: TSHUT_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_2_TSHUT_ENA_MASK (uint16_t)0x4000U
#define WM8994_PWR_MGMT_2_TSHUT_ENA_POSITION 14
int32_t wm8994_pwr_mgmt_2_tshut_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_3
* Address : 0X03
* Bit Group Name: MIXOUTR_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_3_MIXOUTR_ENA_MASK (uint16_t)0x0010U
#define WM8994_PWR_MGMT_3_MIXOUTR_ENA_POSITION 4
int32_t wm8994_pwr_mgmt_3_mixoutr_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_3
* Address : 0X03
* Bit Group Name: MIXOUTL_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_3_MIXOUTL_ENA_MASK (uint16_t)0x0020U
#define WM8994_PWR_MGMT_3_MIXOUTL_ENA_POSITION 5
int32_t wm8994_pwr_mgmt_3_mixoutl_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_3
* Address : 0X03
* Bit Group Name: MIXOUTRVOL_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_3_MIXOUTRVOL_ENA_MASK (uint16_t)0x0040U
#define WM8994_PWR_MGMT_3_MIXOUTRVOL_ENA_POSITION 6
int32_t wm8994_pwr_mgmt_3_mixoutrvol_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_3
* Address : 0X03
* Bit Group Name: MIXOUTLVOL_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_3_MIXOUTLVOL_ENA_MASK (uint16_t)0x0080U
#define WM8994_PWR_MGMT_3_MIXOUTLVOL_ENA_POSITION 7
int32_t wm8994_pwr_mgmt_3_mixoutlvol_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_3
* Address : 0X03
* Bit Group Name: SPKLVOL_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_3_SPKLVOL_ENA_MASK (uint16_t)0x0100U
#define WM8994_PWR_MGMT_3_SPKLVOL_ENA_POSITION 8
int32_t wm8994_pwr_mgmt_3_spklvol_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_3
* Address : 0X03
* Bit Group Name: SPKRVOL_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_3_SPKRVOL_ENA_MASK (uint16_t)0x0200U
#define WM8994_PWR_MGMT_3_SPKRVOL_ENA_POSITION 9
int32_t wm8994_pwr_mgmt_3_spkrvol_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_3
* Address : 0X03
* Bit Group Name: LINEOUT2P_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_3_LINEOUT2P_ENA_MASK (uint16_t)0x0400U
#define WM8994_PWR_MGMT_3_LINEOUT2P_ENA_POSITION 10
int32_t wm8994_pwr_mgmt_3_lineout2p_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_3
* Address : 0X03
* Bit Group Name: LINEOUT2N_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_3_LINEOUT2N_ENA_MASK (uint16_t)0x0800U
#define WM8994_PWR_MGMT_3_LINEOUT2N_ENA_POSITION 11
int32_t wm8994_pwr_mgmt_3_lineout2n_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_3
* Address : 0X03
* Bit Group Name: LINEOUT1P_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_3_LINEOUT1P_ENA_MASK (uint16_t)0x1000U
#define WM8994_PWR_MGMT_3_LINEOUT1P_ENA_POSITION 12
int32_t wm8994_pwr_mgmt_3_lineout1p_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_3
* Address : 0X03
* Bit Group Name: LINEOUT1N_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_3_LINEOUT1N_ENA_MASK (uint16_t)0x2000U
#define WM8994_PWR_MGMT_3_LINEOUT1N_ENA_POSITION 13
int32_t wm8994_pwr_mgmt_3_lineout1n_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_4
* Address : 0X04
* Bit Group Name: ADCR_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_4_ADCR_ENA_MASK (uint16_t)0x0001U
#define WM8994_PWR_MGMT_4_ADCR_ENA_POSITION 0
int32_t wm8994_pwr_mgmt_4_adcr_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_4
* Address : 0X04
* Bit Group Name: ADCL_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_4_ADCL_ENA_MASK (uint16_t)0x0002U
#define WM8994_PWR_MGMT_4_ADCL_ENA_POSITION 1
int32_t wm8994_pwr_mgmt_4_adcl_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_4
* Address : 0X04
* Bit Group Name: DMIC1R_ENA
* Permission : RWZ
*******************************************************************************/
#define WM8994_PWR_MGMT_4_DMIC1R_ENA_MASK (uint16_t)0x0004U
#define WM8994_PWR_MGMT_4_DMIC1R_ENA_POSITION 2
int32_t wm8994_pwr_mgmt_4_dmic1r_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_4
* Address : 0X04
* Bit Group Name: DMIC1L_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_4_DMIC1L_ENA_MASK (uint16_t)0x0008U
#define WM8994_PWR_MGMT_4_DMIC1L_ENA_POSITION 3
int32_t wm8994_pwr_mgmt_4_dmic1l_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_4
* Address : 0X04
* Bit Group Name: DMIC2R_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_4_DMIC2R_ENA_MASK (uint16_t)0x0010U
#define WM8994_PWR_MGMT_4_DMIC2R_ENA_POSITION 4
int32_t wm8994_pwr_mgmt_4_dmic2r_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_4
* Address : 0X04
* Bit Group Name: DMIC2L_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_4_DMIC2L_ENA_MASK (uint16_t)0x0020U
#define WM8994_PWR_MGMT_4_DMIC2L_ENA_POSITION 5
int32_t wm8994_pwr_mgmt_4_dmic2l_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_4
* Address : 0X04
* Bit Group Name: AIF1ADC1R_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_4_AIF1ADC1R_ENA_MASK (uint16_t)0x0100U
#define WM8994_PWR_MGMT_4_AIF1ADC1R_ENA_POSITION 8
int32_t wm8994_pwr_mgmt_4_aif1adc1r_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_4
* Address : 0X04
* Bit Group Name: AIF1ADC1L_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_4_AIF1ADC1L_ENA_MASK (uint16_t)0x0200U
#define WM8994_PWR_MGMT_4_AIF1ADC1L_ENA_POSITION 9
int32_t wm8994_pwr_mgmt_4_aif1adc1l_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_4
* Address : 0X04
* Bit Group Name: AIF1ADC2R_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_4_AIF1ADC2R_ENA_MASK (uint16_t)0x0400U
#define WM8994_PWR_MGMT_4_AIF1ADC2R_ENA_POSITION 10
int32_t wm8994_pwr_mgmt_4_aif1adc2r_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_4
* Address : 0X04
* Bit Group Name: AIF1ADC2L_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_4_AIF1ADC2L_ENA_MASK (uint16_t)0x0800U
#define WM8994_PWR_MGMT_4_AIF1ADC2L_ENA_POSITION 11
int32_t wm8994_pwr_mgmt_4_aif1adc2l_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_4
* Address : 0X04
* Bit Group Name: AIF2ADCR_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_4_AIF2ADCR_ENA_MASK (uint16_t)0x1000U
#define WM8994_PWR_MGMT_4_AIF2ADCR_ENA_POSITION 12
int32_t wm8994_pwr_mgmt_4_aif2adcr_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_4
* Address : 0X04
* Bit Group Name: AIF2ADCL_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_4_AIF2ADCL_ENA_MASK (uint16_t)0x2000U
#define WM8994_PWR_MGMT_4_AIF2ADCL_ENA_POSITION 13
int32_t wm8994_pwr_mgmt_4_aif2adcl_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_5
* Address : 0X05
* Bit Group Name: DAC1R_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_5_DAC1R_ENA_MASK (uint16_t)0x0001U
#define WM8994_PWR_MGMT_5_DAC1R_ENA_POSITION 0
int32_t wm8994_pwr_mgmt_5_dac1r_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_5
* Address : 0X05
* Bit Group Name: DAC1L_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_5_DAC1L_ENA_MASK (uint16_t)0x0002U
#define WM8994_PWR_MGMT_5_DAC1L_ENA_POSITION 1
int32_t wm8994_pwr_mgmt_5_dac1l_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_5
* Address : 0X05
* Bit Group Name: DAC2R_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_5_DAC2R_ENA_MASK (uint16_t)0x0004U
#define WM8994_PWR_MGMT_5_DAC2R_ENA_POSITION 2
int32_t wm8994_pwr_mgmt_5_dac2r_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_5
* Address : 0X05
* Bit Group Name: DAC2L_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_5_DAC2L_ENA_MASK (uint16_t)0x0008U
#define WM8994_PWR_MGMT_5_DAC2L_ENA_POSITION 3
int32_t wm8994_pwr_mgmt_5_dac2l_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_5
* Address : 0X05
* Bit Group Name: AIF1DAC1R_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_5_AIF1DAC1R_ENA_MASK (uint16_t)0x0100U
#define WM8994_PWR_MGMT_5_AIF1DAC1R_ENA_POSITION 8
int32_t wm8994_pwr_mgmt_5_aif1dac1r_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_5
* Address : 0X05
* Bit Group Name: AIF1DAC1L_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_5_AIF1DAC1L_ENA_MASK (uint16_t)0x0200U
#define WM8994_PWR_MGMT_5_AIF1DAC1L_ENA_POSITION 9
int32_t wm8994_pwr_mgmt_5_aif1dac1l_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_5
* Address : 0X05
* Bit Group Name: AIF1DAC2R_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_5_AIF1DAC2R_ENA_MASK (uint16_t)0x0400U
#define WM8994_PWR_MGMT_5_AIF1DAC2R_ENA_POSITION 10
int32_t wm8994_pwr_mgmt_5_aif1dac2r_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_5
* Address : 0X05
* Bit Group Name: AIF1DAC2L_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_5_AIF1DAC2L_ENA_MASK (uint16_t)0x0800U
#define WM8994_PWR_MGMT_5_AIF1DAC2L_ENA_POSITION 11
int32_t wm8994_pwr_mgmt_5_aif1dac2l_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_5
* Address : 0X05
* Bit Group Name: AIF2DACR_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_5_AIF2DACR_ENA_MASK (uint16_t)0x1000U
#define WM8994_PWR_MGMT_5_AIF2DACR_ENA_POSITION 12
int32_t wm8994_pwr_mgmt_5_aif2dacr_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_5
* Address : 0X05
* Bit Group Name: AIF2DACL_ENA
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_5_AIF2DACL_ENA_MASK (uint16_t)0x2000U
#define WM8994_PWR_MGMT_5_AIF2DACL_ENA_POSITION 13
int32_t wm8994_pwr_mgmt_5_aif2dacl_ena(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_6
* Address : 0X06
* Bit Group Name: AIF1_DACDAT_SRC
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_6_AIF1_DACDAT_SRC_MASK (uint16_t)0x0001U
#define WM8994_PWR_MGMT_6_AIF1_DACDAT_SRC_POSITION 0
int32_t wm8994_pwr_mgmt_6_aif1_dacdat_src(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_6
* Address : 0X06
* Bit Group Name: AIF2_DACDAT_SRC
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_6_AIF2_DACDAT_SRC_MASK (uint16_t)0x0002U
#define WM8994_PWR_MGMT_6_AIF2_DACDAT_SRC_POSITION 1
int32_t wm8994_pwr_mgmt_6_aif2_dacdat_src(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_6
* Address : 0X06
* Bit Group Name: AIF2_ADCDAT_SRC
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_6_AIF2_ADCDAT_SRC_MASK (uint16_t)0x0004U
#define WM8994_PWR_MGMT_6_AIF2_ADCDAT_SRC_POSITION 2
int32_t wm8994_pwr_mgmt_6_aif2_adcdat_src(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_6
* Address : 0X06
* Bit Group Name: AIF3_ADCDAT_SRC
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_6_AIF3_ADCDAT_SRC_MASK (uint16_t)0x0018U
#define WM8994_PWR_MGMT_6_AIF3_ADCDAT_SRC_POSITION 3
int32_t wm8994_pwr_mgmt_6_aif3_adcdat_src(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_PWR_MANAGEMENT_6
* Address : 0X06
* Bit Group Name: AIF3_TRI
* Permission : RW
*******************************************************************************/
#define WM8994_PWR_MGMT_6_AIF3_TRI_MASK (uint16_t)0x0020U
#define WM8994_PWR_MGMT_6_AIF3_TRI_POSITION 5
int32_t wm8994_pwr_mgmt_6_aif3_tri(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_INPUT_MIXER_1
* Address : 0X15
* Bit Group Name: INPUTS_CLAMP
* Permission : RW
*******************************************************************************/
#define WM8994_INMIXER1_INPUTS_CLAMP_MASK (uint16_t)0x0040U
#define WM8994_INMIXER1_INPUTS_CLAMP_POSITION 6
int32_t wm8994_inmixer1_inputs_clamp(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_INPUT_MIXER_1
* Address : 0X15
* Bit Group Name: IN1LP_MIXINL_BOOST
* Permission : RW
*******************************************************************************/
#define WM8994_INMIXER1_IN1LP_MIXINL_BOOST_MASK (uint16_t)0x0080U
#define WM8994_INMIXER1_IN1LP_MIXINL_BOOST_POSITION 7
int32_t wm8994_inmixer1_in1lp_mixinl_boost(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_INPUT_MIXER_1
* Address : 0X15
* Bit Group Name: IN1RP_MIXINR_BOOST
* Permission : RW
*******************************************************************************/
#define WM8994_INMIXER1_IN1RP_MIXINR_BOOST_MASK (uint16_t)0x0100U
#define WM8994_INMIXER1_IN1RP_MIXINR_BOOST_POSITION 8
int32_t wm8994_inmixer1_in1rp_mixinr_boost(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_LEFT_LINE_IN12_VOL
* Address : 0X18
* Bit Group Name: IN1L_VOL [4:0]
* Permission : RW
*******************************************************************************/
#define WM8994_LLI_IN1L_VOL_MASK (uint16_t)0x001F
#define WM8994_LLI_IN1L_VOL_POSITION 0
int32_t wm8994_lli_in1l_vol(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************
* Register : WM8994_LEFT_LINE_IN12_VOL
* Address : 0X18
* Bit Group Name: IN1L_ZC
* Permission : RW
*******************************************************************************/
#define WM8994_LLI_IN1L_ZC_MASK (uint16_t)0x0040U
#define WM8994_LLI_IN1L_ZC_POSITION 6
int32_t wm8994_lli_in1l_zc(wm8994_ctx_t *ctx, uint16_t value);
/*******************************************************************************