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cgain_core.mdl
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infoedit " System Generator"
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part "xc6vsx475t"
speed "-2"
package "ff1759"
synthesis_tool "XST"
clock_wrapper "Clock Enables"
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infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop."
rst off
infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs"
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latency "3"
dbl_ovrd off
reg_retiming off
xl_use_area off
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infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop."
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