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fir_core_config.m
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fir_core_config.m
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function fir_core_config(this_block)
% Revision History:
%
% 19-Dec-2011 (15:24 hours):
% Original code was machine generated by Xilinx's System Generator after parsing
% /home/rprimian/git/design_files/fir_core.vhd
%
%
this_block.setTopLevelLanguage('VHDL');
this_block.setEntityName('fir_core');
% System Generator has to assume that your entity has a combinational feed through;
% if it doesn't, then comment out the following line:
%this_block.tagAsCombinational;
this_block.addSimulinkInport('sync');
this_block.addSimulinkInport('i0');
this_block.addSimulinkInport('i1');
this_block.addSimulinkInport('i2');
this_block.addSimulinkInport('i3');
this_block.addSimulinkInport('i4');
this_block.addSimulinkInport('i5');
this_block.addSimulinkInport('i6');
this_block.addSimulinkInport('i7');
this_block.addSimulinkInport('i8');
this_block.addSimulinkInport('i9');
this_block.addSimulinkInport('i10');
this_block.addSimulinkInport('i11');
this_block.addSimulinkInport('i12');
this_block.addSimulinkInport('i13');
this_block.addSimulinkInport('i14');
this_block.addSimulinkInport('i15');
this_block.addSimulinkOutport('sync_out');
this_block.addSimulinkOutport('q0');
this_block.addSimulinkOutport('q1');
this_block.addSimulinkOutport('q2');
this_block.addSimulinkOutport('q3');
this_block.addSimulinkOutport('q4');
this_block.addSimulinkOutport('q5');
this_block.addSimulinkOutport('q6');
this_block.addSimulinkOutport('q7');
this_block.addSimulinkOutport('q8');
this_block.addSimulinkOutport('q9');
this_block.addSimulinkOutport('q10');
this_block.addSimulinkOutport('q11');
this_block.addSimulinkOutport('q12');
this_block.addSimulinkOutport('q13');
this_block.addSimulinkOutport('q14');
this_block.addSimulinkOutport('q15');
q0_port = this_block.port('q0');
q0_port.setType('Fix_18_17');
q1_port = this_block.port('q1');
q1_port.setType('Fix_18_17');
q10_port = this_block.port('q10');
q10_port.setType('Fix_18_17');
q11_port = this_block.port('q11');
q11_port.setType('Fix_18_17');
q12_port = this_block.port('q12');
q12_port.setType('Fix_18_17');
q13_port = this_block.port('q13');
q13_port.setType('Fix_18_17');
q14_port = this_block.port('q14');
q14_port.setType('Fix_18_17');
q15_port = this_block.port('q15');
q15_port.setType('Fix_18_17');
q2_port = this_block.port('q2');
q2_port.setType('Fix_18_17');
q3_port = this_block.port('q3');
q3_port.setType('Fix_18_17');
q4_port = this_block.port('q4');
q4_port.setType('Fix_18_17');
q5_port = this_block.port('q5');
q5_port.setType('Fix_18_17');
q6_port = this_block.port('q6');
q6_port.setType('Fix_18_17');
q7_port = this_block.port('q7');
q7_port.setType('Fix_18_17');
q8_port = this_block.port('q8');
q8_port.setType('Fix_18_17');
q9_port = this_block.port('q9');
q9_port.setType('Fix_18_17');
sync_out_port = this_block.port('sync_out');
sync_out_port.setType('Bool');
sync_out_port.useHDLVector(false);
% -----------------------------
if (this_block.inputTypesKnown)
% do input type checking, dynamic output type and generic setup in this code block.
if (this_block.port('i0').width ~= 8);
this_block.setError('Input data type for port "i0" must have width=8.');
end
if (this_block.port('i1').width ~= 8);
this_block.setError('Input data type for port "i1" must have width=8.');
end
if (this_block.port('i10').width ~= 8);
this_block.setError('Input data type for port "i10" must have width=8.');
end
if (this_block.port('i11').width ~= 8);
this_block.setError('Input data type for port "i11" must have width=8.');
end
if (this_block.port('i12').width ~= 8);
this_block.setError('Input data type for port "i12" must have width=8.');
end
if (this_block.port('i13').width ~= 8);
this_block.setError('Input data type for port "i13" must have width=8.');
end
if (this_block.port('i14').width ~= 8);
this_block.setError('Input data type for port "i14" must have width=8.');
end
if (this_block.port('i15').width ~= 8);
this_block.setError('Input data type for port "i15" must have width=8.');
end
if (this_block.port('i2').width ~= 8);
this_block.setError('Input data type for port "i2" must have width=8.');
end
if (this_block.port('i3').width ~= 8);
this_block.setError('Input data type for port "i3" must have width=8.');
end
if (this_block.port('i4').width ~= 8);
this_block.setError('Input data type for port "i4" must have width=8.');
end
if (this_block.port('i5').width ~= 8);
this_block.setError('Input data type for port "i5" must have width=8.');
end
if (this_block.port('i6').width ~= 8);
this_block.setError('Input data type for port "i6" must have width=8.');
end
if (this_block.port('i7').width ~= 8);
this_block.setError('Input data type for port "i7" must have width=8.');
end
if (this_block.port('i8').width ~= 8);
this_block.setError('Input data type for port "i8" must have width=8.');
end
if (this_block.port('i9').width ~= 8);
this_block.setError('Input data type for port "i9" must have width=8.');
end
if (this_block.port('sync').width ~= 1);
this_block.setError('Input data type for port "sync" must have width=1.');
end
this_block.port('sync').useHDLVector(false);
end % if(inputTypesKnown)
% -----------------------------
% -----------------------------
if (this_block.inputRatesKnown)
setup_as_single_rate(this_block,'clk_1','ce_1')
end % if(inputRatesKnown)
% -----------------------------
% (!) Set the inout port rate to be the same as the first input
% rate. Change the following code if this is untrue.
uniqueInputRates = unique(this_block.getInputRates);
% Add addtional source files as needed.
% |-------------
% | Add files in the order in which they should be compiled.
% | If two files "a.vhd" and "b.vhd" contain the entities
% | entity_a and entity_b, and entity_a contains a
% | component of type entity_b, the correct sequence of
% | addFile() calls would be:
% | this_block.addFile('b.vhd');
% | this_block.addFile('a.vhd');
% |-------------
% this_block.addFile('');
% this_block.addFile('');
this_block.addFile('fir_core.vhd');
return;
% ------------------------------------------------------------
function setup_as_single_rate(block,clkname,cename)
inputRates = block.inputRates;
uniqueInputRates = unique(inputRates);
if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf)
block.addError('The inputs to this block cannot all be constant.');
return;
end
if (uniqueInputRates(end) == Inf)
hasConstantInput = true;
uniqueInputRates = uniqueInputRates(1:end-1);
end
if (length(uniqueInputRates) ~= 1)
block.addError('The inputs to this block must run at a single rate.');
return;
end
theInputRate = uniqueInputRates(1);
for i = 1:block.numSimulinkOutports
block.outport(i).setRate(theInputRate);
end
block.addClkCEPair(clkname,cename,theInputRate);
return;
% ------------------------------------------------------------