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4kiu.txt
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4kiu.txt
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sbc-bench v0.9.9 HUAQIN P6410 HQ3110BR49000 (Wed, 04 Jan 2023 02:11:10 +0000)
Distributor ID: Ubuntu
Description: Ubuntu 20.04.5 LTS
Release: 20.04
Codename: focal
Device Info:
Manufacturer: HUAQIN
Product Name: P6410 HQ3110BR49000
SKU Number: Unknown
Family: Altra Max
BIOS/UEFI:
Vendor: American Megatrends International LLC
Version: 1.15.00
Release Date: 11/25/2022
BIOS Revision: 5.15
Firmware Revision: 2.10
/usr/bin/gcc (Ubuntu 9.4.0-1ubuntu1~20.04.1) 9.4.0
Uptime: 02:11:11 up 1:07, 4 users, load average: 0.78, 1.99, 28.99, °C, 57484481
Linux 5.4.219-sg1-dk (p6410-server) 01/04/23 _aarch64_ (256 CPU)
avg-cpu: %user %nice %system %iowait %steal %idle
36.35 0.01 0.80 0.00 0.00 62.84
Device tps kB_read/s kB_wrtn/s kB_dscd/s kB_read kB_wrtn kB_dscd
nvme0n1 21.37 910.29 144.33 0.00 3680793 583601 0
total used free shared buff/cache available
Mem: 375Gi 3.5Gi 371Gi 4.0Mi 576Mi 370Gi
Swap: 8.0Gi 0B 8.0Gi
Filename Type Size Used Priority
/swap.img file 8388604 0 -2
##########################################################################
Checking cpufreq OPP for cpu0 (Neoverse-N1):
Cpufreq OPP: 3000 Measured: 2998 (2999.085/2998.946/2998.806)
Cpufreq OPP: 1000 Measured: 1030 (1030.567/1030.567/1030.466) (+3.0%)
Checking cpufreq OPP for cpu1 (Neoverse-N1):
Cpufreq OPP: 3000 Measured: 2998 (2999.155/2998.876/2998.806)
Cpufreq OPP: 1000 Measured: 1030 (1030.541/1030.516/1030.466) (+3.0%)
Checking cpufreq OPP for cpu2 (Neoverse-N1):
Cpufreq OPP: 3000 Measured: 2998 (2999.085/2998.876/2998.249)
Cpufreq OPP: 1000 Measured: 1030 (1030.491/1030.416/1030.416) (+3.0%)
Checking cpufreq OPP for cpu3 (Neoverse-N1):
Cpufreq OPP: 3000 Measured: 2999 (2999.085/2999.085/2998.946)
Cpufreq OPP: 1000 Measured: 1030 (1030.541/1030.541/1030.541) (+3.0%)
Checking cpufreq OPP for cpu4 (Neoverse-N1):
Cpufreq OPP: 3000 Measured: 2999 (2999.085/2999.085/2998.876)
Cpufreq OPP: 1000 Measured: 1030 (1030.541/1030.516/1030.491) (+3.0%)
Checking cpufreq OPP for cpu5 (Neoverse-N1):
Cpufreq OPP: 3000 Measured: 2999 (2999.155/2999.015/2998.946)
Cpufreq OPP: 1000 Measured: 1030 (1030.567/1030.466/1030.416) (+3.0%)
Checking cpufreq OPP for cpu6 (Neoverse-N1):
Cpufreq OPP: 3000 Measured: 2999 (2999.224/2999.085/2998.946)
Cpufreq OPP: 1000 Measured: 1030 (1030.516/1030.466/1030.441) (+3.0%)
Checking cpufreq OPP for cpu7 (Neoverse-N1):
Cpufreq OPP: 3000 Measured: 2999 (2999.085/2999.015/2998.946)
Cpufreq OPP: 1000 Measured: 1030 (1030.491/1030.466/1030.466) (+3.0%)
Checking cpufreq OPP for cpu8 (Neoverse-N1):
Cpufreq OPP: 3000 Measured: 2998 (2999.015/2998.946/2998.806)
Cpufreq OPP: 1000 Measured: 1030 (1030.642/1030.541/1030.466) (+3.0%)
Checking cpufreq OPP for cpu9-cpu255 (Neoverse-N1):
Cpufreq OPP: 3000 Measured: 2998 (2999.155/2998.946/2998.737)
Cpufreq OPP: 1000 Measured: 1030 (1030.491/1030.491/1030.416) (+3.0%)
##########################################################################
Hardware sensors:
apm_xgene-isa-0000
SoC Temperature: +44.0 C
CPU power: 20.00 W
IO power: 21.02 W
apm_xgene-isa-0000
SoC Temperature: +43.0 C
CPU power: 20.80 W
IO power: 18.02 W
##########################################################################
Executing benchmark on cpu0 (Neoverse-N1):
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 12409.7 MB/s
C copy backwards (32 byte blocks) : 12335.0 MB/s
C copy backwards (64 byte blocks) : 12342.2 MB/s
C copy : 12605.8 MB/s
C copy prefetched (32 bytes step) : 13128.9 MB/s (0.5%)
C copy prefetched (64 bytes step) : 13137.9 MB/s
C 2-pass copy : 5898.5 MB/s (0.2%)
C 2-pass copy prefetched (32 bytes step) : 7893.7 MB/s (0.1%)
C 2-pass copy prefetched (64 bytes step) : 7802.1 MB/s (0.2%)
C fill : 47039.0 MB/s
C fill (shuffle within 16 byte blocks) : 47031.0 MB/s
C fill (shuffle within 32 byte blocks) : 47024.3 MB/s
C fill (shuffle within 64 byte blocks) : 47035.3 MB/s
---
standard memcpy : 13254.1 MB/s
standard memset : 47953.1 MB/s
---
NEON LDP/STP copy : 13360.2 MB/s
NEON LDP/STP copy pldl2strm (32 bytes step) : 14780.8 MB/s (0.2%)
NEON LDP/STP copy pldl2strm (64 bytes step) : 14800.8 MB/s
NEON LDP/STP copy pldl1keep (32 bytes step) : 15035.3 MB/s (0.2%)
NEON LDP/STP copy pldl1keep (64 bytes step) : 15000.1 MB/s (0.1%)
NEON LD1/ST1 copy : 13391.6 MB/s
NEON STP fill : 47946.4 MB/s
NEON STNP fill : 47949.2 MB/s
ARM LDP/STP copy : 13434.9 MB/s
ARM STP fill : 47935.4 MB/s
ARM STNP fill : 47879.9 MB/s
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON LDP/STP copy (from framebuffer) : 111.9 MB/s (3.5%)
NEON LDP/STP 2-pass copy (from framebuffer) : 114.8 MB/s (1.3%)
NEON LD1/ST1 copy (from framebuffer) : 115.2 MB/s (0.7%)
NEON LD1/ST1 2-pass copy (from framebuffer) : 106.9 MB/s (0.8%)
ARM LDP/STP copy (from framebuffer) : 111.3 MB/s (2.9%)
ARM LDP/STP 2-pass copy (from framebuffer) : 114.6 MB/s (1.1%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 0.0 ns / 0.0 ns
131072 : 1.2 ns / 1.7 ns
262144 : 2.2 ns / 2.8 ns
524288 : 3.2 ns / 3.7 ns
1048576 : 6.8 ns / 9.4 ns
2097152 : 16.7 ns / 23.4 ns
4194304 : 23.3 ns / 28.9 ns
8388608 : 29.2 ns / 33.0 ns
16777216 : 38.3 ns / 47.9 ns
33554432 : 69.3 ns / 91.0 ns
67108864 : 89.3 ns / 109.6 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 0.0 ns / 0.0 ns
131072 : 1.2 ns / 1.7 ns
262144 : 1.8 ns / 2.2 ns
524288 : 2.1 ns / 2.4 ns
1048576 : 2.4 ns / 2.5 ns
2097152 : 15.1 ns / 21.9 ns
4194304 : 21.5 ns / 27.2 ns
8388608 : 24.8 ns / 28.8 ns
16777216 : 26.8 ns / 29.9 ns
33554432 : 63.0 ns / 83.7 ns
67108864 : 81.7 ns / 100.8 ns
Executing benchmark on cpu1 (Neoverse-N1):
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 12447.9 MB/s
C copy backwards (32 byte blocks) : 12364.8 MB/s
C copy backwards (64 byte blocks) : 12369.5 MB/s
C copy : 12597.6 MB/s
C copy prefetched (32 bytes step) : 13121.7 MB/s
C copy prefetched (64 bytes step) : 13135.3 MB/s
C 2-pass copy : 5897.2 MB/s (0.3%)
C 2-pass copy prefetched (32 bytes step) : 7883.8 MB/s
C 2-pass copy prefetched (64 bytes step) : 7798.0 MB/s (0.1%)
C fill : 47031.6 MB/s
C fill (shuffle within 16 byte blocks) : 47047.6 MB/s
C fill (shuffle within 32 byte blocks) : 47046.7 MB/s
C fill (shuffle within 64 byte blocks) : 47016.1 MB/s
---
standard memcpy : 13247.3 MB/s
standard memset : 47962.6 MB/s
---
NEON LDP/STP copy : 13350.9 MB/s
NEON LDP/STP copy pldl2strm (32 bytes step) : 14802.2 MB/s (0.1%)
NEON LDP/STP copy pldl2strm (64 bytes step) : 14852.0 MB/s (0.1%)
NEON LDP/STP copy pldl1keep (32 bytes step) : 15047.1 MB/s (0.1%)
NEON LDP/STP copy pldl1keep (64 bytes step) : 15018.7 MB/s (0.2%)
NEON LD1/ST1 copy : 13396.2 MB/s
NEON STP fill : 47963.4 MB/s
NEON STNP fill : 47971.9 MB/s
ARM LDP/STP copy : 13439.5 MB/s
ARM STP fill : 47962.1 MB/s
ARM STNP fill : 47950.2 MB/s
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON LDP/STP copy (from framebuffer) : 110.9 MB/s
NEON LDP/STP 2-pass copy (from framebuffer) : 114.7 MB/s (1.1%)
NEON LD1/ST1 copy (from framebuffer) : 114.6 MB/s (0.4%)
NEON LD1/ST1 2-pass copy (from framebuffer) : 114.7 MB/s (1.2%)
ARM LDP/STP copy (from framebuffer) : 112.6 MB/s (1.0%)
ARM LDP/STP 2-pass copy (from framebuffer) : 114.2 MB/s (1.1%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 0.0 ns / 0.0 ns
131072 : 1.2 ns / 1.7 ns
262144 : 2.2 ns / 2.8 ns
524288 : 3.2 ns / 3.6 ns
1048576 : 6.6 ns / 9.2 ns
2097152 : 16.6 ns / 23.4 ns
4194304 : 23.3 ns / 28.9 ns
8388608 : 29.3 ns / 33.1 ns
16777216 : 38.4 ns / 47.9 ns
33554432 : 69.3 ns / 91.2 ns
67108864 : 89.6 ns / 110.0 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 0.0 ns / 0.0 ns
131072 : 1.2 ns / 1.7 ns
262144 : 1.8 ns / 2.2 ns
524288 : 2.1 ns / 2.4 ns
1048576 : 2.4 ns / 2.5 ns
2097152 : 15.1 ns / 21.9 ns
4194304 : 21.6 ns / 27.2 ns
8388608 : 24.8 ns / 28.8 ns
16777216 : 26.8 ns / 30.0 ns
33554432 : 62.9 ns / 83.7 ns
67108864 : 81.7 ns / 100.8 ns
Executing benchmark on cpu2 (Neoverse-N1):
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 12432.2 MB/s
C copy backwards (32 byte blocks) : 12347.0 MB/s
C copy backwards (64 byte blocks) : 12353.7 MB/s
C copy : 12623.6 MB/s
C copy prefetched (32 bytes step) : 13187.1 MB/s
C copy prefetched (64 bytes step) : 13203.8 MB/s
C 2-pass copy : 5904.3 MB/s (0.5%)
C 2-pass copy prefetched (32 bytes step) : 7896.7 MB/s (0.1%)
C 2-pass copy prefetched (64 bytes step) : 7809.3 MB/s (0.1%)
C fill : 47050.7 MB/s
C fill (shuffle within 16 byte blocks) : 47049.8 MB/s
C fill (shuffle within 32 byte blocks) : 47046.3 MB/s
C fill (shuffle within 64 byte blocks) : 47038.1 MB/s
---
standard memcpy : 13311.4 MB/s
standard memset : 47961.7 MB/s
---
NEON LDP/STP copy : 13402.0 MB/s
NEON LDP/STP copy pldl2strm (32 bytes step) : 14803.3 MB/s (0.2%)
NEON LDP/STP copy pldl2strm (64 bytes step) : 14850.6 MB/s (0.2%)
NEON LDP/STP copy pldl1keep (32 bytes step) : 15062.0 MB/s (0.1%)
NEON LDP/STP copy pldl1keep (64 bytes step) : 15023.8 MB/s (0.1%)
NEON LD1/ST1 copy : 13439.0 MB/s
NEON STP fill : 47943.9 MB/s
NEON STNP fill : 47966.5 MB/s
ARM LDP/STP copy : 13465.3 MB/s
ARM STP fill : 47951.9 MB/s
ARM STNP fill : 47931.2 MB/s
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON LDP/STP copy (from framebuffer) : 112.1 MB/s (0.7%)
NEON LDP/STP 2-pass copy (from framebuffer) : 114.4 MB/s (1.1%)
NEON LD1/ST1 copy (from framebuffer) : 116.2 MB/s (1.0%)
NEON LD1/ST1 2-pass copy (from framebuffer) : 114.0 MB/s (0.9%)
ARM LDP/STP copy (from framebuffer) : 112.8 MB/s (0.9%)
ARM LDP/STP 2-pass copy (from framebuffer) : 114.7 MB/s (1.0%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 0.0 ns / 0.0 ns
131072 : 1.2 ns / 1.7 ns
262144 : 2.2 ns / 2.8 ns
524288 : 3.2 ns / 3.7 ns
1048576 : 6.9 ns / 9.7 ns
2097152 : 16.5 ns / 23.3 ns
4194304 : 23.2 ns / 28.7 ns
8388608 : 28.9 ns / 33.0 ns
16777216 : 37.9 ns / 47.1 ns
33554432 : 69.0 ns / 90.9 ns
67108864 : 89.2 ns / 109.6 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 0.0 ns / 0.0 ns
131072 : 1.2 ns / 1.7 ns
262144 : 1.8 ns / 2.2 ns
524288 : 2.1 ns / 2.4 ns
1048576 : 2.4 ns / 2.5 ns
2097152 : 15.1 ns / 21.8 ns
4194304 : 21.5 ns / 27.1 ns
8388608 : 24.7 ns / 28.7 ns
16777216 : 26.7 ns / 29.8 ns
33554432 : 62.8 ns / 83.5 ns
67108864 : 81.7 ns / 100.7 ns
Executing benchmark on cpu3 (Neoverse-N1):
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 12461.3 MB/s
C copy backwards (32 byte blocks) : 12387.2 MB/s
C copy backwards (64 byte blocks) : 12390.2 MB/s
C copy : 12616.9 MB/s
C copy prefetched (32 bytes step) : 13182.6 MB/s
C copy prefetched (64 bytes step) : 13198.6 MB/s
C 2-pass copy : 5752.9 MB/s
C 2-pass copy prefetched (32 bytes step) : 7591.9 MB/s
C 2-pass copy prefetched (64 bytes step) : 7149.3 MB/s (0.1%)
C fill : 47024.7 MB/s
C fill (shuffle within 16 byte blocks) : 47044.4 MB/s
C fill (shuffle within 32 byte blocks) : 47049.1 MB/s
C fill (shuffle within 64 byte blocks) : 47038.3 MB/s
---
standard memcpy : 13304.7 MB/s
standard memset : 47945.4 MB/s
---
NEON LDP/STP copy : 13397.6 MB/s
NEON LDP/STP copy pldl2strm (32 bytes step) : 14817.2 MB/s (0.1%)
NEON LDP/STP copy pldl2strm (64 bytes step) : 14873.2 MB/s
NEON LDP/STP copy pldl1keep (32 bytes step) : 15065.3 MB/s (0.1%)
NEON LDP/STP copy pldl1keep (64 bytes step) : 15037.5 MB/s (0.1%)
NEON LD1/ST1 copy : 13421.8 MB/s
NEON STP fill : 47939.8 MB/s
NEON STNP fill : 47965.5 MB/s
ARM LDP/STP copy : 13450.8 MB/s
ARM STP fill : 47949.7 MB/s
ARM STNP fill : 47951.1 MB/s
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON LDP/STP copy (from framebuffer) : 113.5 MB/s (1.0%)
NEON LDP/STP 2-pass copy (from framebuffer) : 113.8 MB/s (0.8%)
NEON LD1/ST1 copy (from framebuffer) : 116.0 MB/s (0.9%)
NEON LD1/ST1 2-pass copy (from framebuffer) : 114.3 MB/s (0.9%)
ARM LDP/STP copy (from framebuffer) : 112.3 MB/s (1.0%)
ARM LDP/STP 2-pass copy (from framebuffer) : 115.1 MB/s (1.1%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 0.0 ns / 0.0 ns
131072 : 1.2 ns / 1.7 ns
262144 : 2.2 ns / 2.8 ns
524288 : 3.2 ns / 3.6 ns
1048576 : 6.6 ns / 9.4 ns
2097152 : 16.6 ns / 23.3 ns
4194304 : 23.2 ns / 28.7 ns
8388608 : 28.9 ns / 33.0 ns
16777216 : 37.9 ns / 47.2 ns
33554432 : 69.1 ns / 90.9 ns
67108864 : 89.2 ns / 109.6 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 0.0 ns / 0.0 ns
131072 : 1.2 ns / 1.7 ns
262144 : 1.8 ns / 2.2 ns
524288 : 2.1 ns / 2.4 ns
1048576 : 2.4 ns / 2.5 ns
2097152 : 15.1 ns / 21.8 ns
4194304 : 21.5 ns / 27.1 ns
8388608 : 24.7 ns / 28.7 ns
16777216 : 26.7 ns / 29.8 ns
33554432 : 62.8 ns / 83.6 ns
67108864 : 81.6 ns / 100.7 ns
Executing benchmark on cpu4 (Neoverse-N1):
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 12387.3 MB/s
C copy backwards (32 byte blocks) : 12302.1 MB/s
C copy backwards (64 byte blocks) : 12311.0 MB/s
C copy : 12547.0 MB/s
C copy prefetched (32 bytes step) : 13095.8 MB/s
C copy prefetched (64 bytes step) : 13119.3 MB/s
C 2-pass copy : 5893.0 MB/s (0.7%)
C 2-pass copy prefetched (32 bytes step) : 7895.5 MB/s (0.1%)
C 2-pass copy prefetched (64 bytes step) : 7790.0 MB/s (0.1%)
C fill : 47031.7 MB/s
C fill (shuffle within 16 byte blocks) : 47050.2 MB/s
C fill (shuffle within 32 byte blocks) : 47045.4 MB/s
C fill (shuffle within 64 byte blocks) : 47029.0 MB/s
---
standard memcpy : 13233.3 MB/s
standard memset : 47936.2 MB/s
---
NEON LDP/STP copy : 13322.1 MB/s
NEON LDP/STP copy pldl2strm (32 bytes step) : 14744.7 MB/s
NEON LDP/STP copy pldl2strm (64 bytes step) : 14811.0 MB/s (0.1%)
NEON LDP/STP copy pldl1keep (32 bytes step) : 15004.4 MB/s
NEON LDP/STP copy pldl1keep (64 bytes step) : 14983.7 MB/s (0.1%)
NEON LD1/ST1 copy : 13358.4 MB/s
NEON STP fill : 47972.6 MB/s
NEON STNP fill : 47972.2 MB/s
ARM LDP/STP copy : 13385.3 MB/s
ARM STP fill : 47947.1 MB/s
ARM STNP fill : 47947.8 MB/s
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON LDP/STP copy (from framebuffer) : 111.6 MB/s (0.4%)
NEON LDP/STP 2-pass copy (from framebuffer) : 114.8 MB/s (1.1%)
NEON LD1/ST1 copy (from framebuffer) : 115.5 MB/s (0.8%)
NEON LD1/ST1 2-pass copy (from framebuffer) : 115.0 MB/s (1.1%)
ARM LDP/STP copy (from framebuffer) : 113.0 MB/s (1.1%)
ARM LDP/STP 2-pass copy (from framebuffer) : 114.1 MB/s (0.9%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 0.0 ns / 0.0 ns
131072 : 1.2 ns / 1.7 ns
262144 : 2.2 ns / 2.8 ns
524288 : 3.2 ns / 3.6 ns
1048576 : 6.9 ns / 9.9 ns
2097152 : 16.8 ns / 23.4 ns
4194304 : 23.3 ns / 28.9 ns
8388608 : 29.2 ns / 33.1 ns
16777216 : 38.0 ns / 47.3 ns
33554432 : 69.6 ns / 91.5 ns
67108864 : 89.8 ns / 110.2 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 0.0 ns / 0.0 ns
131072 : 1.2 ns / 1.7 ns
262144 : 1.8 ns / 2.2 ns
524288 : 2.1 ns / 2.4 ns
1048576 : 2.4 ns / 2.5 ns
2097152 : 15.1 ns / 21.9 ns
4194304 : 21.6 ns / 27.2 ns
8388608 : 24.8 ns / 28.8 ns
16777216 : 26.7 ns / 29.9 ns
33554432 : 63.1 ns / 84.1 ns
67108864 : 82.0 ns / 101.2 ns
Executing benchmark on cpu5 (Neoverse-N1):
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 12405.7 MB/s
C copy backwards (32 byte blocks) : 12314.2 MB/s
C copy backwards (64 byte blocks) : 12321.0 MB/s
C copy : 12578.8 MB/s
C copy prefetched (32 bytes step) : 13130.8 MB/s
C copy prefetched (64 bytes step) : 13144.2 MB/s
C 2-pass copy : 5724.0 MB/s
C 2-pass copy prefetched (32 bytes step) : 7572.9 MB/s
C 2-pass copy prefetched (64 bytes step) : 7133.1 MB/s (0.1%)
C fill : 47023.6 MB/s
C fill (shuffle within 16 byte blocks) : 47039.1 MB/s
C fill (shuffle within 32 byte blocks) : 47034.0 MB/s
C fill (shuffle within 64 byte blocks) : 47039.2 MB/s
---
standard memcpy : 13261.0 MB/s
standard memset : 47962.4 MB/s
---
NEON LDP/STP copy : 13333.5 MB/s
NEON LDP/STP copy pldl2strm (32 bytes step) : 14744.9 MB/s
NEON LDP/STP copy pldl2strm (64 bytes step) : 14843.7 MB/s (0.1%)
NEON LDP/STP copy pldl1keep (32 bytes step) : 15031.1 MB/s (0.2%)
NEON LDP/STP copy pldl1keep (64 bytes step) : 14984.2 MB/s (0.3%)
NEON LD1/ST1 copy : 13367.1 MB/s
NEON STP fill : 47965.8 MB/s
NEON STNP fill : 47962.8 MB/s
ARM LDP/STP copy : 13400.6 MB/s
ARM STP fill : 47958.9 MB/s
ARM STNP fill : 47918.3 MB/s
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON LDP/STP copy (from framebuffer) : 112.3 MB/s (0.8%)
NEON LDP/STP 2-pass copy (from framebuffer) : 114.1 MB/s (1.2%)
NEON LD1/ST1 copy (from framebuffer) : 114.8 MB/s (0.6%)
NEON LD1/ST1 2-pass copy (from framebuffer) : 115.0 MB/s (1.0%)
ARM LDP/STP copy (from framebuffer) : 112.0 MB/s (0.8%)
ARM LDP/STP 2-pass copy (from framebuffer) : 113.9 MB/s (1.0%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 0.0 ns / 0.0 ns
131072 : 1.2 ns / 1.7 ns
262144 : 2.2 ns / 2.8 ns
524288 : 3.2 ns / 3.7 ns
1048576 : 5.9 ns / 8.2 ns
2097152 : 16.7 ns / 23.4 ns
4194304 : 23.3 ns / 28.9 ns
8388608 : 29.2 ns / 33.1 ns
16777216 : 38.6 ns / 46.8 ns
33554432 : 69.7 ns / 91.5 ns
67108864 : 89.8 ns / 110.3 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 0.0 ns / 0.0 ns
131072 : 1.2 ns / 1.7 ns
262144 : 1.8 ns / 2.2 ns
524288 : 2.1 ns / 2.4 ns
1048576 : 2.4 ns / 2.5 ns
2097152 : 15.1 ns / 21.9 ns
4194304 : 21.6 ns / 27.2 ns
8388608 : 24.8 ns / 28.8 ns
16777216 : 26.8 ns / 29.9 ns
33554432 : 63.1 ns / 84.0 ns
67108864 : 82.0 ns / 101.2 ns
Executing benchmark on cpu6 (Neoverse-N1):
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 12406.4 MB/s
C copy backwards (32 byte blocks) : 12325.1 MB/s
C copy backwards (64 byte blocks) : 12325.8 MB/s
C copy : 12567.5 MB/s
C copy prefetched (32 bytes step) : 13141.9 MB/s
C copy prefetched (64 bytes step) : 13163.2 MB/s
C 2-pass copy : 5892.8 MB/s (0.5%)
C 2-pass copy prefetched (32 bytes step) : 7905.1 MB/s (0.1%)
C 2-pass copy prefetched (64 bytes step) : 7791.5 MB/s
C fill : 47045.4 MB/s
C fill (shuffle within 16 byte blocks) : 47040.5 MB/s
C fill (shuffle within 32 byte blocks) : 47043.4 MB/s
C fill (shuffle within 64 byte blocks) : 47016.8 MB/s
---
standard memcpy : 13260.7 MB/s
standard memset : 47962.0 MB/s
---
NEON LDP/STP copy : 13346.7 MB/s
NEON LDP/STP copy pldl2strm (32 bytes step) : 14770.4 MB/s (0.1%)
NEON LDP/STP copy pldl2strm (64 bytes step) : 14790.0 MB/s
NEON LDP/STP copy pldl1keep (32 bytes step) : 15006.7 MB/s (0.1%)
NEON LDP/STP copy pldl1keep (64 bytes step) : 14960.9 MB/s
NEON LD1/ST1 copy : 13369.7 MB/s
NEON STP fill : 47943.4 MB/s
NEON STNP fill : 47967.6 MB/s
ARM LDP/STP copy : 13393.0 MB/s
ARM STP fill : 47954.4 MB/s
ARM STNP fill : 47930.8 MB/s
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON LDP/STP copy (from framebuffer) : 113.3 MB/s (1.0%)
NEON LDP/STP 2-pass copy (from framebuffer) : 114.3 MB/s (1.1%)
NEON LD1/ST1 copy (from framebuffer) : 115.5 MB/s (0.7%)
NEON LD1/ST1 2-pass copy (from framebuffer) : 114.1 MB/s (1.0%)
ARM LDP/STP copy (from framebuffer) : 112.9 MB/s (1.0%)
ARM LDP/STP 2-pass copy (from framebuffer) : 114.7 MB/s (1.1%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================