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OpenRAM Documentation

OpenRAM Logo

These pages provide the documentation of OpenRAM. You can use the links below to navigate through the documentation.

Table of Contents

  1. OpenRAM Dependencies
  2. Supported Technologies
  3. Online Playground
  4. Basic Setup
  5. Basic SRAM Usage
  6. Basic ROM Usage
  7. Python Library
  8. Bitcells
  9. Architecture
  10. Implementation
  11. Technology and Tool Portability
  12. Tutorials
  13. Debugging and Unit Testing
  14. Technology Setup
  15. Library Cells
  16. Base Data Structures
  17. Hierarchical Design Modules
  18. Control Logic and Timing
  19. Routing
  20. Characterization
  21. Results
  22. FAQ
  23. Contributors/Collaborators

OpenRAM Dependencies

In general, the OpenRAM compiler has very few dependencies:

  • Git
  • Make
  • Python 3.5 or higher
  • Various Python packages (pip install -r requirements.txt)
  • Anaconda

Commercial tools (optional):

  • Spice Simulator
    • Hspice I-2013.12-1 (or later)
    • CustomSim 2017 (or later)
  • DRC
    • Calibre 2017.3_29.23
  • LVS
    • Calibre 2017.3_29.23

Supported Technologies

  • NCSU FreePDK 45nm
    • Non-fabricable but contains DSM rules
    • Calibre or klayout for DRC/LVS
  • MOSIS 0.35um (SCN4M_SUBM)
    • Fabricable technology
    • Magic/Netgen or Calibre for DRC/LVS
  • Skywater 130nm (sky130)
    • Fabricable technology
    • Magic/Netgen or klayout

Implementation

  • Front-end mode
    • Generates SPICE, layout views, timing models
      • Netlist-only mode can skip the physical design too
    • Doesn't perform DRC/LVS
    • Estimates power/delay analytically
  • Back-end mode
    • Generates SPICE, layout views, timing models
    • Performs DRC/LVS
      • Can perform at each level of hierarchy or at the end
    • Simulates power/delay
      • Can be back-annotated or not

Technology and Tool Portability

  • OpenRAM is technology independent by using a technology directory that includes:
    • Technology's specific information
    • Technology's rules such as DRC rules and the GDS layer map
    • Custom designed library cells (6T, sense amp, DFF) to improve the SRAM density.
  • For technologies that have specific design requirements, such as specialized well contacts, the user can include helper functions in the technology directory.
  • Verification wrapper scripts
    • Uses a wrapper interface with DRC and LVS tools that allow flexibility
    • DRC and LVS can be performed at all levels of the design hierarchy to enhance bug tracking.
    • DRC and LVS can be disabled completely for improved run-time or if licenses are not available.

Contributors/Collaborators

  • Prof. Matthew Guthaus (UCSC)
  • Prof. James Stine & Dr. Samira Ataei (Oklahoma State University)
  • UCSC students:
  • Many other past students:
    • Jeff Butera
    • Tom Golubev
    • Marcelo Sero
    • Seokjoong Kim
    • Sage Walker