From 735a5f67e351fc072a9f7c18b030036681f7935a Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Mon, 30 Sep 2024 13:24:55 +0100 Subject: [PATCH] [AMDGPU] When allocating VGPRs, VGPR spills are not part of the prologue (#109439) PRs #69924 and #72140 modified SIInstrInfo::isBasicBlockPrologue to skip over EXEC modifications and spills when allocating VGPRs. But treating VGPR spills as part of the prologue can confuse the register allocator as in #109294, so restrict it to SGPR spills, which were inserted during SGPR allocation which is done in an earlier pass. Fixes: #109294 Fixes: SWDEV-485841 --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 44ee5c56a237b4..5c39b2a4fc96aa 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -8899,11 +8899,10 @@ bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI, } uint16_t Opcode = MI.getOpcode(); - // FIXME: Copies inserted in the block prolog for live-range split should also - // be included. return IsNullOrVectorRegister && - (isSpill(Opcode) || (!MI.isTerminator() && Opcode != AMDGPU::COPY && - MI.modifiesRegister(AMDGPU::EXEC, &RI))); + (isSGPRSpill(Opcode) || + (!MI.isTerminator() && Opcode != AMDGPU::COPY && + MI.modifiesRegister(AMDGPU::EXEC, &RI))); } MachineInstrBuilder