Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

SD clock generation #8

Open
harbaum opened this issue Dec 28, 2023 · 0 comments
Open

SD clock generation #8

harbaum opened this issue Dec 28, 2023 · 0 comments

Comments

@harbaum
Copy link

harbaum commented Dec 28, 2023 •
edited
Loading

What is the intended sd card clock rate?

From the comments, it seems that it's supposed to stay below 25Mhz as CLK_DIV is adjusted to one for up to 25Mhz, to 2 for 25 to 50 Mhz and so on ...

However, the resulting clock is much lower. Clockdivr is clockdiv + 1 and clkcnt counts to { clkdivr, 1}. With CLK_DIV set to 2 the counter runs from 0 to 7, effectively dividing the system clock by 8. So on a 32Mhz system, the SD card clock is 4 Mhz. Is this intended that way?
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@harbaum