From 45112d356dfcd24c6fa804f1817567835600b154 Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Fri, 5 Feb 2021 17:55:17 -0800 Subject: [PATCH 1/6] Final opcodes --- proposals/simd/BinarySIMD.md | 80 ++++++++++++++++++------------------ proposals/simd/NewOpcodes.md | 65 +++++++++++++++++++++++++---- 2 files changed, 96 insertions(+), 49 deletions(-) diff --git a/proposals/simd/BinarySIMD.md b/proposals/simd/BinarySIMD.md index c1cc39cdf..075fb67f6 100644 --- a/proposals/simd/BinarySIMD.md +++ b/proposals/simd/BinarySIMD.md @@ -228,43 +228,43 @@ For example, `ImmLaneIdx16` is a byte with values in the range 0-15 (inclusive). | `f32x4.convert_i32x4_u` | `0xfb`| - | | `v128.load32_zero` | `0xfc`| - | | `v128.load64_zero` | `0xfd`| - | -| `i16x8.extmul_low_i8x16_s` | `0x110`| - | -| `i16x8.extmul_high_i8x16_s` | `0x111`| - | -| `i16x8.extmul_low_i8x16_u` | `0x112`| - | -| `i16x8.extmul_high_i8x16_u` | `0x113`| - | -| `i32x4.extmul_low_i16x8_s` | `0x114`| - | -| `i32x4.extmul_high_i16x8_s` | `0x115`| - | -| `i32x4.extmul_low_i16x8_u` | `0x116`| - | -| `i32x4.extmul_high_i16x8_u` | `0x117`| - | -| `i64x2.extmul_low_i32x4_s` | `0x118`| - | -| `i64x2.extmul_high_i32x4_s` | `0x119`| - | -| `i64x2.extmul_low_i32x4_u` | `0x11a`| - | -| `i64x2.extmul_high_i32x4_u` | `0x11b`| - | -| `i16x8.q15mulr_sat_s` | `TBD`| - | -| `v128.any_true` | `TBD`| - | -| `v128.load8_lane` | `TBD`| m:memarg, i:ImmLaneIdx16 | -| `v128.load16_lane` | `TBD`| m:memarg, i:ImmLaneIdx8 | -| `v128.load32_lane` | `TBD`| m:memarg, i:ImmLaneIdx4 | -| `v128.load64_lane` | `TBD`| m:memarg, i:ImmLaneIdx2 | -| `v128.store8_lane` | `TBD`| m:memarg, i:ImmLaneIdx16 | -| `v128.store16_lane` | `TBD`| m:memarg, i:ImmLaneIdx8 | -| `v128.store32_lane` | `TBD`| m:memarg, i:ImmLaneIdx4 | -| `v128.store64_lane` | `TBD`| m:memarg, i:ImmLaneIdx2 | -| `i64x2.eq` | `TBD`| - | -| `i64x2.ne` | `TBD`| - | -| `i64x2.lt_s` | `TBD`| - | -| `i64x2.gt_s` | `TBD`| - | -| `i64x2.le_s` | `TBD`| - | -| `i64x2.ge_s` | `TBD`| - | -| `i64x2.all_true` | `TBD`| - | -| `f64x2.convert_low_i32x4_s` | `TBD`| - | -| `f64x2.convert_low_i32x4_u` | `TBD`| - | -| `i32x4.trunc_sat_f64x2_s_zero` | `TBD`| - | -| `i32x4.trunc_sat_f64x2_u_zero` | `TBD`| - | -| `f32x4.demote_f64x2_zero` | `TBD`| - | -| `f64x2.promote_low_f32x4` | `TBD`| - | -| `i8x16.popcnt` | `TBD`| - | -| `i16x8.extadd_pairwise_i8x16_s` | `TBD`| - | -| `i16x8.extadd_pairwise_i8x16_u` | `TBD`| - | -| `i32x4.extadd_pairwise_i16x8_s` | `TBD`| - | -| `i32x4.extadd_pairwise_i16x8_u` | `TBD`| - | +| `i16x8.extmul_low_i8x16_s` | `0x10c`| - | +| `i16x8.extmul_high_i8x16_s` | `0x10d`| - | +| `i16x8.extmul_low_i8x16_u` | `0x10e`| - | +| `i16x8.extmul_high_i8x16_u` | `0x10f`| - | +| `i32x4.extmul_low_i16x8_s` | `0x110`| - | +| `i32x4.extmul_high_i16x8_s` | `0x111`| - | +| `i32x4.extmul_low_i16x8_u` | `0x112`| - | +| `i32x4.extmul_high_i16x8_u` | `0x113`| - | +| `i64x2.extmul_low_i32x4_s` | `0x114`| - | +| `i64x2.extmul_high_i32x4_s` | `0x115`| - | +| `i64x2.extmul_low_i32x4_u` | `0x116`| - | +| `i64x2.extmul_high_i32x4_u` | `0x117`| - | +| `i16x8.q15mulr_sat_s` | `0x9c`| - | +| `v128.any_true` | `0x53`| - | +| `v128.load8_lane` | `0x54`| m:memarg, i:ImmLaneIdx16 | +| `v128.load16_lane` | `0x55`| m:memarg, i:ImmLaneIdx8 | +| `v128.load32_lane` | `0x56`| m:memarg, i:ImmLaneIdx4 | +| `v128.load64_lane` | `0x57`| m:memarg, i:ImmLaneIdx2 | +| `v128.store8_lane` | `0x58`| m:memarg, i:ImmLaneIdx16 | +| `v128.store16_lane` | `0x59`| m:memarg, i:ImmLaneIdx8 | +| `v128.store32_lane` | `0x5a`| m:memarg, i:ImmLaneIdx4 | +| `v128.store64_lane` | `0x5b`| m:memarg, i:ImmLaneIdx2 | +| `i64x2.eq` | `0x102`| - | +| `i64x2.ne` | `0x103`| - | +| `i64x2.lt_s` | `0x104`| - | +| `i64x2.gt_s` | `0x105`| - | +| `i64x2.le_s` | `0x106`| - | +| `i64x2.ge_s` | `0x107`| - | +| `i64x2.all_true` | `0xc3`| - | +| `f64x2.convert_low_i32x4_s` | `0xfc`| - | +| `f64x2.convert_low_i32x4_u` | `0xfd`| - | +| `i32x4.trunc_sat_f64x2_s_zero` | `0xfe`| - | +| `i32x4.trunc_sat_f64x2_u_zero` | `0xff`| - | +| `f32x4.demote_f64x2_zero` | `0x100`| - | +| `f64x2.promote_low_f32x4` | `0x101`| - | +| `i8x16.popcnt` | `0x74`| - | +| `i16x8.extadd_pairwise_i8x16_s` | `0x108`| - | +| `i16x8.extadd_pairwise_i8x16_u` | `0x109`| - | +| `i32x4.extadd_pairwise_i16x8_s` | `0x10a`| - | +| `i32x4.extadd_pairwise_i16x8_u` | `0x10b`| - | diff --git a/proposals/simd/NewOpcodes.md b/proposals/simd/NewOpcodes.md index fd3646e3f..09845ec1e 100644 --- a/proposals/simd/NewOpcodes.md +++ b/proposals/simd/NewOpcodes.md @@ -77,13 +77,25 @@ | v128.or | 0x50 | | v128.xor | 0x51 | | v128.bitselect | 0x52 | +| v128.any_true | 0x53 | + +| Load Lane Op | opcode | +| ----------------- | ------ | +| v128.load8_lane | 0x54 | +| v128.load16_lane | 0x55 | +| v128.load32_lane | 0x56 | +| v128.load64_lane | 0x57 | +| v128.store8_lane | 0x58 | +| v128.store16_lane | 0x59 | +| v128.store32_lane | 0x5a | +| v128.store64_lane | 0x5b | | i8x16 Op | opcode | i16x8 Op | opcode | i32x4 Op | opcode | i64x2 Op | opcode | | -------------------- | ------ | ------------------------ | ------ | ------------------------ | ------ | ------------------------ | ------ | | i8x16.abs | 0x60 | i16x8.abs | 0x80 | i32x4.abs | 0xa0 | i64x2.abs | 0xc0 | | i8x16.neg | 0x61 | i16x8.neg | 0x81 | i32x4.neg | 0xa1 | i64x2.neg | 0xc1 | -| ------------- | 0x62 | ------------- | 0x82 | ------------- | 0xa2 | ------------- | 0xc2 | -| i8x16.all_true | 0x63 | i16x8.all_true | 0x83 | i32x4.all_true | 0xa3 | (i64x2.all_true) [TBD] | 0xc3 | +| i8x16.popcnt | 0x62 | ------------- | 0x82 | ------------- | 0xa2 | ------------- | 0xc2 | +| i8x16.all_true | 0x63 | i16x8.all_true | 0x83 | i32x4.all_true | 0xa3 | i64x2.all_true | 0xc3 | | i8x16.bitmask | 0x64 | i16x8.bitmask | 0x84 | i32x4.bitmask | 0xa4 | i64x2.bitmask | 0xc4 | | i8x16.narrow_i16x8_s | 0x65 | i16x8.narrow_i32x4_s | 0x85 | ---- narrow ---- | 0xa5 | ------------- | 0xc5 | | i8x16.narrow_i16x8_u | 0x66 | i16x8.narrow_i32x4_u | 0x86 | ---- narrow ---- | 0xa6 | ------------- | 0xc6 | @@ -100,7 +112,7 @@ | i8x16.sub | 0x71 | i16x8.sub | 0x91 | i32x4.sub | 0xb1 | i64x2.sub | 0xd1 | | i8x16.sub_sat_s | 0x72 | i16x8.sub_sat_s | 0x92 | ---- sub_sat ---- | 0xb2 | ------------- | 0xd2 | | i8x16.sub_sat_u | 0x73 | i16x8.sub_sat_u | 0x93 | ---- sub_sat ---- | 0xb3 | ------------- | 0xd3 | -| ------------- | 0x74 | ------------- | 0x94 | ------------- | 0xb4 | ------------- | 0xd4 | +| | 0x74 | ------------- | 0x94 | ------------- | 0xb4 | ------------- | 0xd4 | | ---- mul ---- | 0x75 | i16x8.mul | 0x95 | i32x4.mul | 0xb5 | i64x2.mul | 0xd5 | | i8x16.min_s | 0x76 | i16x8.min_s | 0x96 | i32x4.min_s | 0xb6 | ------------- | 0xd6 | | i8x16.min_u | 0x77 | i16x8.min_u | 0x97 | i32x4.min_u | 0xb7 | ------------- | 0xd7 | @@ -108,6 +120,7 @@ | i8x16.max_u | 0x79 | i16x8.max_u | 0x99 | i32x4.max_u | 0xb9 | ------------- | 0xd9 | | ---------------- | 0x7a | ---------------- | 0x9a | i32x4.dot_i16x8_s | 0xba | ------------- | 0xda | | i8x16.avgr_u | 0x7b | i16x8.avgr_u | 0x9b | ---- avgr_u ---- | 0xbb | ------------- | 0xdb | +| ---------------- | 0x7c | i16x8.q15mulr_sat_s | 0x9c | ---------------- | 0xbc | ------------- | 0xdc | | f32x4 Op | opcode | f64x2 Op | opcode | | --------------- | ------ | --------------- | ------ | @@ -124,9 +137,43 @@ | f32x4.pmin | 0xea | f64x2.pmin | 0xf6 | | f32x4.pmax | 0xeb | f64x2.pmax | 0xf7 | -| Conversion Op | opcode | -| ----------------------- | ------ | -| i32x4.trunc_sat_f32x4_s | 0xf8 | -| i32x4.trunc_sat_f32x4_u | 0xf9 | -| f32x4.convert_i32x4_s | 0xfa | -| f32x4.convert_i32x4_u | 0xfb | +| Conversion Op | opcode | +| ---------------------------- | ------ | +| i32x4.trunc_sat_f32x4_s | 0xf8 | +| i32x4.trunc_sat_f32x4_u | 0xf9 | +| f32x4.convert_i32x4_s | 0xfa | +| f32x4.convert_i32x4_u | 0xfb | +| f64x2.convert_low_i32x4_s | 0xfc | +| f64x2.convert_low_i32x4_u | 0xfd | +| i32x4.trunc_sat_f64x2_s_zero | 0xfe | +| i32x4.trunc_sat_f64x2_u_zero | 0xff | +| f32x4.demote_f64x2_zero | 0x100 | +| f64x2.promote_low_f32x4 | 0x101 | + +| I64x2 Cmp | opcode | +| ---------- | ------ | +| i64x2.eq | 0x102 | +| i64x2.ne | 0x103 | +| i64x2.lt_s | 0x104 | +| i64x2.gt_s | 0x105 | +| i64x2.le_s | 0x106 | +| i64x2.ge_s | 0x107 | + +| Extending Arithmetic Op | opcode | +| ----------------------------- | ------ | +| i16x8.extadd_pairwise_i8x16_s | 0x108 | +| i16x8.extadd_pairwise_i8x16_u | 0x109 | +| i32x4.extadd_pairwise_i16x8_s | 0x10a | +| i32x4.extadd_pairwise_i16x8_u | 0x10b | +| i16x8.extmul_low_i8x16_s | 0x10c | +| i16x8.extmul_high_i8x16_s | 0x10d | +| i16x8.extmul_low_i8x16_u | 0x10e | +| i16x8.extmul_high_i8x16_u | 0x10f | +| i32x4.extmul_low_i16x8_s | 0x110 | +| i32x4.extmul_high_i16x8_s | 0x111 | +| i32x4.extmul_low_i16x8_u | 0x112 | +| i32x4.extmul_high_i16x8_u | 0x113 | +| i64x2.extmul_low_i32x4_s | 0x114 | +| i64x2.extmul_high_i32x4_s | 0x115 | +| i64x2.extmul_low_i32x4_u | 0x116 | +| i64x2.extmul_high_i32x4_u | 0x117 | From 7633dd0dca896ec67c207de1e5c5882d793b90e9 Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Fri, 5 Feb 2021 19:42:59 -0800 Subject: [PATCH 2/6] Add ops from #232 to NewOpcodes.md --- proposals/simd/NewOpcodes.md | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/proposals/simd/NewOpcodes.md b/proposals/simd/NewOpcodes.md index 09845ec1e..59eeba3ae 100644 --- a/proposals/simd/NewOpcodes.md +++ b/proposals/simd/NewOpcodes.md @@ -116,11 +116,22 @@ | ---- mul ---- | 0x75 | i16x8.mul | 0x95 | i32x4.mul | 0xb5 | i64x2.mul | 0xd5 | | i8x16.min_s | 0x76 | i16x8.min_s | 0x96 | i32x4.min_s | 0xb6 | ------------- | 0xd6 | | i8x16.min_u | 0x77 | i16x8.min_u | 0x97 | i32x4.min_u | 0xb7 | ------------- | 0xd7 | -| i8x16.max_s | 0x78 | i16x8.max_s | 0x98 | i32x4.max_s | 0xb8 | ------------- | 0xd8 | -| i8x16.max_u | 0x79 | i16x8.max_u | 0x99 | i32x4.max_u | 0xb9 | ------------- | 0xd9 | -| ---------------- | 0x7a | ---------------- | 0x9a | i32x4.dot_i16x8_s | 0xba | ------------- | 0xda | -| i8x16.avgr_u | 0x7b | i16x8.avgr_u | 0x9b | ---- avgr_u ---- | 0xbb | ------------- | 0xdb | -| ---------------- | 0x7c | i16x8.q15mulr_sat_s | 0x9c | ---------------- | 0xbc | ------------- | 0xdc | +| i8x16.max_s | 0x78 | i16x8.max_s | 0x98 | i32x4.max_s | 0xb8 | ------------- | - | +| i8x16.max_u | 0x79 | i16x8.max_u | 0x99 | i32x4.max_u | 0xb9 | ------------- | - | +| ---------------- | 0x7a | ---------------- | 0x9a | i32x4.dot_i16x8_s | 0xba | ------------- | - | +| i8x16.avgr_u | 0x7b | i16x8.avgr_u | 0x9b | ---- avgr_u ---- | 0xbb | ------------- | - | +| ---------------- | 0x7c | i16x8.q15mulr_sat_s | 0x9c | ---------------- | 0xbc | ------------- | - | + +| Rounding Op | opcode | +| ------------- | ------ | +| f32x4.ceil | 0xd8 | +| f32x4.floor | 0xd9 | +| f32x4.trunc | 0xda | +| f32x4.nearest | 0xdb | +| f64x2.ceil | 0xdc | +| f64x2.floor | 0xdd | +| f64x2.trunc | 0xde | +| f64x2.nearest | 0xdf | | f32x4 Op | opcode | f64x2 Op | opcode | | --------------- | ------ | --------------- | ------ | From 37de1c338021655b3097df655c3100d04a2ed266 Mon Sep 17 00:00:00 2001 From: Thomas Lively <7121787+tlively@users.noreply.github.com> Date: Mon, 8 Feb 2021 09:39:40 -0800 Subject: [PATCH 3/6] Undo spurious change --- proposals/simd/NewOpcodes.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/proposals/simd/NewOpcodes.md b/proposals/simd/NewOpcodes.md index 59eeba3ae..4cff01a16 100644 --- a/proposals/simd/NewOpcodes.md +++ b/proposals/simd/NewOpcodes.md @@ -112,7 +112,7 @@ | i8x16.sub | 0x71 | i16x8.sub | 0x91 | i32x4.sub | 0xb1 | i64x2.sub | 0xd1 | | i8x16.sub_sat_s | 0x72 | i16x8.sub_sat_s | 0x92 | ---- sub_sat ---- | 0xb2 | ------------- | 0xd2 | | i8x16.sub_sat_u | 0x73 | i16x8.sub_sat_u | 0x93 | ---- sub_sat ---- | 0xb3 | ------------- | 0xd3 | -| | 0x74 | ------------- | 0x94 | ------------- | 0xb4 | ------------- | 0xd4 | +| ------------- | 0x74 | ------------- | 0x94 | ------------- | 0xb4 | ------------- | 0xd4 | | ---- mul ---- | 0x75 | i16x8.mul | 0x95 | i32x4.mul | 0xb5 | i64x2.mul | 0xd5 | | i8x16.min_s | 0x76 | i16x8.min_s | 0x96 | i32x4.min_s | 0xb6 | ------------- | 0xd6 | | i8x16.min_u | 0x77 | i16x8.min_u | 0x97 | i32x4.min_u | 0xb7 | ------------- | 0xd7 | From 2cabfd45217181a720a9e41d2386ea6c76b5c624 Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Mon, 8 Feb 2021 16:54:38 -0800 Subject: [PATCH 4/6] Address feedback, compact to 0xff --- proposals/simd/BinarySIMD.md | 70 +++++++++++----------- proposals/simd/NewOpcodes.md | 113 +++++++++++++---------------------- 2 files changed, 75 insertions(+), 108 deletions(-) diff --git a/proposals/simd/BinarySIMD.md b/proposals/simd/BinarySIMD.md index 075fb67f6..492269265 100644 --- a/proposals/simd/BinarySIMD.md +++ b/proposals/simd/BinarySIMD.md @@ -192,14 +192,14 @@ For example, `ImmLaneIdx16` is a byte with values in the range 0-15 (inclusive). | `i64x2.add` | `0xce`| - | | `i64x2.sub` | `0xd1`| - | | `i64x2.mul` | `0xd5`| - | -| `f32x4.ceil` | `0xd8`| - | -| `f32x4.floor` | `0xd9`| - | -| `f32x4.trunc` | `0xda`| - | -| `f32x4.nearest` | `0xdb`| - | -| `f64x2.ceil` | `0xdc`| - | -| `f64x2.floor` | `0xdd`| - | -| `f64x2.trunc` | `0xde`| - | -| `f64x2.nearest` | `0xdf`| - | +| `f32x4.ceil` | `0x67`| - | +| `f32x4.floor` | `0x68`| - | +| `f32x4.trunc` | `0x69`| - | +| `f32x4.nearest` | `0x6a`| - | +| `f64x2.ceil` | `0x74`| - | +| `f64x2.floor` | `0x75`| - | +| `f64x2.trunc` | `0x7a`| - | +| `f64x2.nearest` | `0x94`| - | | `f32x4.abs` | `0xe0`| - | | `f32x4.neg` | `0xe1`| - | | `f32x4.sqrt` | `0xe3`| - | @@ -226,20 +226,20 @@ For example, `ImmLaneIdx16` is a byte with values in the range 0-15 (inclusive). | `i32x4.trunc_sat_f32x4_u` | `0xf9`| - | | `f32x4.convert_i32x4_s` | `0xfa`| - | | `f32x4.convert_i32x4_u` | `0xfb`| - | -| `v128.load32_zero` | `0xfc`| - | -| `v128.load64_zero` | `0xfd`| - | -| `i16x8.extmul_low_i8x16_s` | `0x10c`| - | -| `i16x8.extmul_high_i8x16_s` | `0x10d`| - | -| `i16x8.extmul_low_i8x16_u` | `0x10e`| - | -| `i16x8.extmul_high_i8x16_u` | `0x10f`| - | -| `i32x4.extmul_low_i16x8_s` | `0x110`| - | -| `i32x4.extmul_high_i16x8_s` | `0x111`| - | -| `i32x4.extmul_low_i16x8_u` | `0x112`| - | -| `i32x4.extmul_high_i16x8_u` | `0x113`| - | -| `i64x2.extmul_low_i32x4_s` | `0x114`| - | -| `i64x2.extmul_high_i32x4_s` | `0x115`| - | -| `i64x2.extmul_low_i32x4_u` | `0x116`| - | -| `i64x2.extmul_high_i32x4_u` | `0x117`| - | +| `v128.load32_zero` | `0x5c`| - | +| `v128.load64_zero` | `0x5d`| - | +| `i16x8.extmul_low_i8x16_s` | `0x9c`| - | +| `i16x8.extmul_high_i8x16_s` | `0x9d`| - | +| `i16x8.extmul_low_i8x16_u` | `0x9e`| - | +| `i16x8.extmul_high_i8x16_u` | `0x9f`| - | +| `i32x4.extmul_low_i16x8_s` | `0xbc`| - | +| `i32x4.extmul_high_i16x8_s` | `0xbd`| - | +| `i32x4.extmul_low_i16x8_u` | `0xbe`| - | +| `i32x4.extmul_high_i16x8_u` | `0xbf`| - | +| `i64x2.extmul_low_i32x4_s` | `0xdc`| - | +| `i64x2.extmul_high_i32x4_s` | `0xdd`| - | +| `i64x2.extmul_low_i32x4_u` | `0xde`| - | +| `i64x2.extmul_high_i32x4_u` | `0xdf`| - | | `i16x8.q15mulr_sat_s` | `0x9c`| - | | `v128.any_true` | `0x53`| - | | `v128.load8_lane` | `0x54`| m:memarg, i:ImmLaneIdx16 | @@ -250,21 +250,21 @@ For example, `ImmLaneIdx16` is a byte with values in the range 0-15 (inclusive). | `v128.store16_lane` | `0x59`| m:memarg, i:ImmLaneIdx8 | | `v128.store32_lane` | `0x5a`| m:memarg, i:ImmLaneIdx4 | | `v128.store64_lane` | `0x5b`| m:memarg, i:ImmLaneIdx2 | -| `i64x2.eq` | `0x102`| - | -| `i64x2.ne` | `0x103`| - | -| `i64x2.lt_s` | `0x104`| - | -| `i64x2.gt_s` | `0x105`| - | -| `i64x2.le_s` | `0x106`| - | -| `i64x2.ge_s` | `0x107`| - | +| `i64x2.eq` | `0xd6`| - | +| `i64x2.ne` | `0xd7`| - | +| `i64x2.lt_s` | `0xd8`| - | +| `i64x2.gt_s` | `0xd9`| - | +| `i64x2.le_s` | `0xda`| - | +| `i64x2.ge_s` | `0xdb`| - | | `i64x2.all_true` | `0xc3`| - | | `f64x2.convert_low_i32x4_s` | `0xfc`| - | | `f64x2.convert_low_i32x4_u` | `0xfd`| - | | `i32x4.trunc_sat_f64x2_s_zero` | `0xfe`| - | | `i32x4.trunc_sat_f64x2_u_zero` | `0xff`| - | -| `f32x4.demote_f64x2_zero` | `0x100`| - | -| `f64x2.promote_low_f32x4` | `0x101`| - | -| `i8x16.popcnt` | `0x74`| - | -| `i16x8.extadd_pairwise_i8x16_s` | `0x108`| - | -| `i16x8.extadd_pairwise_i8x16_u` | `0x109`| - | -| `i32x4.extadd_pairwise_i16x8_s` | `0x10a`| - | -| `i32x4.extadd_pairwise_i16x8_u` | `0x10b`| - | +| `f32x4.demote_f64x2_zero` | `0x5e`| - | +| `f64x2.promote_low_f32x4` | `0x5f`| - | +| `i8x16.popcnt` | `0x62`| - | +| `i16x8.extadd_pairwise_i8x16_s` | `0x7c`| - | +| `i16x8.extadd_pairwise_i8x16_u` | `0x7d`| - | +| `i32x4.extadd_pairwise_i16x8_s` | `0x7e`| - | +| `i32x4.extadd_pairwise_i16x8_u` | `0x7f`| - | diff --git a/proposals/simd/NewOpcodes.md b/proposals/simd/NewOpcodes.md index 4cff01a16..8e3e6c307 100644 --- a/proposals/simd/NewOpcodes.md +++ b/proposals/simd/NewOpcodes.md @@ -12,8 +12,6 @@ | v128.load32_splat | 0x09 | | v128.load64_splat | 0x0a | | v128.store | 0x0b | -| v128.load32_zero | 0xfc | -| v128.load64_zero | 0xfd | | Basic operation | opcode | | ----------------| ------ | @@ -89,49 +87,48 @@ | v128.store16_lane | 0x59 | | v128.store32_lane | 0x5a | | v128.store64_lane | 0x5b | +| v128.load32_zero | 0x5c | +| v128.load64_zero | 0x5d | -| i8x16 Op | opcode | i16x8 Op | opcode | i32x4 Op | opcode | i64x2 Op | opcode | -| -------------------- | ------ | ------------------------ | ------ | ------------------------ | ------ | ------------------------ | ------ | -| i8x16.abs | 0x60 | i16x8.abs | 0x80 | i32x4.abs | 0xa0 | i64x2.abs | 0xc0 | -| i8x16.neg | 0x61 | i16x8.neg | 0x81 | i32x4.neg | 0xa1 | i64x2.neg | 0xc1 | -| i8x16.popcnt | 0x62 | ------------- | 0x82 | ------------- | 0xa2 | ------------- | 0xc2 | -| i8x16.all_true | 0x63 | i16x8.all_true | 0x83 | i32x4.all_true | 0xa3 | i64x2.all_true | 0xc3 | -| i8x16.bitmask | 0x64 | i16x8.bitmask | 0x84 | i32x4.bitmask | 0xa4 | i64x2.bitmask | 0xc4 | -| i8x16.narrow_i16x8_s | 0x65 | i16x8.narrow_i32x4_s | 0x85 | ---- narrow ---- | 0xa5 | ------------- | 0xc5 | -| i8x16.narrow_i16x8_u | 0x66 | i16x8.narrow_i32x4_u | 0x86 | ---- narrow ---- | 0xa6 | ------------- | 0xc6 | -| ---- widen ---- | 0x67 | i16x8.widen_low_i8x16_s | 0x87 | i32x4.widen_low_i16x8_s | 0xa7 | i64x2.widen_low_i32x4_s | 0xc7 | -| ---- widen ---- | 0x68 | i16x8.widen_high_i8x16_s | 0x88 | i32x4.widen_high_i16x8_s | 0xa8 | i64x2.widen_high_i32x4_s | 0xc8 | -| ---- widen ---- | 0x69 | i16x8.widen_low_i8x16_u | 0x89 | i32x4.widen_low_i16x8_u | 0xa9 | i64x2.widen_low_i32x4_u | 0xc9 | -| ---- widen ---- | 0x6a | i16x8.widen_high_i8x16_u | 0x8a | i32x4.widen_high_i16x8_u | 0xaa | i64x2.widen_high_i32x4_u | 0xca | -| i8x16.shl | 0x6b | i16x8.shl | 0x8b | i32x4.shl | 0xab | i64x2.shl | 0xcb | -| i8x16.shr_s | 0x6c | i16x8.shr_s | 0x8c | i32x4.shr_s | 0xac | i64x2.shr_s | 0xcc | -| i8x16.shr_u | 0x6d | i16x8.shr_u | 0x8d | i32x4.shr_u | 0xad | i64x2.shr_u | 0xcd | -| i8x16.add | 0x6e | i16x8.add | 0x8e | i32x4.add | 0xae | i64x2.add | 0xce | -| i8x16.add_sat_s | 0x6f | i16x8.add_sat_s | 0x8f | ---- add_sat ---- | 0xaf | ------------- | 0xcf | -| i8x16.add_sat_u | 0x70 | i16x8.add_sat_u | 0x90 | ---- add_sat ---- | 0xb0 | ------------- | 0xd0 | -| i8x16.sub | 0x71 | i16x8.sub | 0x91 | i32x4.sub | 0xb1 | i64x2.sub | 0xd1 | -| i8x16.sub_sat_s | 0x72 | i16x8.sub_sat_s | 0x92 | ---- sub_sat ---- | 0xb2 | ------------- | 0xd2 | -| i8x16.sub_sat_u | 0x73 | i16x8.sub_sat_u | 0x93 | ---- sub_sat ---- | 0xb3 | ------------- | 0xd3 | -| ------------- | 0x74 | ------------- | 0x94 | ------------- | 0xb4 | ------------- | 0xd4 | -| ---- mul ---- | 0x75 | i16x8.mul | 0x95 | i32x4.mul | 0xb5 | i64x2.mul | 0xd5 | -| i8x16.min_s | 0x76 | i16x8.min_s | 0x96 | i32x4.min_s | 0xb6 | ------------- | 0xd6 | -| i8x16.min_u | 0x77 | i16x8.min_u | 0x97 | i32x4.min_u | 0xb7 | ------------- | 0xd7 | -| i8x16.max_s | 0x78 | i16x8.max_s | 0x98 | i32x4.max_s | 0xb8 | ------------- | - | -| i8x16.max_u | 0x79 | i16x8.max_u | 0x99 | i32x4.max_u | 0xb9 | ------------- | - | -| ---------------- | 0x7a | ---------------- | 0x9a | i32x4.dot_i16x8_s | 0xba | ------------- | - | -| i8x16.avgr_u | 0x7b | i16x8.avgr_u | 0x9b | ---- avgr_u ---- | 0xbb | ------------- | - | -| ---------------- | 0x7c | i16x8.q15mulr_sat_s | 0x9c | ---------------- | 0xbc | ------------- | - | +| Float conversion | opcode | +| ----------------------- | ------ | +| f32x4.demote_f64x2_zero | 0x5e | +| f64x2.promote_low_f32x4 | 0x5f | -| Rounding Op | opcode | -| ------------- | ------ | -| f32x4.ceil | 0xd8 | -| f32x4.floor | 0xd9 | -| f32x4.trunc | 0xda | -| f32x4.nearest | 0xdb | -| f64x2.ceil | 0xdc | -| f64x2.floor | 0xdd | -| f64x2.trunc | 0xde | -| f64x2.nearest | 0xdf | +| i8x16 Op | opcode | i16x8 Op | opcode | i32x4 Op | opcode | i64x2 Op | opcode | +| ----------------------------- | ------ | ------------------------- | ------ | ------------------------- | ------ | ------------------------- | ------ | +| i8x16.abs | 0x60 | i16x8.abs | 0x80 | i32x4.abs | 0xa0 | i64x2.abs | 0xc0 | +| i8x16.neg | 0x61 | i16x8.neg | 0x81 | i32x4.neg | 0xa1 | i64x2.neg | 0xc1 | +| i8x16.popcnt | 0x62 | i16x8.q15mulr_sat_s | 0x82 | | 0xa2 | ------------- | 0xc2 | +| i8x16.all_true | 0x63 | i16x8.all_true | 0x83 | i32x4.all_true | 0xa3 | i64x2.all_true | 0xc3 | +| i8x16.bitmask | 0x64 | i16x8.bitmask | 0x84 | i32x4.bitmask | 0xa4 | i64x2.bitmask | 0xc4 | +| i8x16.narrow_i16x8_s | 0x65 | i16x8.narrow_i32x4_s | 0x85 | ---- narrow ---- | 0xa5 | ------------- | 0xc5 | +| i8x16.narrow_i16x8_u | 0x66 | i16x8.narrow_i32x4_u | 0x86 | ---- narrow ---- | 0xa6 | ------------- | 0xc6 | +| f32x4.ceil | 0x67 | i16x8.widen_low_i8x16_s | 0x87 | i32x4.widen_low_i16x8_s | 0xa7 | i64x2.widen_low_i32x4_s | 0xc7 | +| f32x4.floor | 0x68 | i16x8.widen_high_i8x16_s | 0x88 | i32x4.widen_high_i16x8_s | 0xa8 | i64x2.widen_high_i32x4_s | 0xc8 | +| f32x4.trunc | 0x69 | i16x8.widen_low_i8x16_u | 0x89 | i32x4.widen_low_i16x8_u | 0xa9 | i64x2.widen_low_i32x4_u | 0xc9 | +| f32x4.nearest | 0x6a | i16x8.widen_high_i8x16_u | 0x8a | i32x4.widen_high_i16x8_u | 0xaa | i64x2.widen_high_i32x4_u | 0xca | +| i8x16.shl | 0x6b | i16x8.shl | 0x8b | i32x4.shl | 0xab | i64x2.shl | 0xcb | +| i8x16.shr_s | 0x6c | i16x8.shr_s | 0x8c | i32x4.shr_s | 0xac | i64x2.shr_s | 0xcc | +| i8x16.shr_u | 0x6d | i16x8.shr_u | 0x8d | i32x4.shr_u | 0xad | i64x2.shr_u | 0xcd | +| i8x16.add | 0x6e | i16x8.add | 0x8e | i32x4.add | 0xae | i64x2.add | 0xce | +| i8x16.add_sat_s | 0x6f | i16x8.add_sat_s | 0x8f | ---- add_sat ---- | 0xaf | ------------- | 0xcf | +| i8x16.add_sat_u | 0x70 | i16x8.add_sat_u | 0x90 | ---- add_sat ---- | 0xb0 | ------------- | 0xd0 | +| i8x16.sub | 0x71 | i16x8.sub | 0x91 | i32x4.sub | 0xb1 | i64x2.sub | 0xd1 | +| i8x16.sub_sat_s | 0x72 | i16x8.sub_sat_s | 0x92 | ---- sub_sat ---- | 0xb2 | ------------- | 0xd2 | +| i8x16.sub_sat_u | 0x73 | i16x8.sub_sat_u | 0x93 | ---- sub_sat ---- | 0xb3 | ------------- | 0xd3 | +| f64x2.ceil | 0x74 | f64x2.nearest | 0x94 | ------------- | 0xb4 | ------------- | 0xd4 | +| f64x2.floor | 0x75 | i16x8.mul | 0x95 | i32x4.mul | 0xb5 | i64x2.mul | 0xd5 | +| i8x16.min_s | 0x76 | i16x8.min_s | 0x96 | i32x4.min_s | 0xb6 | i64x2.eq | 0xd6 | +| i8x16.min_u | 0x77 | i16x8.min_u | 0x97 | i32x4.min_u | 0xb7 | i64x2.ne | 0xd7 | +| i8x16.max_s | 0x78 | i16x8.max_s | 0x98 | i32x4.max_s | 0xb8 | i64x2.lt_s | 0xd8 | +| i8x16.max_u | 0x79 | i16x8.max_u | 0x99 | i32x4.max_u | 0xb9 | i64x2.gt_s | 0xd9 | +| f64x2.trunc | 0x7a | | 0x9a | i32x4.dot_i16x8_s | 0xba | i64x2.le_s | 0xda | +| i8x16.avgr_u | 0x7b | i16x8.avgr_u | 0x9b | ---- avgr_u ---- | 0xbb | i64x2.ge_s | 0xdb | +| i16x8.extadd_pairwise_i8x16_s | 0x7c | i16x8.extmul_low_i8x16_s | 0x9c | i32x4.extmul_low_i16x8_s | 0xbc | i64x2.extmul_low_i32x4_s | 0xdc | +| i16x8.extadd_pairwise_i8x16_u | 0x7d | i16x8.extmul_high_i8x16_s | 0x9d | i32x4.extmul_high_i16x8_s | 0xbd | i64x2.extmul_high_i32x4_s | 0xdd | +| i32x4.extadd_pairwise_i16x8_s | 0x7e | i16x8.extmul_low_i8x16_u | 0x9e | i32x4.extmul_low_i16x8_u | 0xbe | i64x2.extmul_low_i32x4_u | 0xde | +| i32x4.extadd_pairwise_i16x8_u | 0x7f | i16x8.extmul_high_i8x16_u | 0x9f | i32x4.extmul_high_i16x8_u | 0xbf | i64x2.extmul_high_i32x4_u | 0xdf | | f32x4 Op | opcode | f64x2 Op | opcode | | --------------- | ------ | --------------- | ------ | @@ -158,33 +155,3 @@ | f64x2.convert_low_i32x4_u | 0xfd | | i32x4.trunc_sat_f64x2_s_zero | 0xfe | | i32x4.trunc_sat_f64x2_u_zero | 0xff | -| f32x4.demote_f64x2_zero | 0x100 | -| f64x2.promote_low_f32x4 | 0x101 | - -| I64x2 Cmp | opcode | -| ---------- | ------ | -| i64x2.eq | 0x102 | -| i64x2.ne | 0x103 | -| i64x2.lt_s | 0x104 | -| i64x2.gt_s | 0x105 | -| i64x2.le_s | 0x106 | -| i64x2.ge_s | 0x107 | - -| Extending Arithmetic Op | opcode | -| ----------------------------- | ------ | -| i16x8.extadd_pairwise_i8x16_s | 0x108 | -| i16x8.extadd_pairwise_i8x16_u | 0x109 | -| i32x4.extadd_pairwise_i16x8_s | 0x10a | -| i32x4.extadd_pairwise_i16x8_u | 0x10b | -| i16x8.extmul_low_i8x16_s | 0x10c | -| i16x8.extmul_high_i8x16_s | 0x10d | -| i16x8.extmul_low_i8x16_u | 0x10e | -| i16x8.extmul_high_i8x16_u | 0x10f | -| i32x4.extmul_low_i16x8_s | 0x110 | -| i32x4.extmul_high_i16x8_s | 0x111 | -| i32x4.extmul_low_i16x8_u | 0x112 | -| i32x4.extmul_high_i16x8_u | 0x113 | -| i64x2.extmul_low_i32x4_s | 0x114 | -| i64x2.extmul_high_i32x4_s | 0x115 | -| i64x2.extmul_low_i32x4_u | 0x116 | -| i64x2.extmul_high_i32x4_u | 0x117 | From 01b5f011a6f15d6410843443518c0169449edc68 Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Mon, 8 Feb 2021 17:31:12 -0800 Subject: [PATCH 5/6] Swap truc_sat_zero and convert_low --- proposals/simd/BinarySIMD.md | 8 ++++---- proposals/simd/NewOpcodes.md | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/proposals/simd/BinarySIMD.md b/proposals/simd/BinarySIMD.md index 492269265..f916c78cd 100644 --- a/proposals/simd/BinarySIMD.md +++ b/proposals/simd/BinarySIMD.md @@ -257,10 +257,10 @@ For example, `ImmLaneIdx16` is a byte with values in the range 0-15 (inclusive). | `i64x2.le_s` | `0xda`| - | | `i64x2.ge_s` | `0xdb`| - | | `i64x2.all_true` | `0xc3`| - | -| `f64x2.convert_low_i32x4_s` | `0xfc`| - | -| `f64x2.convert_low_i32x4_u` | `0xfd`| - | -| `i32x4.trunc_sat_f64x2_s_zero` | `0xfe`| - | -| `i32x4.trunc_sat_f64x2_u_zero` | `0xff`| - | +| `f64x2.convert_low_i32x4_s` | `0xfe`| - | +| `f64x2.convert_low_i32x4_u` | `0xff`| - | +| `i32x4.trunc_sat_f64x2_s_zero` | `0xfc`| - | +| `i32x4.trunc_sat_f64x2_u_zero` | `0xfd`| - | | `f32x4.demote_f64x2_zero` | `0x5e`| - | | `f64x2.promote_low_f32x4` | `0x5f`| - | | `i8x16.popcnt` | `0x62`| - | diff --git a/proposals/simd/NewOpcodes.md b/proposals/simd/NewOpcodes.md index 8e3e6c307..a423374e9 100644 --- a/proposals/simd/NewOpcodes.md +++ b/proposals/simd/NewOpcodes.md @@ -151,7 +151,7 @@ | i32x4.trunc_sat_f32x4_u | 0xf9 | | f32x4.convert_i32x4_s | 0xfa | | f32x4.convert_i32x4_u | 0xfb | -| f64x2.convert_low_i32x4_s | 0xfc | -| f64x2.convert_low_i32x4_u | 0xfd | -| i32x4.trunc_sat_f64x2_s_zero | 0xfe | -| i32x4.trunc_sat_f64x2_u_zero | 0xff | +| i32x4.trunc_sat_f64x2_s_zero | 0xfc | +| i32x4.trunc_sat_f64x2_u_zero | 0xfd | +| f64x2.convert_low_i32x4_s | 0xfe | +| f64x2.convert_low_i32x4_u | 0xff | From bbb3b5f80b004d551a3008192c062504a87dbf3b Mon Sep 17 00:00:00 2001 From: Thomas Lively <7121787+tlively@users.noreply.github.com> Date: Tue, 9 Feb 2021 13:17:56 -0800 Subject: [PATCH 6/6] Fix q15 mul opcode --- proposals/simd/BinarySIMD.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/proposals/simd/BinarySIMD.md b/proposals/simd/BinarySIMD.md index f916c78cd..196f462f3 100644 --- a/proposals/simd/BinarySIMD.md +++ b/proposals/simd/BinarySIMD.md @@ -240,7 +240,7 @@ For example, `ImmLaneIdx16` is a byte with values in the range 0-15 (inclusive). | `i64x2.extmul_high_i32x4_s` | `0xdd`| - | | `i64x2.extmul_low_i32x4_u` | `0xde`| - | | `i64x2.extmul_high_i32x4_u` | `0xdf`| - | -| `i16x8.q15mulr_sat_s` | `0x9c`| - | +| `i16x8.q15mulr_sat_s` | `0x82`| - | | `v128.any_true` | `0x53`| - | | `v128.load8_lane` | `0x54`| m:memarg, i:ImmLaneIdx16 | | `v128.load16_lane` | `0x55`| m:memarg, i:ImmLaneIdx8 |