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I have never been able to find a routing solution for this example (as well as many other examples), although it is a small design.
I have attached the Verilog design file, the architecture file, and the log of nextpnr (I interrupted it because it was taking too long).
I have never been able to find a routing solution for this example (as well as many other examples), although it is a small design.
I have attached the Verilog design file, the architecture file, and the log of nextpnr (I interrupted it because it was taking too long).
ca_prng_Design.zip
I'd appreciate any help. Thanks.
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