From 767da07ca24239c1c60c2601000a37b84f16df7d Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 30 Sep 2024 16:35:59 +0200
Subject: [PATCH] rtlil: revert Const ordering to "spreadsheet column order"

---
 kernel/rtlil.cc | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index a3801116e13..bc48c88c853 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -313,12 +313,14 @@ RTLIL::Const::~Const() {
 
 bool RTLIL::Const::operator<(const RTLIL::Const &other) const
 {
-	// Compare common prefix
-	for (int i = 0; i < size() && i < other.size(); i++)
+	if (size() < other.size())
+		return size() < other.size();
+
+	for (int i = 0; i < size(); i++)
 		if ((*this)[i] != other[i])
 			return (*this)[i] < other[i];
 
-	return size() < other.size();
+	return false;
 }
 
 bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
@@ -340,7 +342,6 @@ bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
 
 std::vector<RTLIL::State>& RTLIL::Const::bits()
 {
-	log_assert(is_bits());
 	bitvectorize();
 	return get_bits();
 }
@@ -3913,7 +3914,7 @@ RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
 	wire = bit.wire;
 	offset = 0;
 	if (wire == NULL)
-		data = RTLIL::Const(bit.data).to_bits();
+		data = {bit.data};
 	else
 		offset = bit.offset;
 	width = 1;