How to generate the BLIF file.

[JarvisPei]

Hello. I am trying to generate the BLIF files as in this repo's Benchmarks folder. I take the original verilog file in VTR repository and use yosys and ABC to generate the BLIF file. However, I find that the AIG nodes number are much more larger then that in your benchmarks. Therefore, could you please tell me how do you generate the BLIF files? Please help me to solve it, thanks!

[ycunxi]

there two sets of DSP benchmark, one is hard-logic and the other is soft-logic. you might want to give a try on the other set you have not tried.

[sun123-cmd]

Hello. I am trying to generate the BLIF files as in this repo's Benchmarks folder. I take the original verilog file in VTR repository and use yosys and ABC to generate the BLIF file. However, I find that the AIG nodes number are much more larger then that in your benchmarks. Therefore, could you please tell me how do you generate the BLIF files? Please help me to solve it, thanks!

Hello!
You can try the following script with yosys:

This is script of tool.ys:

read_verilog adder.v
synth -top adder
write_blif adder.blif

And you can simply get .blif file with running yosys tool.ts