-
Notifications
You must be signed in to change notification settings - Fork 24
/
sdram.txt
200 lines (194 loc) · 6.42 KB
/
sdram.txt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
################################################################################
##
## Filename: sdram.txt
##
## Project: OpenArty, an entirely open SoC based upon the Arty platform
##
## Purpose: To describe how to provide access to an SDRAM controller
## from the Wishbone bus, where such SDRAM controller uses a
## different clock from the Wishbone bus itself.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
##
## Copyright (C) 2017-2020, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
##
@PREFIX=sdram
@DEVID=SDRAM
@ACCESS=@$(DEVID)_ACCESS
@DEPENDS=ALLCLOCKS_PRESENT
## LGMEMSZ is the size of the SDRAM in bytes, 28 => 256MB, or 128M 16-bit words
@$LGMEMSZ=28
@LGMEMSZ.FORMAT=%d
@$UNUSED=2
@$NADDR=(1<<(LGMEMSZ-(@$(UNUSED))))
@$NBYTES=(1<<(@$LGMEMSZ))
@NBYTES.FORMAT=0x%08x
@$MADDR= @$(REGBASE)
@MADDR.FORMAT=0x%08x
@SLAVE.TYPE=MEMORY
@SLAVE.BUS=wb
@CLOCK.NAME=clk
# @CLOCK.FREQUENCY = 81250000
#
# AutoFPGA wants a clock cycle duration that's visible by four. Not sure
# if I should correct that here, or in AutoFPGA
@CLOCK.FREQUENCY = 81247960
@BUS=wb
@ERROR.WIRE=@$(PREFIX)_err
# 8-bit byte accesses
@LD.PERM=wx
@TOP.PORTLIST=
// SDRAM I/O port wires
ddr3_reset_n, ddr3_cke, ddr3_ck_p, ddr3_ck_n,
ddr3_cs_n, ddr3_ras_n, ddr3_cas_n, ddr3_we_n,
ddr3_dqs_p, ddr3_dqs_n,
ddr3_addr, ddr3_ba,
ddr3_dq, ddr3_dm, ddr3_odt
@TOP.IODECL=
// I/O declarations for the DDR3 SDRAM
output wire ddr3_reset_n;
output wire [0:0] ddr3_cke;
output wire [0:0] ddr3_ck_p, ddr3_ck_n;
output wire [0:0] ddr3_cs_n;
output wire ddr3_ras_n, ddr3_cas_n, ddr3_we_n;
output wire [2:0] ddr3_ba;
output wire [13:0] ddr3_addr;
output wire [0:0] ddr3_odt;
output wire [1:0] ddr3_dm;
inout wire [1:0] ddr3_dqs_p, ddr3_dqs_n;
inout wire [15:0] ddr3_dq;
@TOP.DEFNS=
// Wires necessary to run the SDRAM
//
wire @$(PREFIX)_cyc, @$(PREFIX)_stb, @$(PREFIX)_we,
@$(PREFIX)_stall, @$(PREFIX)_ack, @$(PREFIX)_err;
wire [(@$(BUS.AWID)-1):0] @$(PREFIX)_addr;
wire [(@$(BUS.WIDTH)-1):0] @$(PREFIX)_wdata,
@$(PREFIX)_rdata;
wire [(@$(BUS.WIDTH)/8-1):0] @$(PREFIX)_sel;
@TOP.MAIN=
// The SDRAM interface to an toplevel AXI4 module
//
@$(PREFIX)_cyc, @$(PREFIX)_stb, @$(PREFIX)_we,
@$(PREFIX)_addr, @$(PREFIX)_wdata, @$(PREFIX)_sel,
@$(PREFIX)_stall, @$(PREFIX)_ack, @$(PREFIX)_rdata,
@$(PREFIX)_err
@TOP.INSERT=
wire [31:0] @$(PREFIX)_debug;
migsdram #(.AXIDWIDTH(1), .WBDATAWIDTH(@$(BUS.WIDTH)),
.DDRWIDTH(16),
.RAMABITS(@$(LGMEMSZ)))
@$(PREFIX)i(
.i_clk(mem_clk_nobuf),
.i_clk_200mhz(mem_clk_200mhz_nobuf),
.o_sys_clk(s_clk),
.i_rst(pwr_reset),
.o_sys_reset(s_reset),
//
.i_wb_cyc(@$(PREFIX)_cyc), .i_wb_stb(@$(PREFIX)_stb),
.i_wb_we(@$(PREFIX)_we), .i_wb_addr(@$(PREFIX)_addr),
.i_wb_data(@$(PREFIX)_wdata), .i_wb_sel(@$(PREFIX)_sel),
.o_wb_stall(@$(PREFIX)_stall), .o_wb_ack(@$(PREFIX)_ack),
.o_wb_data(@$(PREFIX)_rdata), .o_wb_err(@$(PREFIX)_err),
//
.o_ddr_ck_p(ddr3_ck_p), .o_ddr_ck_n(ddr3_ck_n),
.o_ddr_reset_n(ddr3_reset_n), .o_ddr_cke(ddr3_cke),
.o_ddr_cs_n(ddr3_cs_n), .o_ddr_ras_n(ddr3_ras_n),
.o_ddr_cas_n(ddr3_cas_n), .o_ddr_we_n(ddr3_we_n),
.o_ddr_ba(ddr3_ba), .o_ddr_addr(ddr3_addr),
.o_ddr_odt(ddr3_odt), .o_ddr_dm(ddr3_dm),
.io_ddr_dqs_p(ddr3_dqs_p), .io_ddr_dqs_n(ddr3_dqs_n),
.io_ddr_data(ddr3_dq)
);
@MAIN.PORTLIST=
// SDRAM ports
o_@$(PREFIX)_cyc, o_@$(PREFIX)_stb, o_@$(PREFIX)_we,
o_@$(PREFIX)_addr, o_@$(PREFIX)_data, o_@$(PREFIX)_sel,
i_@$(PREFIX)_stall, i_@$(PREFIX)_ack, i_@$(PREFIX)_data,
i_@$(PREFIX)_err
@MAIN.IODECL=
// SDRAM I/O declarations
output wire o_@$(PREFIX)_cyc,
o_@$(PREFIX)_stb, o_@$(PREFIX)_we;
output wire [(@$(BUS.AWID)-1):0] o_@$(PREFIX)_addr;
output wire [(@$(BUS.WIDTH)-1):0] o_@$(PREFIX)_data;
output wire [(@$(BUS.WIDTH)/8)-1:0] o_@$(PREFIX)_sel;
//
input wire i_@$(PREFIX)_ack;
input wire i_@$(PREFIX)_stall;
input wire [(@$(BUS.WIDTH)-1):0] i_@$(PREFIX)_data;
// Verilator lint_off UNUSED
input wire i_@$(PREFIX)_err;
// Verilator lint_on UNUSED
@MAIN.INSERT=
assign o_@$(PREFIX)_cyc = @$(SLAVE.PREFIX)_cyc;
assign o_@$(PREFIX)_stb =(@$(SLAVE.PREFIX)_stb);
assign o_@$(PREFIX)_we = @$(SLAVE.PREFIX)_we;
assign o_@$(PREFIX)_addr = @$(SLAVE.PREFIX)_addr[@$(BUS.AWID)-1:0];
assign o_@$(PREFIX)_data = @$(SLAVE.PREFIX)_data;
assign o_@$(PREFIX)_sel = @$(SLAVE.PREFIX)_sel;
assign @$(SLAVE.PREFIX)_ack = i_@$(PREFIX)_ack;
assign @$(SLAVE.PREFIX)_stall = i_@$(PREFIX)_stall;
assign @$(SLAVE.PREFIX)_idata = i_@$(PREFIX)_data;
assign @$(PREFIX)_err = i_@$(PREFIX)_err;
assign @$(SLAVE.PREFIX)_err = @$(PREFIX)_err;
@REGS.N=1
@REGS.0= 0 R_@$(DEVID) @$(DEVID)
@REGDEFS.H.DEFNS=
#define @$(DEVID)BASE @$[0x%08x](REGBASE)
#define @$(DEVID)LEN @$(NBYTES)
@BDEF.OSDEF=_BOARD_HAS_@$(DEVID)
@BDEF.OSVAL=extern char _@$(PREFIX)[@$NBYTES];
@LD.PERM=wx
@SIM.INCLUDE=
#include "memsim.h"
@SIM.DEFNS=
#ifdef @$(ACCESS)
MEMSIM *m_@$(PREFIX);
#endif // @$(ACCESS)
@SIM.INIT=
#ifdef @$(ACCESS)
m_@$(PREFIX) = new MEMSIM(@$(NBYTES));
#endif // @$(ACCESS)
@SIM.CLOCK=@$(SLAVE.BUS.CLOCK.NAME)
@SIM.TICK=
#ifdef @$(ACCESS)
// Simulate the SDRAM
(*m_@$(PREFIX))(m_core->o_@$(PREFIX)_cyc,
m_core->o_@$(PREFIX)_stb,
m_core->o_@$(PREFIX)_we,
m_core->o_@$(PREFIX)_addr,
&m_core->o_@$(PREFIX)_data,
m_core->o_@$(PREFIX)_sel,
m_core->i_@$(PREFIX)_stall,
m_core->i_@$(PREFIX)_ack,
&m_core->i_@$(PREFIX)_data);
m_core->i_@$(PREFIX)_err = 0;
#endif // @$(ACCESS)
@SIM.LOAD=
m_@$(PREFIX)->load(start, &buf[offset], wlen);