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regdefs.cpp
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regdefs.cpp
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////////////////////////////////////////////////////////////////////////////////
//
// Filename: ./regdefs.cpp
//
// Project: OpenArty, an entirely open SoC based upon the Arty platform
//
// DO NOT EDIT THIS FILE!
// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
// DO NOT EDIT THIS FILE!
//
// CmdLine: autofpga autofpga -d -o . allclocks.txt global.txt icape.txt version.txt buserr.txt pic.txt pwrcount.txt spio.txt clrspio.txt rtcgps.txt rtcdate.txt wbuconsole.txt bkram.txt spansion.txt sdram.txt zipmaster.txt mdio.txt enet.txt gps.txt wboledrgb.txt mem_flash_bkram.txt mem_bkram_only.txt mem_sdram_bkram.txt
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2017-2020, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#include <stdio.h>
#include <stdlib.h>
#include <strings.h>
#include <ctype.h>
#include "regdefs.h"
const REGNAME raw_bregs[] = {
{ R_FLASHCFG , "FLASHCFG" },
{ R_FLASHCFG , "QSPIC" },
{ R_GPSU_SETUP , "GPSSETUP" },
{ R_GPSU_FIFO , "GPSFIFO" },
{ R_GPSU_UARTRX , "GPSRX" },
{ R_GPSU_UARTTX , "GPSTX" },
{ R_CONSOLE_FIFO , "UFIFO" },
{ R_CONSOLE_UARTRX, "RX" },
{ R_CONSOLE_UARTTX, "TX" },
{ R_CFG_CRC , "FPGACRC" },
{ R_CFG_FAR , "FPGAFAR" },
{ R_CFG_FDRI , "FPGAFDRI" },
{ R_CFG_FDRO , "FPGAFDRO" },
{ R_CFG_CMD , "FPGACMD" },
{ R_CFG_CTL0 , "FPGACTL0" },
{ R_CFG_MASK , "FPGAMASK" },
{ R_CFG_STAT , "FPGASTAT" },
{ R_CFG_LOUT , "FPGALOUT" },
{ R_CFG_COR0 , "FPGACOR0" },
{ R_CFG_MFWR , "FPGAMFWR" },
{ R_CFG_CBC , "FPGACBC" },
{ R_CFG_IDCODE , "FPGAIDCODE" },
{ R_CFG_AXSS , "FPGAAXSS" },
{ R_CFG_COR1 , "FPGACOR1" },
{ R_CFG_WBSTAR , "WBSTAR" },
{ R_CFG_TIMER , "CFGTIMER" },
{ R_CFG_BOOTSTS , "BOOTSTS" },
{ R_CFG_CTL1 , "FPGACTL1" },
{ R_CFG_BSPI , "FPGABSPI" },
{ R_MDIO_BMCR , "BMCR" },
{ R_MDIO_BMSR , "BMSR" },
{ R_MDIO_PHYIDR1 , "PHYIDR1" },
{ R_MDIO_PHYIDR2 , "PHYIDR2" },
{ R_MDIO_ANAR , "ANAR" },
{ R_MDIO_ANLPAR , "ANLPAR" },
{ R_MDIO_ANER , "ANER" },
{ R_MDIO_ANNPTR , "ANNPTR" },
{ R_MDIO_PHYSTS , "PHYSYTS" },
{ R_MDIO_FCSCR , "FCSCR" },
{ R_MDIO_RECR , "RECR" },
{ R_MDIO_PCSR , "PCSR" },
{ R_MDIO_RBR , "RBR" },
{ R_MDIO_LEDCR , "LEDCR" },
{ R_MDIO_PHYCR , "PHYCR" },
{ R_MDIO_BTSCR , "BTSCR" },
{ R_MDIO_CDCTRL , "CDCTRL" },
{ R_MDIO_EDCR , "EDCR" },
{ R_CLRLED , "CLRLED" },
{ R_CLRLED0 , "CLRLED0" },
{ R_CLRLED0 , "CLR0" },
{ R_CLRLED1 , "CLRLED1" },
{ R_CLRLED1 , "CLR1" },
{ R_CLRLED2 , "CLRLED2" },
{ R_CLRLED2 , "CLR2" },
{ R_CLRLED3 , "CLRLED3" },
{ R_CLRLED3 , "CLR3" },
{ R_GPS_ALPHA , "ALPHA" },
{ R_GPS_BETA , "BETA" },
{ R_GPS_GAMMA , "GAMMA" },
{ R_GPS_STEP , "STEP" },
{ R_OLEDRGB_CMD , "OLEDRGB" },
{ R_OLEDRGB_CMD , "OLED" },
{ R_OLEDRGB_CDATA , "OLEDRGBA" },
{ R_OLEDRGB_CDATA , "OLEDCA" },
{ R_OLEDRGB_CDATB , "OLEDRGBB" },
{ R_OLEDRGB_CDATB , "OLEDCB" },
{ R_OLEDRGB_DATA , "OLEDRGBD" },
{ R_OLEDRGB_DATA , "ODATA" },
{ R_GPSTB_FREQ , "GPSFREQ" },
{ R_GPSTB_JUMP , "GPSJUMP" },
{ R_GPSTB_ERRHI , "ERRHI" },
{ R_GPSTB_ERRLO , "ERRLO" },
{ R_GPSTB_COUNTHI , "CNTHI" },
{ R_GPSTB_COUNTLO , "CNTLO" },
{ R_GPSTB_STEPHI , "STEPHI" },
{ R_GPSTB_STEPLO , "STEPLO" },
{ R_NET_RXCMD , "RXCMD" },
{ R_NET_RXCMD , "NETRX" },
{ R_NET_TXCMD , "TXCMD" },
{ R_NET_TXCMD , "NETTX" },
{ R_NET_MACHI , "MACHI" },
{ R_NET_MACLO , "MACLO" },
{ R_NET_RXMISS , "NETMISS" },
{ R_NET_RXERR , "NETERR" },
{ R_NET_RXCRC , "NETCRCERR" },
{ R_NET_TXCOL , "NETCOL" },
{ R_CLOCK , "CLOCK" },
{ R_TIMER , "TIMER" },
{ R_STOPWATCH , "STOPWATCH" },
{ R_CKALARM , "ALARM" },
{ R_CKALARM , "CKALARM" },
{ R_BUILDTIME , "BUILDTIME" },
{ R_BUSERR , "BUSERR" },
{ R_PIC , "PIC" },
{ R_PWRCOUNT , "PWRCOUNT" },
{ R_RTCDATE , "RTCDATE" },
{ R_RTCDATE , "DATE" },
{ R_SPIO , "SPIO" },
{ R_SUBSECONDS , "SUBSECONDS" },
{ R_VERSION , "VERSION" },
{ R_NET_RXBUF , "NETRXB" },
{ R_NET_TXBUF , "NETTXB" },
{ R_BKRAM , "RAM" },
{ R_FLASH , "FLASH" },
{ R_SDRAM , "SDRAM" }
};
// REGSDEFS.CPP.INSERT for any bus masters
// And then from the peripherals
// And finally any master REGS.CPP.INSERT tags
#define RAW_NREGS (sizeof(raw_bregs)/sizeof(bregs[0]))
const REGNAME *bregs = raw_bregs;
const int NREGS = RAW_NREGS;
unsigned addrdecode(const char *v) {
if (isalpha(v[0])) {
for(int i=0; i<NREGS; i++)
if (strcasecmp(v, bregs[i].m_name)==0)
return bregs[i].m_addr;
#ifdef R_ZIPCTRL
if (strcasecmp(v, "CPU")==0)
return R_ZIPCTRL;
#endif // R_ZIPCTRL
#ifdef R_ZIPDATA
if (strcasecmp(v, "CPUD")==0)
return R_ZIPDATA;
#endif // R_ZIPDATA
fprintf(stderr, "Unknown register: %s\n", v);
exit(-2);
} else
return strtoul(v, NULL, 0);
}
const char *addrname(const unsigned v) {
for(int i=0; i<NREGS; i++)
if (bregs[i].m_addr == v)
return bregs[i].m_name;
return NULL;
}