Pipeline the parallel prefix adder

[joosthooz]

The delta designs have a limited data width because of timing difficulty in the parallel prefix adder. However, it should be possible to pipeline this. In the last cycle of the pipeline, the final value of the previous addition is known. So it can be added to all the partial sums. (see figure below or also fig. 17 here: http://users.encs.concordia.ca/~asim/COEN_6501/Lecture_Notes/L2_Notes.pdf)

.-. .-. .-. .-.                                     
|1| |2| |3| |4| input                               
'-' '-' '-' '-'                                     
 | \ |   |   |                                      
(r) (+) (r) (r)                                     
 |   | \ |   |                                      
(r) (r) (+) (r)                                     
 |   |   | \ |                                      
(r) (r) (r) (+)                                     
 |   |   |   |                                      
(+) (+) (+) (+) <- (ppp)                            
 |   |   |   |\     ^                               
 |   |   |   | \    | update ppp
 |   |   |   |  '--'                                
 v   v   v   v                                      
.-. .-. .-. .-.                                     
|o| |o| |o| |o| output                              
'-' '-' '-' '-'                                     

(r) = register
(+) = addition (and register)
(ppp) = previous partial prefix (initialize with the start value)