Upgrade to Clash 1.8.1 (ghc-9.6.4)

[prabhupraveen]

Hi Adam,

Trying to get this running with 1.8.1, ghc-9.6.4. Managed to make some changes, but stuck with a few errors.

I have forked this repo to https://github.com/prabhupraveen/clash-riscv and pushed the changes made so far there.

Any help appreciated in making it run. I can raise a PR if required.

Getting following errors after the changes:

root@49897eb7d812:/workspaces/clash/clash-riscv# stack build
Building all executables for clash-riscv once. After a successful build of all of them, only specified executables will be rebuilt.
clash-riscv> build (lib + exe)
Preprocessing library for clash-riscv-0.1.0.0..
Building library for clash-riscv-0.1.0.0..
[ 1 of 10] Compiling Cache.PseudoLRUTree

/workspaces/clash/clash-riscv/src/Cache/PseudoLRUTree.hs:28:28: error: [GHC-58481]
	parse error on input ‘)’
   |
28 | data Step (f :: TyFun Nat *) :: *
   |                            ^
[10 of 10] Compiling Core.Pipeline

/workspaces/clash/clash-riscv/src/Core/Pipeline.hs:194:30: error: [GHC-39999]
	• Could not deduce ‘NFDataX ForwardingSource’
		arising from a use of ‘register’
	  from the context: HiddenClockResetEnable dom
		bound by the type signature for:
				   pipeline :: forall {k1} {k2} (dom :: Domain) (sync :: k1)
									  (gated :: k2).
							   HiddenClockResetEnable dom =>
							   Signal dom FromInstructionMem
							   -> Signal dom FromDataMem
							   -> (Signal dom ToInstructionMem, Signal dom ToDataMem,
								   Signal dom D.PipelineState)
		at src/Core/Pipeline.hs:(48,1)-(52,86)
	• In the expression: register NoForwarding forwardALUOp1_1
	  In an equation for ‘forwardALUOp1_2’:
		  forwardALUOp1_2 = register NoForwarding forwardALUOp1_1
	  In an equation for ‘pipeline’:
		  pipeline fromInstructionMem fromDataMem
			= (ToInstructionMem . unpack . slice d31 d2 . pack <$> nextPC_0, 
			   toDataMem, pipelineState)
			where
				instrStall = instructionStall <$> fromInstructionMem
				pc_0 :: Signal dom (Unsigned 32)
				pc_0 = regEn (- 4) (fmap not stallStage2OrEarlier) nextPC_0
				nextPC_0 :: Signal dom (Unsigned 32)
				....
	|
194 |     forwardALUOp1_2        = register NoForwarding forwardALUOp1_1
	|                              ^^^^^^^^

/workspaces/clash/clash-riscv/src/Core/Pipeline.hs:331:23: error: [GHC-39999]
	• Could not deduce ‘NFDataX DestRegSource’
		arising from a use of ‘register’
	  from the context: HiddenClockResetEnable dom
		bound by the type signature for:
				   pipeline :: forall {k1} {k2} (dom :: Domain) (sync :: k1)
									  (gated :: k2).
							   HiddenClockResetEnable dom =>
							   Signal dom FromInstructionMem
							   -> Signal dom FromDataMem
							   -> (Signal dom ToInstructionMem, Signal dom ToDataMem,
								   Signal dom D.PipelineState)
		at src/Core/Pipeline.hs:(48,1)-(52,86)
	• In the expression: register SourceALU destRegSource_3
	  In an equation for ‘destRegSource_4’:
		  destRegSource_4 = register SourceALU destRegSource_3
	  In an equation for ‘pipeline’:
		  pipeline fromInstructionMem fromDataMem
			= (ToInstructionMem . unpack . slice d31 d2 . pack <$> nextPC_0, 
			   toDataMem, pipelineState)
			where
				instrStall = instructionStall <$> fromInstructionMem
				pc_0 :: Signal dom (Unsigned 32)
				pc_0 = regEn (- 4) (fmap not stallStage2OrEarlier) nextPC_0
				nextPC_0 :: Signal dom (Unsigned 32)
				....
	|
331 |     destRegSource_4 = register SourceALU destRegSource_3
	|                       ^^^^^^^^

Error: [S-7282]
	   Stack failed to execute the build plan.
	   
	   While executing the build plan, Stack encountered the error:
	   
	   [S-7011]
	   While building package clash-riscv-0.1.0.0 (scroll up to its section to see the error) using:
	   /root/.stack/setup-exe-cache/x86_64-linux-tinfo6-libc6-pre232/Cabal-simple_6HauvNHV_3.10.1.0_ghc-9.6.4 --verbose=1 --builddir=.stack-work/dist/x86_64-linux-tinfo6-libc6-pre232/ghc-9.6.4 build lib:clash-riscv exe:clash exe:clashi --ghc-options " -fdiagnostics-color=always"
	   Process exited with code: ExitFailure 1