Freeing the sintax tree ?

[tarberd]

I'm getting confised by the usage of your parser. After populating yy_verilog_source_tree using the provided functions described on https://codedocs.xyz/ben-marshall/verilog-parser/group__parser-api.html, how can I free all the memory allocated by your library?

@ben-marshall

[ben-marshall]

So, big caveat here: The AST is not a nice piece of work. I'm not proud of it.

Unfortunately, I did not build in functions for freeing the AST. You have to manually walk to each leaf and very carefully free everything on the way back up.

It was always my intention to go back and re-do the AST, but I never got the time to do it properly. What is it you are using the parser for? If there is only a small section of the AST you are interested in, my advice would probably be to nuke all of my AST code and only write the bits you need yourself. It will probably be easier than trying to de-mangle my code!

Sorry this isn't the answer you were looking for. Let me know if I can help any more!

[tarberd]

So, I'am working on an opensource eda librarie called ophidian.

The way we used your library to construct our Verilog object was king of messy and I am trying to refactor it, if you want to take a look at VerilogParser.h and VerilogParser.cpp.

I would be happy to help you with anything although I've never coded a parser. This layer is crucial for working on eda argorithims.

I need the verilog for in order to build the netlist graph topology btw. To later use it by placement and routing and everything else.

[ben-marshall]

So, I'am working on an opensource eda librarie called ophidian.

Wow, that looks like a fantastic project!

I would be happy to help you with anything although I've never coded a parser. This layer is crucial for working on eda argorithims.

Indeed. This is exactly why I wrote the parser, I wanted to enable projects like yours. Unfortunately, though I am happy with the actual parser, the AST component is not so good. I wrote this when I had substantially more free time, and have been wanting to revisit it for a while now to tidy it up.

Given you seem to be making good use of the parser so far, I might look at trying to re-write the AST in a more sensible / best practice kind of way. It won't happen very quickly, but I can take a look. Once I know what is involved, I am more than happy to parcel the work out into something we can share?

I need the verilog for in order to build the netlist graph topology btw.

I see. Does that mean you are only using it to parse netlist level verilog, or do you need the entire behavioral syntax as well?

[tarberd]

I see. Does that mean you are only using it to parse netlist level verilog, or do you need the entire behavioral syntax as well?

Only the netlist level. We supose that our user already have the verilog generated by the logic synthesis together with some standard cells library.